diff options
author | Thomas Wood <thomas.wood@intel.com> | 2014-11-28 11:02:44 +0000 |
---|---|---|
committer | Thomas Wood <thomas.wood@intel.com> | 2014-12-04 16:07:55 +0000 |
commit | b2ac2642a9b5448761086bdb8ae1a1e2974b3995 (patch) | |
tree | 48c6e835a0b62de686a6889847c3176cd77637fe /tests | |
parent | 029dee797965357dbcbe5a097731701e4d965d82 (diff) |
tests: add more test descriptions
Add more test descriptions based on exiting comments.
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Diffstat (limited to 'tests')
66 files changed, 167 insertions, 4 deletions
diff --git a/tests/drm_vma_limiter.c b/tests/drm_vma_limiter.c index e1381fe3d..bb7102f18 100644 --- a/tests/drm_vma_limiter.c +++ b/tests/drm_vma_limiter.c @@ -50,6 +50,8 @@ struct intel_batchbuffer *batch; * this checks whether they actually work. */ +IGT_TEST_DESCRIPTION("Check whether the libdrm vma limiter works."); + /* we do both cpu and gtt maps, so only need half of 64k to exhaust */ #define BO_ARRAY_SIZE 35000 drm_intel_bo *bos[BO_ARRAY_SIZE]; diff --git a/tests/gem_bad_length.c b/tests/gem_bad_length.c index 11cc197a0..29b392530 100644 --- a/tests/gem_bad_length.c +++ b/tests/gem_bad_length.c @@ -38,8 +38,10 @@ #include "ioctl_wrappers.h" #include "drmtest.h" +IGT_TEST_DESCRIPTION("Test minimal bo_create and batchbuffer exec."); + /* - * Testcase: Minmal bo_create and batchbuffer exec + * Testcase: Minimal bo_create and batchbuffer exec * * Originally this caught an kernel oops due to the unchecked assumption that * objects have size > 0. diff --git a/tests/gem_bad_reloc.c b/tests/gem_bad_reloc.c index df0100fa4..cf1f2faf6 100644 --- a/tests/gem_bad_reloc.c +++ b/tests/gem_bad_reloc.c @@ -42,6 +42,9 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Simulates SNA behaviour using negative self-relocations" + " for STATE_BASE_ADDRESS command packets."); + #define USE_LUT (1 << 12) /* Simulates SNA behaviour using negative self-relocations for diff --git a/tests/gem_caching.c b/tests/gem_caching.c index b7f4bfb08..2fad0ec9e 100644 --- a/tests/gem_caching.c +++ b/tests/gem_caching.c @@ -45,6 +45,9 @@ #include "intel_chipset.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test snoop consistency when touching partial" + " cachelines."); + /* * Testcase: snoop consistency when touching partial cachelines * diff --git a/tests/gem_concurrent_blit.c b/tests/gem_concurrent_blit.c index 7d8d628d5..4ce5ef0d5 100644 --- a/tests/gem_concurrent_blit.c +++ b/tests/gem_concurrent_blit.c @@ -55,6 +55,9 @@ #include "intel_chipset.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test of pread/pwrite behavior when writing to active" + " buffers."); + int fd, devid, gen; struct intel_batchbuffer *batch; diff --git a/tests/gem_cpu_reloc.c b/tests/gem_cpu_reloc.c index 1413ebfca..c67907ad6 100644 --- a/tests/gem_cpu_reloc.c +++ b/tests/gem_cpu_reloc.c @@ -64,6 +64,8 @@ #include "intel_chipset.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test the relocations through the CPU domain."); + static uint32_t use_blt; static void copy(int fd, uint32_t batch, uint32_t src, uint32_t dst) diff --git a/tests/gem_cs_prefetch.c b/tests/gem_cs_prefetch.c index e64b224bd..700883c8c 100644 --- a/tests/gem_cs_prefetch.c +++ b/tests/gem_cs_prefetch.c @@ -54,6 +54,8 @@ #include "intel_chipset.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test the CS prefetch behaviour on batches."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; diff --git a/tests/gem_cs_tlb.c b/tests/gem_cs_tlb.c index c203e318b..5b8b993ce 100644 --- a/tests/gem_cs_tlb.c +++ b/tests/gem_cs_tlb.c @@ -54,6 +54,8 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Check whether we correctly invalidate the cs tlb."); + #define LOCAL_I915_EXEC_VEBOX (4<<0) #define BATCH_SIZE (1024*1024) diff --git a/tests/gem_ctx_bad_destroy.c b/tests/gem_ctx_bad_destroy.c index 77091314b..d848265c7 100644 --- a/tests/gem_ctx_bad_destroy.c +++ b/tests/gem_ctx_bad_destroy.c @@ -36,6 +36,8 @@ #include "ioctl_wrappers.h" #include "drmtest.h" +IGT_TEST_DESCRIPTION("Negative test cases for destroy contexts."); + struct local_drm_i915_context_destroy { __u32 ctx_id; __u32 pad; diff --git a/tests/gem_ctx_bad_exec.c b/tests/gem_ctx_bad_exec.c index f0bb0fc9c..36afd7d86 100644 --- a/tests/gem_ctx_bad_exec.c +++ b/tests/gem_ctx_bad_exec.c @@ -45,6 +45,9 @@ #include "ioctl_wrappers.h" #include "drmtest.h" +IGT_TEST_DESCRIPTION("Test that context cannot be submitted to unsupported" + " rings."); + /* Copied from gem_exec_nop.c */ static int exec(int fd, uint32_t handle, int ring, int ctx_id) { diff --git a/tests/gem_ctx_basic.c b/tests/gem_ctx_basic.c index b8b01c03e..2d866b3ee 100644 --- a/tests/gem_ctx_basic.c +++ b/tests/gem_ctx_basic.c @@ -47,6 +47,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Basic test for memory and refcount leaks."); + /* options */ int num_contexts = 10; int uncontexted = 0; /* test only context create/destroy */ diff --git a/tests/gem_ctx_exec.c b/tests/gem_ctx_exec.c index da7412cf1..7a6ed9b1f 100644 --- a/tests/gem_ctx_exec.c +++ b/tests/gem_ctx_exec.c @@ -48,6 +48,8 @@ #include "igt_aux.h" #include "igt_debugfs.h" +IGT_TEST_DESCRIPTION("Test basic context switch functionality."); + struct local_drm_i915_gem_context_destroy { __u32 ctx_id; __u32 pad; diff --git a/tests/gem_double_irq_loop.c b/tests/gem_double_irq_loop.c index f9dab7c78..a43fd1a9d 100644 --- a/tests/gem_double_irq_loop.c +++ b/tests/gem_double_irq_loop.c @@ -53,6 +53,8 @@ static drm_intel_bo *target_buffer, *blt_bo; * on the second batch. This hopefully catches races in our irq acknowledgement. */ +IGT_TEST_DESCRIPTION("Basic check for missed IRQs on blt ring."); + #define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1) #define MI_DO_COMPARE (1<<21) diff --git a/tests/gem_dummy_reloc_loop.c b/tests/gem_dummy_reloc_loop.c index 7a9714032..335700d31 100644 --- a/tests/gem_dummy_reloc_loop.c +++ b/tests/gem_dummy_reloc_loop.c @@ -62,6 +62,7 @@ static drm_intel_bo *mbuffer[NUM_FD]; * at hitting the missed irq bug that's worked around with the HWSTAM irq write. */ +IGT_TEST_DESCRIPTION("Check ring<->cpu sync using a dummy reloc."); #define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1) #define MI_DO_COMPARE (1<<21) diff --git a/tests/gem_evict_alignment.c b/tests/gem_evict_alignment.c index 86676b05e..43d39ed55 100644 --- a/tests/gem_evict_alignment.c +++ b/tests/gem_evict_alignment.c @@ -49,6 +49,9 @@ #include "intel_chipset.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Run a couple of big batches to force the unbind on" + " misalignment code."); + #define HEIGHT 256 #define WIDTH 1024 diff --git a/tests/gem_evict_everything.c b/tests/gem_evict_everything.c index fae89032f..f108da3a9 100644 --- a/tests/gem_evict_everything.c +++ b/tests/gem_evict_everything.c @@ -48,6 +48,9 @@ #include "eviction_common.c" +IGT_TEST_DESCRIPTION("Run a couple of big batches to force the eviction" + " code."); + #define HEIGHT 256 #define WIDTH 1024 diff --git a/tests/gem_exec_bad_domains.c b/tests/gem_exec_bad_domains.c index 99012815f..818e58532 100644 --- a/tests/gem_exec_bad_domains.c +++ b/tests/gem_exec_bad_domains.c @@ -46,6 +46,9 @@ * If it does not, it'll oops somewhen later on because we don't expect that. */ +IGT_TEST_DESCRIPTION("Test whether the kernel rejects relocations with non-gpu" + " domains."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; diff --git a/tests/gem_exec_big.c b/tests/gem_exec_big.c index b82774fb8..652c8f15c 100644 --- a/tests/gem_exec_big.c +++ b/tests/gem_exec_big.c @@ -47,6 +47,9 @@ #include "ioctl_wrappers.h" #include "drmtest.h" +IGT_TEST_DESCRIPTION("Run a large nop batch to stress test the error capture" + " code."); + #define BATCH_SIZE (1024*1024) static void exec(int fd, uint32_t handle, uint32_t reloc_ofs) diff --git a/tests/gem_exec_faulting_reloc.c b/tests/gem_exec_faulting_reloc.c index acd703b60..9f1211261 100644 --- a/tests/gem_exec_faulting_reloc.c +++ b/tests/gem_exec_faulting_reloc.c @@ -48,6 +48,9 @@ * To be really evil, use a gtt mmap for them. */ +IGT_TEST_DESCRIPTION("Submit patches with relocations in memory that will" + " fault."); + #define OBJECT_SIZE 16384 #define COPY_BLT_CMD_NOLEN (2<<29|0x53<<22) diff --git a/tests/gem_exec_lut_handle.c b/tests/gem_exec_lut_handle.c index 6ee75274f..c2d490f94 100644 --- a/tests/gem_exec_lut_handle.c +++ b/tests/gem_exec_lut_handle.c @@ -25,7 +25,7 @@ * */ -/* Exercises the basic execbuffer using theh andle LUT interface */ +/* Exercises the basic execbuffer using the handle LUT interface */ #include <stdlib.h> #include <stdio.h> @@ -39,6 +39,9 @@ #include "ioctl_wrappers.h" #include "drmtest.h" +IGT_TEST_DESCRIPTION("Exercises the basic execbuffer using the handle LUT" + " interface."); + #define BATCH_SIZE (1024*1024) #define LOCAL_I915_EXEC_NO_RELOC (1<<11) diff --git a/tests/gem_fenced_exec_thrash.c b/tests/gem_fenced_exec_thrash.c index 85ead308e..75f251cc3 100644 --- a/tests/gem_fenced_exec_thrash.c +++ b/tests/gem_fenced_exec_thrash.c @@ -43,6 +43,8 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test execbuf fence accounting."); + #define WIDTH 1024 #define HEIGHT 1024 #define OBJECT_SIZE (4*WIDTH*HEIGHT) diff --git a/tests/gem_flink_race.c b/tests/gem_flink_race.c index a1dc85dd4..c2a5d81c5 100644 --- a/tests/gem_flink_race.c +++ b/tests/gem_flink_race.c @@ -38,6 +38,8 @@ #include "intel_bufmgr.h" #include "igt_debugfs.h" +IGT_TEST_DESCRIPTION("Check for flink/open vs. gem close races."); + /* Testcase: check for flink/open vs. gem close races * * The gem flink open ioctl had a little race with gem close which could result diff --git a/tests/gem_gtt_cpu_tlb.c b/tests/gem_gtt_cpu_tlb.c index 953070c0c..a019061c8 100644 --- a/tests/gem_gtt_cpu_tlb.c +++ b/tests/gem_gtt_cpu_tlb.c @@ -44,6 +44,9 @@ #include "drmtest.h" #include "intel_io.h" +IGT_TEST_DESCRIPTION("Check whether gtt tlbs for cpu access are correctly" + " invalidated."); + #define OBJ_SIZE (1024*1024) #define PAGE_SIZE 4096 diff --git a/tests/gem_hangcheck_forcewake.c b/tests/gem_hangcheck_forcewake.c index ec74c511b..f274fabb4 100644 --- a/tests/gem_hangcheck_forcewake.c +++ b/tests/gem_hangcheck_forcewake.c @@ -41,6 +41,9 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Provoke the hangcheck timer on an otherwise idle" + " system."); + /* * Testcase: Provoke the hangcheck timer on an otherwise idle system * diff --git a/tests/gem_linear_blits.c b/tests/gem_linear_blits.c index cbd115678..13c2ab75b 100644 --- a/tests/gem_linear_blits.c +++ b/tests/gem_linear_blits.c @@ -50,6 +50,9 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test doing many blits with a working set larger than the" + " aperture size."); + #define WIDTH 512 #define HEIGHT 512 diff --git a/tests/gem_lut_handle.c b/tests/gem_lut_handle.c index d3f6f7325..7fc72f1ac 100644 --- a/tests/gem_lut_handle.c +++ b/tests/gem_lut_handle.c @@ -25,7 +25,7 @@ * */ -/* Exercises the basic execbuffer using theh andle LUT interface */ +/* Exercises the basic execbuffer using the handle LUT interface */ #include <stdlib.h> #include <stdio.h> @@ -39,6 +39,9 @@ #include "ioctl_wrappers.h" #include "drmtest.h" +IGT_TEST_DESCRIPTION("Exercises the basic execbuffer using the handle LUT" + " interface."); + #define BATCH_SIZE (1024*1024) #define LOCAL_I915_EXEC_HANDLE_LUT (1<<12) diff --git a/tests/gem_madvise.c b/tests/gem_madvise.c index f95fbda3f..58ab629f8 100644 --- a/tests/gem_madvise.c +++ b/tests/gem_madvise.c @@ -39,6 +39,9 @@ #include "ioctl_wrappers.h" #include "drmtest.h" +IGT_TEST_DESCRIPTION("Checks that the kernel reports EFAULT when trying to use" + " purged bo."); + #define OBJECT_SIZE (1024*1024) /* Testcase: checks that the kernel reports EFAULT when trying to use purged bo diff --git a/tests/gem_media_fill.c b/tests/gem_media_fill.c index 3067317fc..ade56f255 100644 --- a/tests/gem_media_fill.c +++ b/tests/gem_media_fill.c @@ -49,6 +49,9 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Basic test for the media_fill() function, a very simple" + " workload for the Media pipeline."); + #define WIDTH 64 #define STRIDE (WIDTH) #define HEIGHT 64 diff --git a/tests/gem_mmap_offset_exhaustion.c b/tests/gem_mmap_offset_exhaustion.c index 914fe6ebb..b0310501b 100644 --- a/tests/gem_mmap_offset_exhaustion.c +++ b/tests/gem_mmap_offset_exhaustion.c @@ -38,6 +38,9 @@ #include "ioctl_wrappers.h" #include "drmtest.h" +IGT_TEST_DESCRIPTION("Checks whether the kernel handles mmap offset exhaustion" + " correctly."); + #define OBJECT_SIZE (1024*1024) /* Testcase: checks whether the kernel handles mmap offset exhaustion correctly diff --git a/tests/gem_multi_bsd_sync_loop.c b/tests/gem_multi_bsd_sync_loop.c index dec738b6b..0766eb616 100644 --- a/tests/gem_multi_bsd_sync_loop.c +++ b/tests/gem_multi_bsd_sync_loop.c @@ -43,6 +43,8 @@ #include "i830_reg.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Basic check of ring<->ring sync using a dummy reloc."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; static drm_intel_bo *target_buffer; diff --git a/tests/gem_non_secure_batch.c b/tests/gem_non_secure_batch.c index a1e875dfe..d00ce4569 100644 --- a/tests/gem_non_secure_batch.c +++ b/tests/gem_non_secure_batch.c @@ -42,6 +42,8 @@ #include "intel_io.h" #include "i830_reg.h" +IGT_TEST_DESCRIPTION("Basic check of non-secure batches."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; diff --git a/tests/gem_partial_pwrite_pread.c b/tests/gem_partial_pwrite_pread.c index b9ffeec1c..0be749c1e 100644 --- a/tests/gem_partial_pwrite_pread.c +++ b/tests/gem_partial_pwrite_pread.c @@ -42,6 +42,9 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test pwrite/pread consistency when touching partial" + " cachelines."); + /* * Testcase: pwrite/pread consistency when touching partial cachelines * diff --git a/tests/gem_persistent_relocs.c b/tests/gem_persistent_relocs.c index 585eda8d3..cab52a871 100644 --- a/tests/gem_persistent_relocs.c +++ b/tests/gem_persistent_relocs.c @@ -46,6 +46,8 @@ #include "igt_debugfs.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test persistent relocations as used by uxa/libva."); + /* * Testcase: Persistent relocations as used by uxa/libva * diff --git a/tests/gem_pin.c b/tests/gem_pin.c index 91e1456a1..b35496e78 100644 --- a/tests/gem_pin.c +++ b/tests/gem_pin.c @@ -44,6 +44,8 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Exercises pinning of small buffer objects."); + #define COPY_BLT_CMD (2<<29|0x53<<22|0x6) #define BLT_WRITE_ALPHA (1<<21) #define BLT_WRITE_RGB (1<<20) diff --git a/tests/gem_pipe_control_store_loop.c b/tests/gem_pipe_control_store_loop.c index 86681f2aa..86ee4050f 100644 --- a/tests/gem_pipe_control_store_loop.c +++ b/tests/gem_pipe_control_store_loop.c @@ -47,6 +47,8 @@ #include "intel_chipset.h" #include "intel_io.h" +IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; uint32_t devid; diff --git a/tests/gem_pread_after_blit.c b/tests/gem_pread_after_blit.c index 0b8bfa6cc..a56e6fed5 100644 --- a/tests/gem_pread_after_blit.c +++ b/tests/gem_pread_after_blit.c @@ -51,6 +51,9 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test pread behavior when getting values out of" + " just-drawn-to buffers."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; static const int width = 512, height = 512; diff --git a/tests/gem_reloc_overflow.c b/tests/gem_reloc_overflow.c index 06a315fd4..ea591711c 100644 --- a/tests/gem_reloc_overflow.c +++ b/tests/gem_reloc_overflow.c @@ -48,6 +48,8 @@ #include "drmtest.h" #include "intel_io.h" +IGT_TEST_DESCRIPTION("Check that kernel relocation overflows are caught."); + /* * Testcase: Kernel relocation overflows are caught. */ diff --git a/tests/gem_reloc_vs_gpu.c b/tests/gem_reloc_vs_gpu.c index e249757d3..cc1b954b6 100644 --- a/tests/gem_reloc_vs_gpu.c +++ b/tests/gem_reloc_vs_gpu.c @@ -46,6 +46,8 @@ #include "igt_debugfs.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test kernel relocations vs. gpu races."); + /* * Testcase: Kernel relocations vs. gpu races * diff --git a/tests/gem_render_copy.c b/tests/gem_render_copy.c index 094816c92..006b6f503 100644 --- a/tests/gem_render_copy.c +++ b/tests/gem_render_copy.c @@ -52,6 +52,8 @@ #include "intel_chipset.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Basic test for the render_copy() function."); + #define WIDTH 512 #define STRIDE (WIDTH*4) #define HEIGHT 512 diff --git a/tests/gem_render_copy_redux.c b/tests/gem_render_copy_redux.c index 6fc82df9a..43d4c5af8 100644 --- a/tests/gem_render_copy_redux.c +++ b/tests/gem_render_copy_redux.c @@ -54,6 +54,8 @@ #include "intel_chipset.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Advanced test for the render_copy() function."); + #define WIDTH 512 #define STRIDE (WIDTH*4) #define HEIGHT 512 diff --git a/tests/gem_ring_sync_copy.c b/tests/gem_ring_sync_copy.c index 725718873..f5ffddc32 100644 --- a/tests/gem_ring_sync_copy.c +++ b/tests/gem_ring_sync_copy.c @@ -55,6 +55,8 @@ #include "intel_batchbuffer.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Ensure inter-ring dependencies are respected."); + #define WIDTH 512 #define HEIGHT 512 #define NUM_BUSY_BUFFERS 32 diff --git a/tests/gem_ring_sync_loop.c b/tests/gem_ring_sync_loop.c index fc510e4be..4b88530b0 100644 --- a/tests/gem_ring_sync_loop.c +++ b/tests/gem_ring_sync_loop.c @@ -42,6 +42,8 @@ #include "i830_reg.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Basic check of ring<->ring sync using a dummy reloc."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; static drm_intel_bo *target_buffer; diff --git a/tests/gem_seqno_wrap.c b/tests/gem_seqno_wrap.c index 51fd88ce8..be4ab3dd3 100644 --- a/tests/gem_seqno_wrap.c +++ b/tests/gem_seqno_wrap.c @@ -51,6 +51,9 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Runs blitcopy -> rendercopy with multiple buffers over" + " wrap boundary."); + static int devid; static int card_index = 0; static uint32_t last_seqno = 0; diff --git a/tests/gem_set_tiling_vs_blt.c b/tests/gem_set_tiling_vs_blt.c index 4de325cd5..ab2f81120 100644 --- a/tests/gem_set_tiling_vs_blt.c +++ b/tests/gem_set_tiling_vs_blt.c @@ -61,6 +61,9 @@ #include "intel_chipset.h" #include "intel_io.h" +IGT_TEST_DESCRIPTION("Check for proper synchronization of tiling changes vs." + " tiled gpu access."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; uint32_t devid; diff --git a/tests/gem_set_tiling_vs_gtt.c b/tests/gem_set_tiling_vs_gtt.c index e0ef2b7bb..006f50a00 100644 --- a/tests/gem_set_tiling_vs_gtt.c +++ b/tests/gem_set_tiling_vs_gtt.c @@ -40,6 +40,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Check set_tiling vs gtt mmap coherency."); + #define OBJECT_SIZE (1024*1024) #define TEST_STRIDE (1024*4) diff --git a/tests/gem_set_tiling_vs_pwrite.c b/tests/gem_set_tiling_vs_pwrite.c index cf5aaeb09..a4bdc64f1 100644 --- a/tests/gem_set_tiling_vs_pwrite.c +++ b/tests/gem_set_tiling_vs_pwrite.c @@ -39,6 +39,8 @@ #include "drmtest.h" #include "intel_io.h" +IGT_TEST_DESCRIPTION("Check set_tiling vs pwrite coherency."); + #define OBJECT_SIZE (1024*1024) #define TEST_STRIDE (1024*4) diff --git a/tests/gem_storedw_loop_blt.c b/tests/gem_storedw_loop_blt.c index 43750cc3e..44e46a84a 100644 --- a/tests/gem_storedw_loop_blt.c +++ b/tests/gem_storedw_loop_blt.c @@ -42,6 +42,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Basic blitter MI check using MI_STORE_DATA_IMM."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; static drm_intel_bo *target_buffer; diff --git a/tests/gem_storedw_loop_bsd.c b/tests/gem_storedw_loop_bsd.c index d5451be34..e534c16fc 100644 --- a/tests/gem_storedw_loop_bsd.c +++ b/tests/gem_storedw_loop_bsd.c @@ -42,6 +42,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Basic bsd MI check using MI_STORE_DATA_IMM."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; static drm_intel_bo *target_buffer; diff --git a/tests/gem_storedw_loop_render.c b/tests/gem_storedw_loop_render.c index e1d3dadb8..48fb6d4ea 100644 --- a/tests/gem_storedw_loop_render.c +++ b/tests/gem_storedw_loop_render.c @@ -42,6 +42,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Basic render MI check using MI_STORE_DATA_IMM."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; static drm_intel_bo *target_buffer; diff --git a/tests/gem_storedw_loop_vebox.c b/tests/gem_storedw_loop_vebox.c index 5e5536f99..8643dd395 100644 --- a/tests/gem_storedw_loop_vebox.c +++ b/tests/gem_storedw_loop_vebox.c @@ -41,6 +41,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Basic vebox MI check using MI_STORE_DATA_IMM."); + #define LOCAL_I915_EXEC_VEBOX (4<<0) static drm_intel_bufmgr *bufmgr; diff --git a/tests/gem_stress.c b/tests/gem_stress.c index ab2cd0eb4..6e3a64c4f 100644 --- a/tests/gem_stress.c +++ b/tests/gem_stress.c @@ -69,6 +69,8 @@ #include "intel_chipset.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("General gem coherency test."); + #define CMD_POLY_STIPPLE_OFFSET 0x7906 #define DUCTAPE 0xdead0001 diff --git a/tests/gem_threaded_access_tiled.c b/tests/gem_threaded_access_tiled.c index 3752a1f64..3a5921f3f 100644 --- a/tests/gem_threaded_access_tiled.c +++ b/tests/gem_threaded_access_tiled.c @@ -34,6 +34,8 @@ #include "ioctl_wrappers.h" #include "intel_bufmgr.h" +IGT_TEST_DESCRIPTION("Check parallel access to tiled memory."); + /* Testcase: check parallel access to tiled memory * * Parallel access to tiled memory caused sigbus diff --git a/tests/gem_tiled_blits.c b/tests/gem_tiled_blits.c index 0f883286e..3fceb8117 100644 --- a/tests/gem_tiled_blits.c +++ b/tests/gem_tiled_blits.c @@ -58,6 +58,9 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test doing many tiled blits, with a working set larger" + " than the aperture size."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; static int width = 512, height = 512; diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c index cf8f48d68..8dea82e48 100644 --- a/tests/gem_tiled_partial_pwrite_pread.c +++ b/tests/gem_tiled_partial_pwrite_pread.c @@ -42,6 +42,9 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test pwrite/pread consistency when touching partial" + " cachelines."); + /* * Testcase: pwrite/pread consistency when touching partial cachelines * diff --git a/tests/gem_tiled_pread.c b/tests/gem_tiled_pread.c index d99b4eab8..fdc517332 100644 --- a/tests/gem_tiled_pread.c +++ b/tests/gem_tiled_pread.c @@ -50,6 +50,10 @@ #include "intel_io.h" #include "intel_chipset.h" + +IGT_TEST_DESCRIPTION("Test pread behavior on tiled objects with respect to the" + " reported swizzling value."); + #define WIDTH 512 #define HEIGHT 512 static uint32_t linear[WIDTH * HEIGHT]; diff --git a/tests/gem_tiled_pread_pwrite.c b/tests/gem_tiled_pread_pwrite.c index 5ab467835..3d8fdc9f9 100644 --- a/tests/gem_tiled_pread_pwrite.c +++ b/tests/gem_tiled_pread_pwrite.c @@ -36,7 +36,7 @@ */ /* - * Testcase: Test swizzling by testing pwrite does the invers of pread + * Testcase: Test swizzling by testing pwrite does the inverse of pread * * Together with the explicit pread testcase, this should cover our swizzle * handling. @@ -61,6 +61,9 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Test swizzling by testing pwrite does the inverse of" + " pread."); + #define WIDTH 512 #define HEIGHT 512 static uint32_t linear[WIDTH * HEIGHT]; diff --git a/tests/gem_tiled_swapping.c b/tests/gem_tiled_swapping.c index 11bb245b2..3fac52f4f 100644 --- a/tests/gem_tiled_swapping.c +++ b/tests/gem_tiled_swapping.c @@ -62,6 +62,8 @@ #include "intel_io.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Exercise swizzle code for swapping."); + #define WIDTH 512 #define HEIGHT 512 #define LINEAR_DWORDS (4 * WIDTH * HEIGHT) diff --git a/tests/gem_tiled_wb.c b/tests/gem_tiled_wb.c index fdf79e3c2..b6efd6eef 100644 --- a/tests/gem_tiled_wb.c +++ b/tests/gem_tiled_wb.c @@ -47,6 +47,10 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("This is a test of write-combining mmap's behavior on" + " tiled objects with respect to the reported swizzling" + " value."); + #define WIDTH 512 #define HEIGHT 512 #define SIZE (WIDTH*HEIGHT*sizeof(uint32_t)) diff --git a/tests/gem_tiling_max_stride.c b/tests/gem_tiling_max_stride.c index 4d0553d4a..fce1ac7d8 100644 --- a/tests/gem_tiling_max_stride.c +++ b/tests/gem_tiling_max_stride.c @@ -41,6 +41,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Check that max fence stride works."); + static void do_test_invalid_tiling(int fd, uint32_t handle, int tiling, int stride) { igt_assert(__gem_set_tiling(fd, handle, tiling, tiling ? stride : 0) == -EINVAL); diff --git a/tests/gem_unfence_active_buffers.c b/tests/gem_unfence_active_buffers.c index fffe3a798..125568ed0 100644 --- a/tests/gem_unfence_active_buffers.c +++ b/tests/gem_unfence_active_buffers.c @@ -55,6 +55,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Check for use-after-free in the fence stealing code."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; uint32_t devid; diff --git a/tests/gem_unref_active_buffers.c b/tests/gem_unref_active_buffers.c index 7a1bc9370..8c8efaadd 100644 --- a/tests/gem_unref_active_buffers.c +++ b/tests/gem_unref_active_buffers.c @@ -48,6 +48,8 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Test unreferencing of active buffers."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; static drm_intel_bo *load_bo; diff --git a/tests/gem_write_read_ring_switch.c b/tests/gem_write_read_ring_switch.c index f3407f94e..da579dac7 100644 --- a/tests/gem_write_read_ring_switch.c +++ b/tests/gem_write_read_ring_switch.c @@ -43,6 +43,8 @@ #include "i830_reg.h" #include "igt_aux.h" +IGT_TEST_DESCRIPTION("Check read/write syncpoints when switching rings."); + #define LOCAL_I915_EXEC_VEBOX (4<<0) static drm_intel_bufmgr *bufmgr; diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c index e9748077e..01299c52c 100644 --- a/tests/gen7_forcewake_mt.c +++ b/tests/gen7_forcewake_mt.c @@ -41,6 +41,9 @@ #include "intel_io.h" #include "intel_chipset.h" +IGT_TEST_DESCRIPTION("Exercise a suspect workaround required for" + " FORCEWAKE_MT."); + #define FORCEWAKE_MT 0xa188 struct thread { diff --git a/tests/kms_flip_tiling.c b/tests/kms_flip_tiling.c index 5c67398fc..9bc085b29 100644 --- a/tests/kms_flip_tiling.c +++ b/tests/kms_flip_tiling.c @@ -34,6 +34,9 @@ #include "igt_kms.h" #include "ioctl_wrappers.h" +IGT_TEST_DESCRIPTION("Test that a page flip from a tiled buffer to a linear" + " one works correctly."); + typedef struct { int drm_fd; igt_display_t display; diff --git a/tests/kms_force_connector.c b/tests/kms_force_connector.c index 34c33b04d..d481dbf4e 100644 --- a/tests/kms_force_connector.c +++ b/tests/kms_force_connector.c @@ -27,6 +27,9 @@ #include "drmtest.h" #include "igt_edid.h" +IGT_TEST_DESCRIPTION("Check the debugfs force connector/edid features work" + " correctly."); + int main (int argc, char **argv) { diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c index dd9c29331..9cb078060 100644 --- a/tests/prime_self_import.c +++ b/tests/prime_self_import.c @@ -48,6 +48,9 @@ #include "drmtest.h" #include "igt_debugfs.h" +IGT_TEST_DESCRIPTION("Check whether prime import/export works on the same" + " device."); + #define BO_SIZE (16*1024) static char counter; |