diff options
| author | Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> | 2024-05-15 14:19:43 +0200 |
|---|---|---|
| committer | Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> | 2024-05-16 06:14:58 +0200 |
| commit | 7e61c8e8c1827af71a1ce19efa7ddc94222b25fd (patch) | |
| tree | abc062cc3ac31a37721b4a10290ed0598f68f070 /lib | |
| parent | c6ebaf8f9f620f4ae4cd0beb0072ff536d3c2588 (diff) | |
lib/intel_bufops: Start supporting compression on Xe2+
Xe2+ uses unified compression where PAT index determines using
compressed pages so lets add support of that to intel-buf. It is
necessary to run render-copy with compression on those platforms.
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Link: https://lore.kernel.org/r/20240515121949.245280-4-zbigniew.kempczynski@intel.com
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/intel_bufops.c | 31 |
1 files changed, 27 insertions, 4 deletions
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c index 7118272e5..52a5f322e 100644 --- a/lib/intel_bufops.c +++ b/lib/intel_bufops.c @@ -934,8 +934,14 @@ static void __intel_buf_init(struct buf_ops *bops, if (__gem_create_in_memory_regions(bops->fd, &buf->handle, &bo_size, region)) igt_assert_eq(__gem_create(bops->fd, &bo_size, &buf->handle), 0); } else { + uint16_t cpu_caching = __xe_default_cpu_caching(bops->fd, region, 0); + + if (AT_LEAST_GEN(bops->devid, 20) && compression) + cpu_caching = DRM_XE_GEM_CPU_CACHING_WC; + bo_size = ALIGN(bo_size, xe_get_default_alignment(bops->fd)); - buf->handle = xe_bo_create(bops->fd, 0, bo_size, region, 0); + buf->handle = xe_bo_create_caching(bops->fd, 0, bo_size, region, 0, + cpu_caching); } } @@ -970,11 +976,16 @@ void intel_buf_init(struct buf_ops *bops, uint32_t tiling, uint32_t compression) { uint64_t region; + uint8_t pat_index = DEFAULT_PAT_INDEX; + + if (compression && AT_LEAST_GEN(bops->devid, 20)) + pat_index = intel_get_pat_idx_uc_comp(bops->fd); region = bops->driver == INTEL_DRIVER_I915 ? I915_SYSTEM_MEMORY : system_memory(bops->fd); __intel_buf_init(bops, 0, buf, width, height, bpp, alignment, - tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX, + tiling, compression, 0, 0, region, + pat_index, DEFAULT_MOCS_INDEX); intel_buf_set_ownership(buf, true); @@ -991,8 +1002,14 @@ void intel_buf_init_in_region(struct buf_ops *bops, uint32_t tiling, uint32_t compression, uint64_t region) { + uint8_t pat_index = DEFAULT_PAT_INDEX; + + if (compression && AT_LEAST_GEN(bops->devid, 20)) + pat_index = intel_get_pat_idx_uc_comp(bops->fd); + __intel_buf_init(bops, 0, buf, width, height, bpp, alignment, - tiling, compression, 0, 0, region, DEFAULT_PAT_INDEX, + tiling, compression, 0, 0, region, + pat_index, DEFAULT_MOCS_INDEX); intel_buf_set_ownership(buf, true); @@ -1053,10 +1070,16 @@ void intel_buf_init_using_handle_and_size(struct buf_ops *bops, uint32_t req_tiling, uint32_t compression, uint64_t size) { + uint8_t pat_index = DEFAULT_PAT_INDEX; + igt_assert(handle); igt_assert(size); + + if (compression && AT_LEAST_GEN(bops->devid, 20)) + pat_index = intel_get_pat_idx_uc_comp(bops->fd); + __intel_buf_init(bops, handle, buf, width, height, bpp, alignment, - req_tiling, compression, size, 0, -1, DEFAULT_PAT_INDEX, + req_tiling, compression, size, 0, -1, pat_index, DEFAULT_MOCS_INDEX); } |