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2008-05-04remove target ifdefs from vl.caurel321-0/+22
2008-05-04Simplify mips branch handling. Retire T2 from use. Use TCG for branches.ths5-77/+55
2008-05-03Fix MIPS MT GPR accesses, thanks Stefan Weil.ths2-10/+10
2008-04-28Factorize code in translate.caurel321-0/+8
2008-04-11Remove osdep.c/qemu-img code duplicationaurel321-0/+1
2008-03-29Fix infinite loop when invalidating TLB, by Herve Poussineau.ths1-1/+1
2008-02-12Make MIPS MT implementation more cache friendly.ths5-59/+59
2008-02-01use the TCG code generatorbellard2-55/+6
2008-01-09Fix typo which broke MIPS32R2 64-bit FPU support.ths1-1/+1
2008-01-08Fix broken absoluteness check for cabs.d.*.ths1-2/+2
2008-01-04Handle some more exception types.ths1-29/+43
2008-01-03Fix exception debug output.ths1-39/+36
2007-12-30MIPS COP1X (and related) instructions, by Richard Sandiford.ths3-18/+74
2007-12-28Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.ths1-3/+3
2007-12-26De-cruft exception definitions, and implement nicer debug output.ths2-26/+65
2007-12-25Support for VR5432, and some of its special instructions. Original patchths6-7/+405
2007-12-255K and 20K are Release 1 CPUs.ths1-3/+3
2007-12-25Avoid host FPE for overflowing division on MIPS, by Richard Sandiford.ths1-3/+10
2007-12-25Improved PABITS handling, and config register fixes.ths4-56/+106
2007-12-24Update debug code to match new accumulator register layout.ths1-4/+4
2007-12-24Fix CCRes value for 20Kc.ths1-1/+1
2007-12-17MIPS TODO: mention unimplemented system controllers.ths1-0/+2
2007-12-17Update MIPS TODO. The mipsnet failure is caused by a kernel bug.ths1-6/+0
2007-12-09Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.ths1-0/+1
2007-12-02Larger physical address space for 32-bit MIPS.ths1-0/+3
2007-11-26Micro-optimize back-to-back store-load sequences.ths1-103/+135
2007-11-22Optimize the conventional move operation.ths1-0/+6
2007-11-22Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno.ths1-4/+4
2007-11-19Add older 4Km variants.ths1-0/+34
2007-11-18Add strict checking mode for softfp code.pbrook1-4/+4
2007-11-18Fix MIPS64 R2 instructions.ths3-30/+34
2007-11-18Use a valid PRid.ths1-1/+1
2007-11-17Fix int/float inconsistencies.pbrook3-36/+34
2007-11-14Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSPths1-2/+19
2007-11-10added cpu_model parameter to cpu_init()bellard3-29/+23
2007-11-09Use FORCE_RET, scrap RETURN which was implemented in target-specific code.ths5-424/+418
2007-11-09Move kernel loader parameters from the cpu state to being board specific.ths1-5/+0
2007-11-08Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths9-61/+61
2007-11-08Formatting fix.ths1-1/+1
2007-10-29Adjust s390 addresses (the MSB is defined as "to be ignored").ths1-1/+5
2007-10-29Preliminary MIPS64R2 mode.ths1-0/+21
2007-10-29Fix logic bug which broke TLBL/TLBS handling somewhat.ths1-3/+3
2007-10-29Restrict CP0_PerfCnt to legal values.ths1-1/+1
2007-10-28Implement missing MIPS supervisor mode bits.ths6-35/+49
2007-10-27Add sharable clz/clo inline functions and use them for the mips target.ths3-49/+33
2007-10-26The other half of the mul64 rework. Sorry for the breakage, I committedths1-2/+2
2007-10-24Remove bogus instruction decode.ths1-1/+0
2007-10-24Force proper sign extension for mfc0/mfhc0 on MIPS64.ths1-2/+2
2007-10-23Fix writable length of the index register.ths1-1/+8
2007-10-23Enforce proper sign extension for lwl/lwr on MIPS64.ths1-1/+3
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