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2011-03-22target-arm: use make_float32() to make constant floats for VRSQRTSPeter Maydell1-6/+5
2011-03-22target-arm: Fix VRECPS edge cases handlingPeter Maydell1-3/+8
2011-03-22target-arm: Fix TCG temporary leaks for scalar VMULLPeter Maydell1-0/+2
2011-03-22target-arm: Set Q bit for overflow in SMUAD and SMLADPeter Maydell1-4/+12
2011-03-22target-arm: Fix GE bits for v6media signed modulo arithmeticPeter Maydell1-2/+2
2011-03-22target-arm: Fix UNDEF cases in Thumb load/storePeter Maydell1-11/+18
2011-03-13inline cpu_halted into sole callerPaolo Bonzini1-13/+0
2011-03-07target-arm: Implement a minimal set of cp14 debug registersPeter Maydell1-0/+28
2011-03-07target-arm: Use TCG temporary leak debugging facilitiesPeter Maydell1-0/+7
2011-03-07target-arm: Remove ad-hoc leak checking codePeter Maydell1-360/+338
2011-03-06target-arm: Implement cp15 VA->PA translationAdam Lackorzynski3-3/+50
2011-03-06target-arm: Set carry flag correctly for Thumb2 ORNSPeter Maydell1-2/+1
2011-03-06target-arm: Handle VMOV between two core and VFP single regsPeter Maydell1-5/+5
2011-03-06target-arm: Don't decode old cp15 WFI instructions on v7 coresPeter Maydell1-5/+30
2011-02-24target-arm: fix support for VRSQRTE.Christophe Lyon1-10/+113
2011-02-24target-arm: fix support for VRECPE.Christophe Lyon1-12/+71
2011-02-24target-arm: Introduce float64_256 and float64_512 constants.Christophe Lyon1-0/+5
2011-02-21target-arm: Fix shift by immediate and narrow where src, dest overlapPeter Maydell1-40/+44
2011-02-21target-arm: Refactor to pull narrowing decode into separate functionPeter Maydell1-26/+19
2011-02-20target-arm: Fix unsigned VQRSHL by large shift countsPeter Maydell1-3/+34
2011-02-20target-arm: Fix signed VQRSHL by large shift countsPeter Maydell1-3/+31
2011-02-20target-arm: fix decoding of Neon 64 bit shifts.Christophe Lyon1-15/+30
2011-02-20target-arm: fix Neon VQSHRN and VSHRN.Christophe Lyon1-2/+2
2011-02-20target-arm: Fix saturated values for Neon right shiftsPeter Maydell1-1/+4
2011-02-20target-arm: fix unsigned 64 bit right shifts.Christophe Lyon1-1/+1
2011-02-20target-arm: Fix unsigned VRSHL.s8 and .s16 right shifts by type widthChristophe Lyon1-1/+1
2011-02-20target-arm: Fix signed VRSHL by large shift countsPeter Maydell1-14/+3
2011-02-20target-arm: Fix rounding constant addition for Neon shiftsChristophe Lyon1-12/+127
2011-02-20target-arm: Move Neon VZIP to helper functionsPeter Maydell3-73/+133
2011-02-20target-arm: Move Neon VUZP to helper functionsPeter Maydell3-75/+137
2011-02-20target-arm: Correct conversion of Thumb Neon dp encodings into ARMJuha Riihimäki1-1/+1
2011-02-20target-arm: Fix Neon VQDMLSL instructionPeter Maydell1-8/+14
2011-02-20target-arm: Refactor handling of VQDMULLPeter Maydell1-10/+6
2011-02-20target-arm: Implement VMULL.P8Peter Maydell3-2/+35
2011-02-11arm: drop unused irq-related part of CPUARMStateDmitry Eremin-Solenikov1-4/+0
2011-02-10target-arm: Remove stray #include from middle of neon_helper.cPeter Maydell1-1/+0
2011-02-10target-arm: Use standard FPSCR for Neon half-precision operationsPeter Maydell3-12/+32
2011-02-10target-arm: Silence NaNs resulting from half-precision conversionsPeter Maydell1-2/+10
2011-02-10softfloat: Add float16 type and float16 NaN handling functionsPeter Maydell1-2/+2
2011-02-09target-arm: implement vsli.64, vsri.64Christophe Lyon1-1/+13
2011-02-09target-arm: fix VSHLL Neon instruction.Christophe Lyon1-3/+15
2011-02-09target-arm: Fix 32 bit signed saturating narrowPeter Maydell1-1/+1
2011-02-09target-arm: Fix VQMOVUN Neon instruction.Juha Riihimäki3-6/+88
2011-02-04target-arm: Fix decoding of Thumb preload and hint spacePeter Maydell1-22/+48
2011-02-04target-arm: Fix decoding of preload and memory hint spacePeter Maydell1-3/+25
2011-02-04target-arm: Clean up handling of MPIDRPeter Maydell1-5/+21
2011-02-04target-arm: Add CPU feature flag for v7MPPeter Maydell2-1/+8
2011-02-04Set the right overflow bit for neon 32 and 64 bit saturating add/sub.Christophe Lyon4-63/+105
2011-02-04target-arm: Fix Neon vsra instructions.Christophe Lyon1-2/+2
2011-01-29target-arm: Fix Neon VQ(R)DMULH.S16 instructionsJuha Riihimäki1-1/+2
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