Merge commit '6049f4f831c6f409031dfa09282b38d0cbaecad8' into upstream-merge

* commit '6049f4f831c6f409031dfa09282b38d0cbaecad8': (32 commits)
  alpha-linux-user: Implement signals.
  target-alpha: Implement IEEE FP qualifiers.
  target-ppc: don't print invalid opcode messages on the console
  Revert "target-ppc: stop translation after a trap instruction"
  audio/alsa: Handle SND_PCM_STATE_SETUP in alsa_poll_handler
  audio/alsa: Spelling typo (paramters)
  target-ppc: stop translation after a trap instruction
  qemu-char.c: drop debug printfs from qemu_chr_parse_compat
  powerpc/e500: adjust fdt and ramdisk loading addr
  powerpc: fix compilation with CONFIG_FDT undefined
  powerpc/booke: move fdt loading to rom infrastructure
  target-ppc: add synchronize register for booke init
  target-sh4: Fix gdb read/write register
  target-ppc: fix SPE evsplat* instructions
  target-ppc: fix SPE evcmp* instructions
  arm host: Fix linker warning (m68k targets)
  Fix 'make install' from non-srcdir build
  Fix to 'gdb detach' stub
  Fix qemu -net user,hostfwd= example
  tcg/ppc: Fix right rotation
  ...

Conflicts:
	Makefile.target

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>

2 files changed, 6 insertions, 17 deletions

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index fc735f4e9..6aba61c98 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -835,10 +835,10 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 #define CRF_GT        2
 #define CRF_EQ        1
 #define CRF_SO        0
-#define CRF_CH        (1 << 4)
-#define CRF_CL        (1 << 3)
-#define CRF_CH_OR_CL  (1 << 2)
-#define CRF_CH_AND_CL (1 << 1)
+#define CRF_CH        (1 << CRF_LT)
+#define CRF_CL        (1 << CRF_GT)
+#define CRF_CH_OR_CL  (1 << CRF_EQ)
+#define CRF_CH_AND_CL (1 << CRF_SO)
 
 /* XER definitions */
 #define XER_SO  31
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d4e81ce89..7c79665d0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7001,7 +7001,7 @@ static inline void gen_evmergelohi(DisasContext *ctx)
 }
 static inline void gen_evsplati(DisasContext *ctx)
 {
-    uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
+    uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
 
 #if defined(TARGET_PPC64)
     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
@@ -7012,7 +7012,7 @@ static inline void gen_evsplati(DisasContext *ctx)
 }
 static inline void gen_evsplatfi(DisasContext *ctx)
 {
-    uint64_t imm = rA(ctx->opcode) << 11;
+    uint64_t imm = rA(ctx->opcode) << 27;
 
 #if defined(TARGET_PPC64)
     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
@@ -9053,11 +9053,6 @@ static inline void gen_intermediate_code_internal(CPUState *env,
                          "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
                          opc1(ctx.opcode), opc2(ctx.opcode),
                          opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
-            } else {
-                printf("invalid/unsupported opcode: "
-                       "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
-                       opc1(ctx.opcode), opc2(ctx.opcode),
-                       opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
             }
         } else {
             if (unlikely((ctx.opcode & handler->inval) != 0)) {
@@ -9067,12 +9062,6 @@ static inline void gen_intermediate_code_internal(CPUState *env,
                              ctx.opcode & handler->inval, opc1(ctx.opcode),
                              opc2(ctx.opcode), opc3(ctx.opcode),
                              ctx.opcode, ctx.nip - 4);
-                } else {
-                    printf("invalid bits: %08x for opcode: "
-                           "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
-                           ctx.opcode & handler->inval, opc1(ctx.opcode),
-                           opc2(ctx.opcode), opc3(ctx.opcode),
-                           ctx.opcode, ctx.nip - 4);
                 }
                 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
                 break;