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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-07 15:39:12 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-05-07 15:39:12 +0000
commitbec19c0932e51752fbe0b0b59e9c7cc8a130c269 (patch)
treea930d1f0449f91069b518147d2ba61b982a37321 /target-mips/TODO
parentb5e817eac16ce07270b20e93e82167e319229fd9 (diff)
Mention missing CPU save/restore.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4381 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/TODO')
-rw-r--r--target-mips/TODO1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/TODO b/target-mips/TODO
index dda580118..c58956cff 100644
--- a/target-mips/TODO
+++ b/target-mips/TODO
@@ -29,6 +29,7 @@ General
To cope with these differences, Qemu currently flushes the TLB at
each ASID change. Using the MMU modes to implement ASIDs hinges on
implementing the global bit efficiently.
+- save/restore of the CPU state is not implemented (see machine.c).
MIPS64
------