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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-03 17:57:36 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-03 17:57:36 +0000
commit551bd27f22638c854c43d7e6417d549764311c31 (patch)
treeb67965e4923a4b5367c47686b279be46ba79c2a0 /target-arm
parent06e80fc92715ca720d23526f6d3db8c78fd8971c (diff)
Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/op_helper.c2
-rw-r--r--target-arm/translate.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 5d9fd8488..5b5581f2c 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -97,7 +97,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
- if (__builtin_expect(ret, 0)) {
+ if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
pc = (unsigned long)retaddr;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e03de44d5..a3aabd26d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -3393,7 +3393,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
static inline void gen_jmp (DisasContext *s, uint32_t dest)
{
- if (__builtin_expect(s->singlestep_enabled, 0)) {
+ if (unlikely(s->singlestep_enabled)) {
/* An indirect jump so that we still trigger the debug exception. */
if (s->thumb)
dest |= 1;
@@ -8703,7 +8703,7 @@ static inline int gen_intermediate_code_internal(CPUState *env,
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (__builtin_expect(env->singlestep_enabled, 0)) {
+ if (unlikely(env->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
gen_set_condexec(dc);