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authorEric Anholt <eric@anholt.net>2010-12-08 09:52:56 -0800
committerEric Anholt <eric@anholt.net>2010-12-08 09:53:16 -0800
commit0d3b8a5cc2c1730af0efc69482d36a86ff18f15e (patch)
tree48f311dba1601376424a6372c829de9dd9a3d01f
parentd2028ba33967b3ce3de94b0837c9faf06f1c2b94 (diff)
i965: Set up the color masking for the first drawbuffer on gen6.
Fixes glean/maskedClear
-rw-r--r--src/mesa/drivers/dri/i965/gen6_cc.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index f51cf5f112..dfcef20961 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -35,6 +35,7 @@
struct gen6_blend_state_key {
GLboolean color_blend, alpha_enabled;
GLboolean dither;
+ GLboolean color_mask[4];
GLenum logic_op;
@@ -54,6 +55,9 @@ blend_state_populate_key(struct brw_context *brw,
memset(key, 0, sizeof(*key));
/* _NEW_COLOR */
+ memcpy(key->color_mask, ctx->Color.ColorMask[0], sizeof(key->color_mask));
+
+ /* _NEW_COLOR */
if (ctx->Color._LogicOpEnabled)
key->logic_op = ctx->Color.LogicOp;
else
@@ -137,6 +141,11 @@ blend_state_create_from_key(struct brw_context *brw,
blend.blend1.x_dither_offset = 0;
}
+ blend.blend1.write_disable_r = !key->color_mask[0];
+ blend.blend1.write_disable_g = !key->color_mask[1];
+ blend.blend1.write_disable_b = !key->color_mask[2];
+ blend.blend1.write_disable_a = !key->color_mask[3];
+
bo = brw_upload_cache(&brw->cache, BRW_BLEND_STATE,
key, sizeof(*key),
NULL, 0,