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path: root/intel/intel_bufmgr_gem.c
AgeCommit message (Expand)AuthorFilesLines
2011-02-14intel: Remember named boChris Wilson1-0/+28
2011-02-14intel: Set the public handle after opening by nameChris Wilson1-0/+1
2010-12-19intel: Export CONSTANT_BUFFER addressing modeChris Wilson1-3/+3
2010-12-07intel: Reorder need_fence vs fenced_command to avoid fences on gen4Chris Wilson1-4/+5
2010-12-03intel: If the command is fenced inform the kernelChris Wilson1-1/+2
2010-11-22intel: Compute in-aperture size for relaxed fenced objectsChris Wilson1-2/+17
2010-11-09intel: Fix drm_intel_gem_bo_wait_rendering to wait for read-only usage too.Eric Anholt1-2/+2
2010-11-07intel: initialize bufmgr.bo_mrb_exec unconditionallyAlbert Damen1-2/+1
2010-11-02intel: Drop silly asserts on mappings present at unmap time.Eric Anholt1-5/+0
2010-11-02intel: Remove gratuitous assert on bo_reference.Eric Anholt1-1/+0
2010-11-01intel: Remove stale comment.Eric Anholt1-2/+0
2010-10-29intel: enable relaxed fence allocation for i915Chris Wilson1-3/+12
2010-10-26intel: Prepare for BLT ring split.Chris Wilson1-5/+23
2010-10-01intel: Downgrade error warnings to debugChris Wilson1-56/+47
2010-09-25intel: Replace open-coded drmIoctl with calls to drmIoctl()Chris Wilson1-83/+62
2010-06-29intel: Suppress the error return from setting domains after mapping.Chris Wilson1-6/+1
2010-06-24intel: Limit tiled pitches to 8192 on pre-i965.Chris Wilson1-4/+12
2010-06-22intel: Only adjust the local stride used for SET_TILING in tiled allocChris Wilson1-9/+4
2010-06-22intel: Restore SET_TILING for non-flinked bo.Chris Wilson1-5/+3
2010-06-22intel: '===' != '=='Chris Wilson1-1/+1
2010-06-22intel: Sanitise strides for linear buffers and SET_TILINGChris Wilson1-0/+6
2010-06-21intel: Print out debugging message following ENOSPCChris Wilson1-1/+1
2010-06-21intel: Scan the cache for old bo once every second.Chris Wilson1-2/+7
2010-06-21intel: Force stride to be 0 for I915_TILING_NONE.Chris Wilson1-0/+3
2010-06-21intel: Defer tiling change to allocation.Chris Wilson1-35/+58
2010-06-21intel: Track tiling strideChris Wilson1-1/+9
2010-06-10intel: Fix several other paths for buffers pointing at themselves.Eric Anholt1-4/+9
2010-06-10intel: Add more intermediate sizes of cache buckets between powers of 2.Eric Anholt1-15/+48
2010-06-09intel: Convert to untiled pitches if surface is too large for tiling.Chris Wilson1-23/+31
2010-06-07Allow a buffer to point at itself and still get relocs.Eric Anholt1-2/+10
2010-06-06intel: Add support for kernel multi-ringbuffer API.Zou Nan hai1-7/+27
2010-05-24intel: Don't change tiling mode unless the kernel reports success.Chris Wilson1-5/+7
2010-05-13Revert "intel: We don't need to take the bufmgr lock whilst mapping."Chris Wilson1-0/+17
2010-05-11intel: query whether a buffer is reusable.Chris Wilson1-0/+9
2010-05-06intel: We don't need to take the bufmgr lock whilst mapping.Chris Wilson1-17/+0
2010-04-11intel: Use the correct size when allocating reloc_target_info arrayChris Wilson1-1/+1
2010-03-17intel: Align untiled buffer pitch to 64B.Eric Anholt1-1/+4
2010-03-17libdrm: Move intel_atomic.h to libdrm core for sharing.Pauli Nieminen1-1/+1
2010-03-07intel: Repeat execbuffer if interrupted by signalChris Wilson1-1/+1
2010-03-04intel: Only align Y-tiling pitch to the Y tile width.Eric Anholt1-1/+6
2010-03-04intel: Propagate some more error returnsChris Wilson1-12/+20
2010-03-03intel: Update the needs_fence flag of buffers on the validate list.Eric Anholt1-1/+5
2010-03-02intel: Don't enable execbuf2 fenced relocs unless we have execbuf2.Eric Anholt1-2/+3
2010-03-02intel: Don't tile-align pitch for untiled buffers.Eric Anholt1-1/+1
2010-03-02intel: Fix typo in conversion from IS_GEN to bufmgr_gem->gen.Eric Anholt1-1/+1
2010-03-02intel: add a comment about tiled buffer alloc height alignment from Mesa.Eric Anholt1-0/+11
2010-03-02intel: Use an integer for chipset generation instead of many conditionals.Eric Anholt1-8/+17
2010-03-02libdrm/intel: execbuf2 supportJesse Barnes1-33/+253
2010-02-25intel: Add initial support for Sandybridge, and clean up the #defines.Eric Anholt1-5/+6
2010-02-10intel: Handle resetting of input params after EINTR during SET_TILINGChris Wilson1-7/+4
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