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authorEric Anholt <eric@anholt.net>2010-03-04 16:09:40 -0800
committerEric Anholt <eric@anholt.net>2010-03-04 16:27:45 -0800
commit1d4d1e6b138aac8bd734c4c20617a43fb3337c63 (patch)
tree0a2f9f4875978bc75481c62639a4382f55a22253 /intel
parent3e21e3ba0090c4dbe976269409b336dc82fe3d36 (diff)
intel: Only align Y-tiling pitch to the Y tile width.
Fixes piglit depth-tex-modes on gen4.
Diffstat (limited to 'intel')
-rw-r--r--intel/intel_bufmgr_gem.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index f852c09d..21fe099e 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -254,12 +254,17 @@ static unsigned long
drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
unsigned long pitch, uint32_t tiling_mode)
{
- unsigned long tile_width = 512;
+ unsigned long tile_width;
unsigned long i;
if (tiling_mode == I915_TILING_NONE)
return pitch;
+ if (tiling_mode == I915_TILING_X)
+ tile_width = 512;
+ else
+ tile_width = 128;
+
/* 965 is flexible */
if (bufmgr_gem->gen >= 4)
return ROUND_UP_TO(pitch, tile_width);