Ok. We got 3d hw acceleration on S3 Virge too now ; )

69 files changed, 1862 insertions, 548 deletions

diff --git a/bsd/drm.h b/bsd/drm.h
index ddb280cc..92fddec6 100644
--- a/bsd/drm.h
+++ b/bsd/drm.h
@@ -93,6 +93,15 @@ typedef struct drm_tex_region {
 	unsigned int	age;
 } drm_tex_region_t;
 
+/* Seperate include files for the driver specific structures */
+#include "mga_drm.h"
+#include "i810_drm.h"
+#include "i830_drm.h"
+#include "r128_drm.h"
+#include "radeon_drm.h"
+#include "sis_drm.h"
+#include "gamma_drm.h"
+
 typedef struct drm_version {
 	int    version_major;	  /* Major version			    */
 	int    version_minor;	  /* Minor version			    */
@@ -413,8 +422,87 @@ typedef struct drm_scatter_gather {
 #define DRM_IOCTL_SG_ALLOC		DRM_IOW( 0x38, drm_scatter_gather_t)
 #define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, drm_scatter_gather_t)
 
-/* Device specfic ioctls should only be in their respective headers
- * The device specific ioctl range is 0x40 to 0x79.                  */
-#define DRM_COMMAND_BASE                0x40
+/* MGA specific ioctls */
+#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
+#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x41, drm_lock_t)
+#define DRM_IOCTL_MGA_RESET		DRM_IO(  0x42)
+#define DRM_IOCTL_MGA_SWAP		DRM_IO(  0x43)
+#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x44, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x45, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x47, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x48, drm_mga_blit_t)
+
+/* i810 specific ioctls */
+#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)
+#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)
+#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)
+#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)
+
+/* Rage 128 specific ioctls */
+#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)
+#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)
+#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)
+#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_INDIRECT		DRM_IOWR(0x4f, drm_r128_indirect_t)
+#define DRM_IOCTL_R128_FULLSCREEN	DRM_IOW( 0x50, drm_r128_fullscreen_t)
+#define DRM_IOCTL_R128_CLEAR2		DRM_IOW( 0x51, drm_r128_clear2_t)
+
+/* Radeon specific ioctls */
+#define DRM_IOCTL_RADEON_CP_INIT	DRM_IOW( 0x40, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START	DRM_IO(  0x41)
+#define DRM_IOCTL_RADEON_CP_STOP	DRM_IOW( 0x42, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_RADEON_CP_IDLE	DRM_IO(  0x44)
+#define DRM_IOCTL_RADEON_RESET		DRM_IO(  0x45)
+#define DRM_IOCTL_RADEON_FULLSCREEN	DRM_IOW( 0x46, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_RADEON_CLEAR		DRM_IOW( 0x48, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX		DRM_IOW( 0x49, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES	DRM_IOW( 0x4a, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_STIPPLE	DRM_IOW( 0x4c, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_INDIRECT	DRM_IOWR(0x4d, drm_radeon_indirect_t)
+#define DRM_IOCTL_RADEON_TEXTURE	DRM_IOWR(0x4e, drm_radeon_texture_t)
+#define DRM_IOCTL_RADEON_VERTEX2	DRM_IOW( 0x4f, drm_radeon_vertex_t)
+
+/* Gamma specific ioctls */
+#define DRM_IOCTL_GAMMA_INIT		DRM_IOW( 0x40, drm_gamma_init_t)
+#define DRM_IOCTL_GAMMA_COPY		DRM_IOW( 0x41, drm_gamma_copy_t)
+
+/* SiS specific ioctls */
+
+#define SIS_IOCTL_FB_ALLOC		DRM_IOWR(0x44, drm_sis_mem_t)
+#define SIS_IOCTL_FB_FREE		DRM_IOW( 0x45, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_INIT		DRM_IOWR(0x53, drm_sis_agp_t)
+#define SIS_IOCTL_AGP_ALLOC		DRM_IOWR(0x54, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_FREE		DRM_IOW( 0x55, drm_sis_mem_t)
+#define SIS_IOCTL_FLIP			DRM_IOW( 0x48, drm_sis_flip_t)
+#define SIS_IOCTL_FLIP_INIT		DRM_IO(  0x49)
+#define SIS_IOCTL_FLIP_FINAL		DRM_IO(  0x50)
+
+/* I830 specific ioctls */
+#define DRM_IOCTL_I830_INIT		DRM_IOW( 0x40, drm_i830_init_t)
+#define DRM_IOCTL_I830_VERTEX		DRM_IOW( 0x41, drm_i830_vertex_t)
+#define DRM_IOCTL_I830_CLEAR		DRM_IOW( 0x42, drm_i830_clear_t)
+#define DRM_IOCTL_I830_FLUSH		DRM_IO ( 0x43)
+#define DRM_IOCTL_I830_GETAGE		DRM_IO ( 0x44)
+#define DRM_IOCTL_I830_GETBUF		DRM_IOWR(0x45, drm_i830_dma_t)
+#define DRM_IOCTL_I830_SWAP		DRM_IO ( 0x46)
+#define DRM_IOCTL_I830_COPY		DRM_IOW( 0x47, drm_i830_copy_t)
+#define DRM_IOCTL_I830_DOCOPY		DRM_IO ( 0x48)
 
 #endif
diff --git a/bsd/gamma/gamma_dma.c b/bsd/gamma/gamma_dma.c
index 0dee8c74..fd0da710 100644
--- a/bsd/gamma/gamma_dma.c
+++ b/bsd/gamma/gamma_dma.c
@@ -33,8 +33,6 @@
 
 #include "gamma.h"
 #include "drmP.h"
-#include "drm.h"
-#include "gamma_drm.h"
 #include "gamma_drv.h"
 
 
diff --git a/bsd/gamma/gamma_drv.c b/bsd/gamma/gamma_drv.c
index 50658bba..e58d853c 100644
--- a/bsd/gamma/gamma_drv.c
+++ b/bsd/gamma/gamma_drv.c
@@ -35,8 +35,6 @@
 #include <opt_drm_linux.h>
 #include "gamma.h"
 #include "drmP.h"
-#include "drm.h"
-#include "gamma_drm.h"
 #include "gamma_drv.h"
 
 #define DRIVER_AUTHOR		"VA Linux Systems Inc."
diff --git a/bsd/gamma_drm.h b/bsd/gamma_drm.h
index 0d58b07b..d06763ae 100644
--- a/bsd/gamma_drm.h
+++ b/bsd/gamma_drm.h
@@ -48,16 +48,6 @@ typedef struct _drm_gamma_sarea {
 	int vertex_prim;
 } drm_gamma_sarea_t;
 
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (xf86drmGamma.h)
- */
-
-/* Gamma specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_GAMMA_INIT		DRM_IOW( 0x40, drm_gamma_init_t)
-#define DRM_IOCTL_GAMMA_COPY		DRM_IOW( 0x41, drm_gamma_copy_t)
-
 typedef struct drm_gamma_copy {
 	unsigned int	DMAOutputAddress;
 	unsigned int	DMAOutputCount;
diff --git a/bsd/i810/i810_dma.c b/bsd/i810/i810_dma.c
index 4310851a..4558c199 100644
--- a/bsd/i810/i810_dma.c
+++ b/bsd/i810/i810_dma.c
@@ -33,8 +33,6 @@
 
 #include "i810.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i810_drm.h"
 #include "i810_drv.h"
 
 #define I810_BUF_FREE		2
@@ -127,7 +125,7 @@ static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf)
    	return 0;
 }
 
-#if 0
+
 int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
 {
 	DRM_OS_DEVICE;
@@ -152,7 +150,6 @@ int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
 			     vma->vm_page_prot)) DRM_OS_RETURN(EAGAIN);
 	return 0;
 }
-#endif
 
 static int i810_map_buffer(drm_buf_t *buf, struct file *filp)
 {
diff --git a/bsd/i810/i810_drv.c b/bsd/i810/i810_drv.c
index e76e3a8a..e1c08127 100644
--- a/bsd/i810/i810_drv.c
+++ b/bsd/i810/i810_drv.c
@@ -38,8 +38,6 @@
 
 #include "i810.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i810_drm.h"
 #include "i810_drv.h"
 
 #define DRIVER_AUTHOR		"VA Linux Systems Inc."
diff --git a/bsd/i810_drm.h b/bsd/i810_drm.h
index 990e50e2..f2114dd1 100644
--- a/bsd/i810_drm.h
+++ b/bsd/i810_drm.h
@@ -166,34 +166,14 @@ typedef struct _drm_i810_sarea {
 
 } drm_i810_sarea_t;
 
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (xf86drmMga.h)
- */
-
-/* i810 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)
-#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)
-#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)
-#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)
-#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)
-#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)
-#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)
-#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)
-#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)
-#define DRM_IOCTL_I810_OV0INFO		DRM_IOR( 0x49, drm_i810_overlay_t)
-#define DRM_IOCTL_I810_FSTATUS		DRM_IO ( 0x4a)
-#define DRM_IOCTL_I810_OV0FLIP		DRM_IO ( 0x4b)
-#define DRM_IOCTL_I810_MC		DRM_IOW( 0x4c, drm_i810_mc_t)
-#define DRM_IOCTL_I810_RSTATUS		DRM_IO ( 0x4d )
-
 typedef struct _drm_i810_clear {
 	int clear_color;
 	int clear_depth;
 	int flags;
 } drm_i810_clear_t;
 
+
+
 /* These may be placeholders if we have more cliprects than
  * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
  * false, indicating that the buffer will be dispatched again with a
diff --git a/bsd/i830/i830_dma.c b/bsd/i830/i830_dma.c
index fbdc9523..69b1c8a3 100644
--- a/bsd/i830/i830_dma.c
+++ b/bsd/i830/i830_dma.c
@@ -34,8 +34,6 @@
 #define __NO_VERSION__
 #include "i830.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i830_drm.h"
 #include "i830_drv.h"
 #include <linux/interrupt.h>	/* For task queue support */
 
diff --git a/bsd/i830/i830_drv.c b/bsd/i830/i830_drv.c
index ad31d1ef..904f3660 100644
--- a/bsd/i830/i830_drv.c
+++ b/bsd/i830/i830_drv.c
@@ -34,8 +34,6 @@
 #include <linux/config.h>
 #include "i830.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i830_drm.h"
 #include "i830_drv.h"
 
 #define DRIVER_AUTHOR		"VA Linux Systems Inc."
diff --git a/bsd/i830_drm.h b/bsd/i830_drm.h
index 725ad369..e4a2a257 100644
--- a/bsd/i830_drm.h
+++ b/bsd/i830_drm.h
@@ -201,19 +201,6 @@ typedef struct _drm_i830_sarea {
 	int vertex_prim;
 } drm_i830_sarea_t;
 
-/* I830 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_I830_INIT		DRM_IOW( 0x40, drm_i830_init_t)
-#define DRM_IOCTL_I830_VERTEX		DRM_IOW( 0x41, drm_i830_vertex_t)
-#define DRM_IOCTL_I830_CLEAR		DRM_IOW( 0x42, drm_i830_clear_t)
-#define DRM_IOCTL_I830_FLUSH		DRM_IO ( 0x43)
-#define DRM_IOCTL_I830_GETAGE		DRM_IO ( 0x44)
-#define DRM_IOCTL_I830_GETBUF		DRM_IOWR(0x45, drm_i830_dma_t)
-#define DRM_IOCTL_I830_SWAP		DRM_IO ( 0x46)
-#define DRM_IOCTL_I830_COPY		DRM_IOW( 0x47, drm_i830_copy_t)
-#define DRM_IOCTL_I830_DOCOPY		DRM_IO ( 0x48)
-
 typedef struct _drm_i830_clear {
 	int clear_color;
 	int clear_depth;
diff --git a/bsd/mga/mga_dma.c b/bsd/mga/mga_dma.c
index d9449c53..9ed5d095 100644
--- a/bsd/mga/mga_dma.c
+++ b/bsd/mga/mga_dma.c
@@ -36,8 +36,6 @@
 #define __NO_VERSION__
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 
 
diff --git a/bsd/mga/mga_drv.c b/bsd/mga/mga_drv.c
index d8af2236..206a77dc 100644
--- a/bsd/mga/mga_drv.c
+++ b/bsd/mga/mga_drv.c
@@ -37,8 +37,6 @@
 
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 
 #define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
diff --git a/bsd/mga/mga_state.c b/bsd/mga/mga_state.c
index a0bd404a..b71f333d 100644
--- a/bsd/mga/mga_state.c
+++ b/bsd/mga/mga_state.c
@@ -35,8 +35,6 @@
 #define __NO_VERSION__
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 #include "drm.h"
 
diff --git a/bsd/mga/mga_warp.c b/bsd/mga/mga_warp.c
index f11cd922..4fe4315c 100644
--- a/bsd/mga/mga_warp.c
+++ b/bsd/mga/mga_warp.c
@@ -30,8 +30,6 @@
 #define __NO_VERSION__
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 #include "mga_ucode.h"
 
diff --git a/bsd/mga_drm.h b/bsd/mga_drm.h
index 8f56beed..4af2ca2e 100644
--- a/bsd/mga_drm.h
+++ b/bsd/mga_drm.h
@@ -38,7 +38,6 @@
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (mga_sarea.h)
  */
-
 #ifndef __MGA_SAREA_DEFINES__
 #define __MGA_SAREA_DEFINES__
 
@@ -226,20 +225,6 @@ typedef struct _drm_mga_sarea {
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmMga.h)
  */
-
-/* MGA specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
-#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x41, drm_lock_t)
-#define DRM_IOCTL_MGA_RESET		DRM_IO(  0x42)
-#define DRM_IOCTL_MGA_SWAP		DRM_IO(  0x43)
-#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x44, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x45, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
-#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x47, drm_mga_iload_t)
-#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x48, drm_mga_blit_t)
-
 typedef struct _drm_mga_warp_index {
    	int installed;
    	unsigned long phys_addr;
diff --git a/bsd/r128/r128_cce.c b/bsd/r128/r128_cce.c
index 36cc3120..6c4a5e65 100644
--- a/bsd/r128/r128_cce.c
+++ b/bsd/r128/r128_cce.c
@@ -31,8 +31,6 @@
 #define __NO_VERSION__
 #include "r128.h"
 #include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
 #include "r128_drv.h"
 
 
diff --git a/bsd/r128/r128_drv.c b/bsd/r128/r128_drv.c
index cf59aa0d..51e08a28 100644
--- a/bsd/r128/r128_drv.c
+++ b/bsd/r128/r128_drv.c
@@ -37,8 +37,6 @@
 
 #include "r128.h"
 #include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
 #include "r128_drv.h"
 #if __REALLY_HAVE_SG
 #include "ati_pcigart.h"
diff --git a/bsd/r128/r128_state.c b/bsd/r128/r128_state.c
index 34500bb3..0fce0c55 100644
--- a/bsd/r128/r128_state.c
+++ b/bsd/r128/r128_state.c
@@ -30,8 +30,6 @@
 
 #include "r128.h"
 #include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
 #include "r128_drv.h"
 #include "drm.h"
 
diff --git a/bsd/r128_drm.h b/bsd/r128_drm.h
index a8d23008..0fc6a6cd 100644
--- a/bsd/r128_drm.h
+++ b/bsd/r128_drm.h
@@ -170,27 +170,6 @@ typedef struct drm_r128_sarea {
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmR128.h)
  */
-
-/* Rage 128 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)
-#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)
-#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)
-#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)
-#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)
-#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)
-#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)
-#define DRM_IOCTL_R128_INDIRECT		DRM_IOWR(0x4f, drm_r128_indirect_t)
-#define DRM_IOCTL_R128_FULLSCREEN	DRM_IOW( 0x50, drm_r128_fullscreen_t)
-#define DRM_IOCTL_R128_CLEAR2		DRM_IOW( 0x51, drm_r128_clear2_t)
-
 typedef struct drm_r128_init {
 	enum {
 		R128_INIT_CCE    = 0x01,
diff --git a/bsd/radeon/radeon_cp.c b/bsd/radeon/radeon_cp.c
index 9c262ae3..ed5128b2 100644
--- a/bsd/radeon/radeon_cp.c
+++ b/bsd/radeon/radeon_cp.c
@@ -30,8 +30,6 @@
 
 #include "radeon.h"
 #include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
 #include "radeon_drv.h"
 
 #include <vm/vm.h>
@@ -626,7 +624,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 
 		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 			     entry->busaddr[page_ofs]);
-		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08x\n",
+		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
 			   entry->busaddr[page_ofs],
 			   entry->handle + tmp_ofs );
 	}
diff --git a/bsd/radeon/radeon_drv.c b/bsd/radeon/radeon_drv.c
index 009f90c1..61be65f7 100644
--- a/bsd/radeon/radeon_drv.c
+++ b/bsd/radeon/radeon_drv.c
@@ -36,8 +36,6 @@
 
 #include "radeon.h"
 #include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
 #include "radeon_drv.h"
 #if __REALLY_HAVE_SG
 #include "ati_pcigart.h"
diff --git a/bsd/radeon/radeon_state.c b/bsd/radeon/radeon_state.c
index cbb9d1f6..a7e301e7 100644
--- a/bsd/radeon/radeon_state.c
+++ b/bsd/radeon/radeon_state.c
@@ -29,9 +29,8 @@
 
 #include "radeon.h"
 #include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
 #include "radeon_drv.h"
+#include "drm.h"
 
 
 /* ================================================================
diff --git a/bsd/radeon_drm.h b/bsd/radeon_drm.h
index 6774b2bc..81e76b19 100644
--- a/bsd/radeon_drm.h
+++ b/bsd/radeon_drm.h
@@ -236,29 +236,7 @@ typedef struct {
 
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmRadeon.h)
- *
- * KW: actually it's illegal to change any of this (backwards compatibility).
- */
-
-/* Radeon specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
  */
-#define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( 0x40, drm_radeon_init_t)
-#define DRM_IOCTL_RADEON_CP_START   DRM_IO(  0x41)
-#define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( 0x42, drm_radeon_cp_stop_t)
-#define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  0x43)
-#define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  0x44)
-#define DRM_IOCTL_RADEON_RESET      DRM_IO(  0x45)
-#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
-#define DRM_IOCTL_RADEON_SWAP       DRM_IO(  0x47)
-#define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( 0x48, drm_radeon_clear_t)
-#define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( 0x49, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_INDICES    DRM_IOW( 0x4a, drm_radeon_indices_t)
-#define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( 0x4c, drm_radeon_stipple_t)
-#define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(0x4d, drm_radeon_indirect_t)
-#define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(0x4e, drm_radeon_texture_t)
-#define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( 0x4f, drm_radeon_vertex_t)
-
 typedef struct drm_radeon_init {
 	enum {
 		RADEON_INIT_CP    = 0x01,
diff --git a/bsd/sis_drm.h b/bsd/sis_drm.h
index 21b66350..db11cf63 100644
--- a/bsd/sis_drm.h
+++ b/bsd/sis_drm.h
@@ -2,16 +2,6 @@
 #ifndef _sis_drm_public_h_
 #define _sis_drm_public_h_
 
-/* SiS specific ioctls */
-#define SIS_IOCTL_FB_ALLOC		DRM_IOWR(0x44, drm_sis_mem_t)
-#define SIS_IOCTL_FB_FREE		DRM_IOW( 0x45, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_INIT		DRM_IOWR(0x53, drm_sis_agp_t)
-#define SIS_IOCTL_AGP_ALLOC		DRM_IOWR(0x54, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_FREE		DRM_IOW( 0x55, drm_sis_mem_t)
-#define SIS_IOCTL_FLIP			DRM_IOW( 0x48, drm_sis_flip_t)
-#define SIS_IOCTL_FLIP_INIT		DRM_IO(  0x49)
-#define SIS_IOCTL_FLIP_FINAL		DRM_IO(  0x50)
-
 typedef struct {
   int context;
   unsigned int offset;
diff --git a/libdrm/xf86drm.c b/libdrm/xf86drm.c
index 9cc83a27..1d26b6e6 100644
--- a/libdrm/xf86drm.c
+++ b/libdrm/xf86drm.c
@@ -434,7 +434,7 @@ static void drmCopyVersion(drmVersionPtr d, const drm_version_t *s)
     d->desc               = drmStrdup(s->desc);
 }
 
-/* drmGet Version obtains the driver version information via an ioctl.  Similar
+/* drmVersion obtains the version information via an ioctl.  Similar
  * information is available via /proc/dri. */
 
 drmVersionPtr drmGetVersion(int fd)
@@ -483,26 +483,6 @@ drmVersionPtr drmGetVersion(int fd)
     return retval;
 }
 
-/* drmGetLibVersion set version information for the drm user space library.
- * this version number is driver indepedent */
-
-drmVersionPtr drmGetLibVersion(int fd)
-{
-    drm_version_t *version = drmMalloc(sizeof(*version));
-
-    /* Version history:
-     *   revision 1.0.x = original DRM interface with no drmGetLibVersion
-     *                    entry point and many drm<Device> extensions
-     *   revision 1.1.x = added drmCommand entry points for device extensions
-     *                    added drmGetLibVersion to identify libdrm.a version
-     */
-    version->version_major      = 1;
-    version->version_minor      = 1;
-    version->version_patchlevel = 0;
-
-    return (drmVersionPtr)version;
-}
-
 void drmFreeBusid(const char *busid)
 {
     drmFree((void *)busid);
@@ -1363,58 +1343,6 @@ int drmGetStats(int fd, drmStatsT *stats)
     return 0;
 }
 
-int drmCommandNone(int fd, unsigned long drmCommandIndex)
-{
-    void *data = NULL; /* dummy */
-    unsigned long request;
-
-    request = DRM_IO( DRM_COMMAND_BASE + drmCommandIndex);
-
-    if (ioctl(fd, request, data)) {
-	return -errno;
-    }
-    return 0;
-}
-
-int drmCommandRead(int fd, unsigned long drmCommandIndex,
-                   void *data, unsigned long size )
-{
-    unsigned long request;
-
-    request = DRM_IOR( DRM_COMMAND_BASE + drmCommandIndex, size);
-
-    if (ioctl(fd, request, data)) {
-	return -errno;
-    }
-    return 0;
-}
-
-int drmCommandWrite(int fd, unsigned long drmCommandIndex,
-                   void *data, unsigned long size )
-{
-    unsigned long request;
-
-    request = DRM_IOW( DRM_COMMAND_BASE + drmCommandIndex, size);
-
-    if (ioctl(fd, request, data)) {
-	return -errno;
-    }
-    return 0;
-}
-
-int drmCommandWriteRead(int fd, unsigned long drmCommandIndex,
-                   void *data, unsigned long size )
-{
-    unsigned long request;
-
-    request = DRM_IOWR( DRM_COMMAND_BASE + drmCommandIndex, size);
-
-    if (ioctl(fd, request, data)) {
-	return -errno;
-    }
-    return 0;
-}
-
 #if defined(XFree86Server) || defined(DRM_USE_MALLOC)
 static void drmSIGIOHandler(int interrupt, void *closure)
 {
diff --git a/linux-core/drm_context.c b/linux-core/drm_context.c
index e155946d..39267b14 100644
--- a/linux-core/drm_context.c
+++ b/linux-core/drm_context.c
@@ -555,7 +555,7 @@ static int DRM(alloc_queue)(drm_device_t *dev)
 				/* Allocate a new queue */
 	down(&dev->struct_sem);
 
-	queue = gamma_alloc(sizeof(*queue), DRM_MEM_QUEUES);
+	queue = DRM(alloc)(sizeof(*queue), DRM_MEM_QUEUES);
 	memset(queue, 0, sizeof(*queue));
 	atomic_set(&queue->use_count, 1);
 
diff --git a/linux-core/i810_dma.c b/linux-core/i810_dma.c
index 815633b6..4f434199 100644
--- a/linux-core/i810_dma.c
+++ b/linux-core/i810_dma.c
@@ -33,8 +33,6 @@
 #define __NO_VERSION__
 #include "i810.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i810_drm.h"
 #include "i810_drv.h"
 #include <linux/interrupt.h>	/* For task queue support */
 
diff --git a/linux-core/i810_drm.h b/linux-core/i810_drm.h
index 6b865d40..bff61637 100644
--- a/linux-core/i810_drm.h
+++ b/linux-core/i810_drm.h
@@ -168,34 +168,14 @@ typedef struct _drm_i810_sarea {
 
 } drm_i810_sarea_t;
 
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (xf86drmMga.h)
- */
-
-/* i810 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)
-#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)
-#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)
-#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)
-#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)
-#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)
-#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)
-#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)
-#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)
-#define DRM_IOCTL_I810_OV0INFO		DRM_IOR( 0x49, drm_i810_overlay_t)
-#define DRM_IOCTL_I810_FSTATUS		DRM_IO ( 0x4a)
-#define DRM_IOCTL_I810_OV0FLIP		DRM_IO ( 0x4b)
-#define DRM_IOCTL_I810_MC		DRM_IOW( 0x4c, drm_i810_mc_t)
-#define DRM_IOCTL_I810_RSTATUS		DRM_IO ( 0x4d )
-
 typedef struct _drm_i810_clear {
 	int clear_color;
 	int clear_depth;
 	int flags;
 } drm_i810_clear_t;
 
+
+
 /* These may be placeholders if we have more cliprects than
  * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
  * false, indicating that the buffer will be dispatched again with a
diff --git a/linux-core/i810_drv.c b/linux-core/i810_drv.c
index d1a92e2a..f792e378 100644
--- a/linux-core/i810_drv.c
+++ b/linux-core/i810_drv.c
@@ -33,8 +33,6 @@
 #include <linux/config.h>
 #include "i810.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i810_drm.h"
 #include "i810_drv.h"
 
 #define DRIVER_AUTHOR		"VA Linux Systems Inc."
diff --git a/linux-core/i830_dma.c b/linux-core/i830_dma.c
index fbdc9523..69b1c8a3 100644
--- a/linux-core/i830_dma.c
+++ b/linux-core/i830_dma.c
@@ -34,8 +34,6 @@
 #define __NO_VERSION__
 #include "i830.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i830_drm.h"
 #include "i830_drv.h"
 #include <linux/interrupt.h>	/* For task queue support */
 
diff --git a/linux-core/i830_drm.h b/linux-core/i830_drm.h
index 725ad369..e4a2a257 100644
--- a/linux-core/i830_drm.h
+++ b/linux-core/i830_drm.h
@@ -201,19 +201,6 @@ typedef struct _drm_i830_sarea {
 	int vertex_prim;
 } drm_i830_sarea_t;
 
-/* I830 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_I830_INIT		DRM_IOW( 0x40, drm_i830_init_t)
-#define DRM_IOCTL_I830_VERTEX		DRM_IOW( 0x41, drm_i830_vertex_t)
-#define DRM_IOCTL_I830_CLEAR		DRM_IOW( 0x42, drm_i830_clear_t)
-#define DRM_IOCTL_I830_FLUSH		DRM_IO ( 0x43)
-#define DRM_IOCTL_I830_GETAGE		DRM_IO ( 0x44)
-#define DRM_IOCTL_I830_GETBUF		DRM_IOWR(0x45, drm_i830_dma_t)
-#define DRM_IOCTL_I830_SWAP		DRM_IO ( 0x46)
-#define DRM_IOCTL_I830_COPY		DRM_IOW( 0x47, drm_i830_copy_t)
-#define DRM_IOCTL_I830_DOCOPY		DRM_IO ( 0x48)
-
 typedef struct _drm_i830_clear {
 	int clear_color;
 	int clear_depth;
diff --git a/linux-core/i830_drv.c b/linux-core/i830_drv.c
index ad31d1ef..904f3660 100644
--- a/linux-core/i830_drv.c
+++ b/linux-core/i830_drv.c
@@ -34,8 +34,6 @@
 #include <linux/config.h>
 #include "i830.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i830_drm.h"
 #include "i830_drv.h"
 
 #define DRIVER_AUTHOR		"VA Linux Systems Inc."
diff --git a/linux-core/mga_drv.c b/linux-core/mga_drv.c
index cc8d728e..91216d24 100644
--- a/linux-core/mga_drv.c
+++ b/linux-core/mga_drv.c
@@ -32,8 +32,6 @@
 #include <linux/config.h>
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 
 #define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
diff --git a/linux-core/r128_drv.c b/linux-core/r128_drv.c
index 32180a30..d8d7be4f 100644
--- a/linux-core/r128_drv.c
+++ b/linux-core/r128_drv.c
@@ -32,8 +32,6 @@
 #include <linux/config.h>
 #include "r128.h"
 #include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
 #include "r128_drv.h"
 #include "ati_pcigart.h"
 
diff --git a/linux-core/radeon_drv.c b/linux-core/radeon_drv.c
index 4dea95f6..847c71c9 100644
--- a/linux-core/radeon_drv.c
+++ b/linux-core/radeon_drv.c
@@ -30,8 +30,6 @@
 #include <linux/config.h>
 #include "radeon.h"
 #include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
 #include "radeon_drv.h"
 #include "ati_pcigart.h"
 
diff --git a/linux/Makefile.linux b/linux/Makefile.linux
index 893d4985..5a536a11 100644
--- a/linux/Makefile.linux
+++ b/linux/Makefile.linux
@@ -38,7 +38,7 @@
 
 # **** End of SMP/MODVERSIONS detection
 
-MODS =		gamma.o tdfx.o r128.o radeon.o
+MODS =		s3v.o gamma.o tdfx.o r128.o radeon.o
 LIBS =
 
 DRMTEMPLATES =	drm_auth.h drm_bufs.h drm_context.h drm_dma.h drm_drawable.h \
@@ -59,6 +59,9 @@ RADEONOBJS =	radeon_drv.o radeon_cp.o radeon_state.o
 RADEONHEADERS =	radeon.h radeon_drv.h radeon_drm.h $(DRMHEADERS) \
 		$(DRMTEMPLATES)
 
+S3VOBJS = s3v_drv.o s3v_dma.o
+S3VHEADERS = s3v.h s3v_drv.h s3v_drm.h $(DRMHEADERS) $(DRMTEMPLATES)
+
 INC =		/usr/include
 
 CFLAGS =	-O2 $(WARNINGS)
@@ -221,6 +224,11 @@ radeon_drv.o: radeon_drv.c
 radeon.o: $(RADEONOBJS) $(LIBS)
 	$(LD) -r $^ -o $@
 
+s3v_drv.o: s3v_drv.c
+	$(CC) $(MODCFLAGS) -DEXPORT_SYMTAB -I$(TREE) -c $< -o $@
+s3v.o: $(S3VOBJS) $(LIBS)
+	$(LD) -r $^ -o $@
+
 ifeq ($(AGP),1)
 mga_drv.o: mga_drv.c
 	$(CC) $(MODCFLAGS) -DEXPORT_SYMTAB -I$(TREE) -c $< -o $@
@@ -254,6 +262,7 @@ ChangeLog:
 
 $(GAMMAOBJS): $(GAMMAHEADERS)
 $(TDFXOBJS): $(TDFXHEADERS)
+$(S3VOBJS): $(S3VHEADERS)
 ifeq ($(AGP),1)
 $(MGAOBJS): $(MGAHEADERS)
 $(I810OBJS): $(I810HEADERS)
diff --git a/linux/drm.h b/linux/drm.h
index d116f375..1ad21860 100644
--- a/linux/drm.h
+++ b/linux/drm.h
@@ -99,6 +99,19 @@ typedef struct drm_tex_region {
 	unsigned int	age;
 } drm_tex_region_t;
 
+/* Seperate include files for the i810/mga/r128 specific structures */
+#include "mga_drm.h"
+#include "i810_drm.h"
+#include "r128_drm.h"
+#include "radeon_drm.h"
+#include "sis_drm.h"
+/* #include "i830_drm.h" */
+#include "gamma_drm.h"
+#include "s3v_drm.h"
+#ifdef CONFIG_DRM_SIS
+#include "sis_drm.h"
+#endif
+
 typedef struct drm_version {
 	int    version_major;	  /* Major version			    */
 	int    version_minor;	  /* Minor version			    */
@@ -419,8 +432,104 @@ typedef struct drm_scatter_gather {
 #define DRM_IOCTL_SG_ALLOC		DRM_IOW( 0x38, drm_scatter_gather_t)
 #define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, drm_scatter_gather_t)
 
-/* Device specfic ioctls should only be in their respective headers
- * The device specific ioctl range is 0x40 to 0x79.                  */
-#define DRM_COMMAND_BASE                0x40
+/* MGA specific ioctls */
+#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
+#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x41, drm_lock_t)
+#define DRM_IOCTL_MGA_RESET		DRM_IO(  0x42)
+#define DRM_IOCTL_MGA_SWAP		DRM_IO(  0x43)
+#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x44, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x45, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x47, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x48, drm_mga_blit_t)
+
+/* i810 specific ioctls */
+#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)
+#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)
+#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)
+#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)
+#define DRM_IOCTL_I810_OV0INFO		DRM_IOR( 0x49, drm_i810_overlay_t)
+#define DRM_IOCTL_I810_FSTATUS		DRM_IO ( 0x4a)
+#define DRM_IOCTL_I810_OV0FLIP		DRM_IO ( 0x4b)
+#define DRM_IOCTL_I810_MC		DRM_IOW( 0x4c, drm_i810_mc_t)
+#define DRM_IOCTL_I810_RSTATUS		DRM_IO ( 0x4d )
+
+
+/* Rage 128 specific ioctls */
+#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)
+#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)
+#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)
+#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_INDIRECT		DRM_IOWR(0x4f, drm_r128_indirect_t)
+#define DRM_IOCTL_R128_FULLSCREEN	DRM_IOW( 0x50, drm_r128_fullscreen_t)
+#define DRM_IOCTL_R128_CLEAR2		DRM_IOW( 0x51, drm_r128_clear2_t)
+
+/* Radeon specific ioctls */
+#define DRM_IOCTL_RADEON_CP_INIT	DRM_IOW( 0x40, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START	DRM_IO(  0x41)
+#define DRM_IOCTL_RADEON_CP_STOP	DRM_IOW( 0x42, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_RADEON_CP_IDLE	DRM_IO(  0x44)
+#define DRM_IOCTL_RADEON_RESET		DRM_IO(  0x45)
+#define DRM_IOCTL_RADEON_FULLSCREEN	DRM_IOW( 0x46, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_RADEON_CLEAR		DRM_IOW( 0x48, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX		DRM_IOW( 0x49, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES	DRM_IOW( 0x4a, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_STIPPLE	DRM_IOW( 0x4c, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_INDIRECT	DRM_IOWR(0x4d, drm_radeon_indirect_t)
+#define DRM_IOCTL_RADEON_TEXTURE	DRM_IOWR(0x4e, drm_radeon_texture_t)
+#define DRM_IOCTL_RADEON_VERTEX2	DRM_IOW( 0x4f, drm_radeon_vertex_t)
+
+/* Gamma specific ioctls */
+#define DRM_IOCTL_GAMMA_INIT		DRM_IOW( 0x40, drm_gamma_init_t)
+#define DRM_IOCTL_GAMMA_COPY		DRM_IOW( 0x41, drm_gamma_copy_t)
+
+/* SiS specific ioctls */
+#define SIS_IOCTL_FB_ALLOC		DRM_IOWR(0x44, drm_sis_mem_t)
+#define SIS_IOCTL_FB_FREE		DRM_IOW( 0x45, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_INIT		DRM_IOWR(0x53, drm_sis_agp_t)
+#define SIS_IOCTL_AGP_ALLOC		DRM_IOWR(0x54, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_FREE		DRM_IOW( 0x55, drm_sis_mem_t)
+#define SIS_IOCTL_FLIP			DRM_IOW( 0x48, drm_sis_flip_t)
+#define SIS_IOCTL_FLIP_INIT		DRM_IO(  0x49)
+#define SIS_IOCTL_FLIP_FINAL		DRM_IO(  0x50)
+
+/* I830 specific ioctls */
+#if 0
+#define DRM_IOCTL_I830_INIT		DRM_IOW( 0x40, drm_i830_init_t)
+#define DRM_IOCTL_I830_VERTEX		DRM_IOW( 0x41, drm_i830_vertex_t)
+#define DRM_IOCTL_I830_CLEAR		DRM_IOW( 0x42, drm_i830_clear_t)
+#define DRM_IOCTL_I830_FLUSH		DRM_IO ( 0x43)
+#define DRM_IOCTL_I830_GETAGE		DRM_IO ( 0x44)
+#define DRM_IOCTL_I830_GETBUF		DRM_IOWR(0x45, drm_i830_dma_t)
+#define DRM_IOCTL_I830_SWAP		DRM_IO ( 0x46)
+#define DRM_IOCTL_I830_COPY		DRM_IOW( 0x47, drm_i830_copy_t)
+#define DRM_IOCTL_I830_DOCOPY		DRM_IO ( 0x48)
+#endif
 
+/* s3v specific ioctls */
+#define DRM_IOCTL_S3V_INIT      	DRM_IOW( 0x60, drm_s3v_init_t)
+#define DRM_IOCTL_S3V_SIMPLE_LOCK   	DRM_IO(  0x6a)
+#define DRM_IOCTL_S3V_SIMPLE_FLUSH_LOCK DRM_IO(  0x6b)
+#define DRM_IOCTL_S3V_SIMPLE_UNLOCK 	DRM_IO(  0x6c)
+#define DRM_IOCTL_S3V_RESET     	DRM_IO(  0x61)
+#define DRM_IOCTL_S3V_STATUS        	DRM_IO(  0x62)
+/*
+#define DRM_IOCTL_S3V_COPY      		DRM_IOW( 0x6d, drm_s3v_copy_t)
+*/
 #endif
diff --git a/linux/drm_context.h b/linux/drm_context.h
index e155946d..39267b14 100644
--- a/linux/drm_context.h
+++ b/linux/drm_context.h
@@ -555,7 +555,7 @@ static int DRM(alloc_queue)(drm_device_t *dev)
 				/* Allocate a new queue */
 	down(&dev->struct_sem);
 
-	queue = gamma_alloc(sizeof(*queue), DRM_MEM_QUEUES);
+	queue = DRM(alloc)(sizeof(*queue), DRM_MEM_QUEUES);
 	memset(queue, 0, sizeof(*queue));
 	atomic_set(&queue->use_count, 1);
 
diff --git a/linux/gamma_dma.c b/linux/gamma_dma.c
index e18a577c..094f51d6 100644
--- a/linux/gamma_dma.c
+++ b/linux/gamma_dma.c
@@ -32,8 +32,6 @@
 #define __NO_VERSION__
 #include "gamma.h"
 #include "drmP.h"
-#include "drm.h"
-#include "gamma_drm.h"
 #include "gamma_drv.h"
 
 #include <linux/interrupt.h>	/* For task queue support */
diff --git a/linux/gamma_drm.h b/linux/gamma_drm.h
index 0d58b07b..d06763ae 100644
--- a/linux/gamma_drm.h
+++ b/linux/gamma_drm.h
@@ -48,16 +48,6 @@ typedef struct _drm_gamma_sarea {
 	int vertex_prim;
 } drm_gamma_sarea_t;
 
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (xf86drmGamma.h)
- */
-
-/* Gamma specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_GAMMA_INIT		DRM_IOW( 0x40, drm_gamma_init_t)
-#define DRM_IOCTL_GAMMA_COPY		DRM_IOW( 0x41, drm_gamma_copy_t)
-
 typedef struct drm_gamma_copy {
 	unsigned int	DMAOutputAddress;
 	unsigned int	DMAOutputCount;
diff --git a/linux/gamma_drv.c b/linux/gamma_drv.c
index 3d37a5fc..58cea241 100644
--- a/linux/gamma_drv.c
+++ b/linux/gamma_drv.c
@@ -32,8 +32,6 @@
 #include <linux/config.h>
 #include "gamma.h"
 #include "drmP.h"
-#include "drm.h"
-#include "gamma_drm.h"
 #include "gamma_drv.h"
 
 #define DRIVER_AUTHOR		"VA Linux Systems Inc."
diff --git a/linux/i810_dma.c b/linux/i810_dma.c
index 815633b6..4f434199 100644
--- a/linux/i810_dma.c
+++ b/linux/i810_dma.c
@@ -33,8 +33,6 @@
 #define __NO_VERSION__
 #include "i810.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i810_drm.h"
 #include "i810_drv.h"
 #include <linux/interrupt.h>	/* For task queue support */
 
diff --git a/linux/i810_drm.h b/linux/i810_drm.h
index 6b865d40..bff61637 100644
--- a/linux/i810_drm.h
+++ b/linux/i810_drm.h
@@ -168,34 +168,14 @@ typedef struct _drm_i810_sarea {
 
 } drm_i810_sarea_t;
 
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (xf86drmMga.h)
- */
-
-/* i810 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)
-#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)
-#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)
-#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)
-#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)
-#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)
-#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)
-#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)
-#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)
-#define DRM_IOCTL_I810_OV0INFO		DRM_IOR( 0x49, drm_i810_overlay_t)
-#define DRM_IOCTL_I810_FSTATUS		DRM_IO ( 0x4a)
-#define DRM_IOCTL_I810_OV0FLIP		DRM_IO ( 0x4b)
-#define DRM_IOCTL_I810_MC		DRM_IOW( 0x4c, drm_i810_mc_t)
-#define DRM_IOCTL_I810_RSTATUS		DRM_IO ( 0x4d )
-
 typedef struct _drm_i810_clear {
 	int clear_color;
 	int clear_depth;
 	int flags;
 } drm_i810_clear_t;
 
+
+
 /* These may be placeholders if we have more cliprects than
  * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
  * false, indicating that the buffer will be dispatched again with a
diff --git a/linux/i810_drv.c b/linux/i810_drv.c
index d1a92e2a..f792e378 100644
--- a/linux/i810_drv.c
+++ b/linux/i810_drv.c
@@ -33,8 +33,6 @@
 #include <linux/config.h>
 #include "i810.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i810_drm.h"
 #include "i810_drv.h"
 
 #define DRIVER_AUTHOR		"VA Linux Systems Inc."
diff --git a/linux/i830_dma.c b/linux/i830_dma.c
index fbdc9523..69b1c8a3 100644
--- a/linux/i830_dma.c
+++ b/linux/i830_dma.c
@@ -34,8 +34,6 @@
 #define __NO_VERSION__
 #include "i830.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i830_drm.h"
 #include "i830_drv.h"
 #include <linux/interrupt.h>	/* For task queue support */
 
diff --git a/linux/i830_drm.h b/linux/i830_drm.h
index 725ad369..e4a2a257 100644
--- a/linux/i830_drm.h
+++ b/linux/i830_drm.h
@@ -201,19 +201,6 @@ typedef struct _drm_i830_sarea {
 	int vertex_prim;
 } drm_i830_sarea_t;
 
-/* I830 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_I830_INIT		DRM_IOW( 0x40, drm_i830_init_t)
-#define DRM_IOCTL_I830_VERTEX		DRM_IOW( 0x41, drm_i830_vertex_t)
-#define DRM_IOCTL_I830_CLEAR		DRM_IOW( 0x42, drm_i830_clear_t)
-#define DRM_IOCTL_I830_FLUSH		DRM_IO ( 0x43)
-#define DRM_IOCTL_I830_GETAGE		DRM_IO ( 0x44)
-#define DRM_IOCTL_I830_GETBUF		DRM_IOWR(0x45, drm_i830_dma_t)
-#define DRM_IOCTL_I830_SWAP		DRM_IO ( 0x46)
-#define DRM_IOCTL_I830_COPY		DRM_IOW( 0x47, drm_i830_copy_t)
-#define DRM_IOCTL_I830_DOCOPY		DRM_IO ( 0x48)
-
 typedef struct _drm_i830_clear {
 	int clear_color;
 	int clear_depth;
diff --git a/linux/i830_drv.c b/linux/i830_drv.c
index ad31d1ef..904f3660 100644
--- a/linux/i830_drv.c
+++ b/linux/i830_drv.c
@@ -34,8 +34,6 @@
 #include <linux/config.h>
 #include "i830.h"
 #include "drmP.h"
-#include "drm.h"
-#include "i830_drm.h"
 #include "i830_drv.h"
 
 #define DRIVER_AUTHOR		"VA Linux Systems Inc."
diff --git a/linux/mga_dma.c b/linux/mga_dma.c
index 525975a8..2a151361 100644
--- a/linux/mga_dma.c
+++ b/linux/mga_dma.c
@@ -36,8 +36,6 @@
 #define __NO_VERSION__
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 
 #include <linux/interrupt.h>	/* For task queue support */
diff --git a/linux/mga_drm.h b/linux/mga_drm.h
index 8f56beed..4af2ca2e 100644
--- a/linux/mga_drm.h
+++ b/linux/mga_drm.h
@@ -38,7 +38,6 @@
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (mga_sarea.h)
  */
-
 #ifndef __MGA_SAREA_DEFINES__
 #define __MGA_SAREA_DEFINES__
 
@@ -226,20 +225,6 @@ typedef struct _drm_mga_sarea {
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmMga.h)
  */
-
-/* MGA specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
-#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x41, drm_lock_t)
-#define DRM_IOCTL_MGA_RESET		DRM_IO(  0x42)
-#define DRM_IOCTL_MGA_SWAP		DRM_IO(  0x43)
-#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x44, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x45, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
-#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x47, drm_mga_iload_t)
-#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x48, drm_mga_blit_t)
-
 typedef struct _drm_mga_warp_index {
    	int installed;
    	unsigned long phys_addr;
diff --git a/linux/mga_drv.c b/linux/mga_drv.c
index cc8d728e..91216d24 100644
--- a/linux/mga_drv.c
+++ b/linux/mga_drv.c
@@ -32,8 +32,6 @@
 #include <linux/config.h>
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 
 #define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
diff --git a/linux/mga_state.c b/linux/mga_state.c
index 17cbc855..16919514 100644
--- a/linux/mga_state.c
+++ b/linux/mga_state.c
@@ -35,8 +35,6 @@
 #define __NO_VERSION__
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 #include "drm.h"
 
diff --git a/linux/mga_warp.c b/linux/mga_warp.c
index 4dd998b3..fba691b1 100644
--- a/linux/mga_warp.c
+++ b/linux/mga_warp.c
@@ -30,8 +30,6 @@
 #define __NO_VERSION__
 #include "mga.h"
 #include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
 #include "mga_drv.h"
 #include "mga_ucode.h"
 
diff --git a/linux/r128_cce.c b/linux/r128_cce.c
index 72b8d767..ef11a497 100644
--- a/linux/r128_cce.c
+++ b/linux/r128_cce.c
@@ -31,8 +31,6 @@
 #define __NO_VERSION__
 #include "r128.h"
 #include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
 #include "r128_drv.h"
 
 #include <linux/interrupt.h>	/* For task queue support */
diff --git a/linux/r128_drm.h b/linux/r128_drm.h
index a8d23008..0fc6a6cd 100644
--- a/linux/r128_drm.h
+++ b/linux/r128_drm.h
@@ -170,27 +170,6 @@ typedef struct drm_r128_sarea {
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmR128.h)
  */
-
-/* Rage 128 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)
-#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)
-#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)
-#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)
-#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)
-#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)
-#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)
-#define DRM_IOCTL_R128_INDIRECT		DRM_IOWR(0x4f, drm_r128_indirect_t)
-#define DRM_IOCTL_R128_FULLSCREEN	DRM_IOW( 0x50, drm_r128_fullscreen_t)
-#define DRM_IOCTL_R128_CLEAR2		DRM_IOW( 0x51, drm_r128_clear2_t)
-
 typedef struct drm_r128_init {
 	enum {
 		R128_INIT_CCE    = 0x01,
diff --git a/linux/r128_drv.c b/linux/r128_drv.c
index 32180a30..d8d7be4f 100644
--- a/linux/r128_drv.c
+++ b/linux/r128_drv.c
@@ -32,8 +32,6 @@
 #include <linux/config.h>
 #include "r128.h"
 #include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
 #include "r128_drv.h"
 #include "ati_pcigart.h"
 
diff --git a/linux/r128_state.c b/linux/r128_state.c
index a5b925f5..9de1b6b9 100644
--- a/linux/r128_state.c
+++ b/linux/r128_state.c
@@ -30,8 +30,6 @@
 #define __NO_VERSION__
 #include "r128.h"
 #include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
 #include "r128_drv.h"
 #include "drm.h"
 #include <linux/delay.h>
diff --git a/linux/radeon_cp.c b/linux/radeon_cp.c
index 0823edd0..0acaca8e 100644
--- a/linux/radeon_cp.c
+++ b/linux/radeon_cp.c
@@ -31,8 +31,6 @@
 #define __NO_VERSION__
 #include "radeon.h"
 #include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
 #include "radeon_drv.h"
 
 #include <linux/interrupt.h>	/* For task queue support */
diff --git a/linux/radeon_drm.h b/linux/radeon_drm.h
index 6774b2bc..81e76b19 100644
--- a/linux/radeon_drm.h
+++ b/linux/radeon_drm.h
@@ -236,29 +236,7 @@ typedef struct {
 
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (xf86drmRadeon.h)
- *
- * KW: actually it's illegal to change any of this (backwards compatibility).
- */
-
-/* Radeon specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
  */
-#define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( 0x40, drm_radeon_init_t)
-#define DRM_IOCTL_RADEON_CP_START   DRM_IO(  0x41)
-#define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( 0x42, drm_radeon_cp_stop_t)
-#define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  0x43)
-#define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  0x44)
-#define DRM_IOCTL_RADEON_RESET      DRM_IO(  0x45)
-#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
-#define DRM_IOCTL_RADEON_SWAP       DRM_IO(  0x47)
-#define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( 0x48, drm_radeon_clear_t)
-#define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( 0x49, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_INDICES    DRM_IOW( 0x4a, drm_radeon_indices_t)
-#define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( 0x4c, drm_radeon_stipple_t)
-#define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(0x4d, drm_radeon_indirect_t)
-#define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(0x4e, drm_radeon_texture_t)
-#define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( 0x4f, drm_radeon_vertex_t)
-
 typedef struct drm_radeon_init {
 	enum {
 		RADEON_INIT_CP    = 0x01,
diff --git a/linux/radeon_drv.c b/linux/radeon_drv.c
index 4dea95f6..847c71c9 100644
--- a/linux/radeon_drv.c
+++ b/linux/radeon_drv.c
@@ -30,8 +30,6 @@
 #include <linux/config.h>
 #include "radeon.h"
 #include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
 #include "radeon_drv.h"
 #include "ati_pcigart.h"
 
diff --git a/linux/radeon_state.c b/linux/radeon_state.c
index 79b29134..5efa447a 100644
--- a/linux/radeon_state.c
+++ b/linux/radeon_state.c
@@ -30,9 +30,8 @@
 #define __NO_VERSION__
 #include "radeon.h"
 #include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
 #include "radeon_drv.h"
+#include "drm.h"
 #include <linux/delay.h>
 
 
@@ -748,54 +747,6 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
 		   sarea_priv->nbox, prim->start, prim->finish,
 		   prim->prim, numverts );
 
-	switch (prim->prim & RADEON_PRIM_TYPE_MASK) {
-	case RADEON_PRIM_TYPE_NONE:
-	case RADEON_PRIM_TYPE_POINT:
-		if (prim->numverts < 1) {
-			DRM_ERROR( "Bad nr verts for line %d\n",
-				   prim->numverts);
-			return;
-		}
-		break;
-	case RADEON_PRIM_TYPE_LINE:
-		if ((prim->numverts & 1) || prim->numverts == 0) {
-			DRM_ERROR( "Bad nr verts for line %d\n",
-				   prim->numverts);
-			return;
-		}
-		break;
-	case RADEON_PRIM_TYPE_LINE_STRIP:
-		if (prim->numverts < 2) {
-			DRM_ERROR( "Bad nr verts for line_strip %d\n",
-				   prim->numverts);
-			return;
-		}
-		break;
-	case RADEON_PRIM_TYPE_TRI_LIST:
-	case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
-	case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
-	case RADEON_PRIM_TYPE_RECT_LIST:
-		if (prim->numverts % 3 || prim->numverts == 0) {
-			DRM_ERROR( "Bad nr verts for tri %d\n",
-				   prim->numverts);
-			return;
-		}
-		break;
-	case RADEON_PRIM_TYPE_TRI_FAN:
-	case RADEON_PRIM_TYPE_TRI_STRIP:
-		if (prim->numverts < 3) {
-			DRM_ERROR( "Bad nr verts for strip/fan %d\n",
-				   prim->numverts);
-			return;
-		}
-		break;
-	default:
-		DRM_ERROR( "buffer prim %x start %x\n", 
-			   prim->prim, prim->start );
-		return;
-	}	
-
-
 	buf_priv->dispatched = 1;
 
 	do {
@@ -904,51 +855,6 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
 		   prim->start, start, prim->finish,
 		   count, prim->numverts, offset );
 
-	switch (prim->prim & RADEON_PRIM_TYPE_MASK) {
-	case RADEON_PRIM_TYPE_NONE:
-	case RADEON_PRIM_TYPE_POINT:
-		if (count < 1) {
-			DRM_ERROR( "Bad nr verts %d\n",
-				   count);
-			return;
-		}
-		break;
-	case RADEON_PRIM_TYPE_LINE:
-		if ((count & 1) || count == 0) {
-			DRM_ERROR( "Bad nr verts for line %d\n",
-				   count);
-			return;
-		}
-		break;
-	case RADEON_PRIM_TYPE_LINE_STRIP:
-		if (count < 2) {
-			DRM_ERROR( "Bad nr verts for line_strip %d\n",
-				   count);
-			return;
-		}
-		break;
-	case RADEON_PRIM_TYPE_TRI_LIST:
-	case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
-	case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
-	case RADEON_PRIM_TYPE_RECT_LIST:
-		if (count % 3 || count == 0) {
-			DRM_ERROR( "Bad nr verts for tri %d\n", count);
-			return;
-		}
-		break;
-	case RADEON_PRIM_TYPE_TRI_FAN:
-	case RADEON_PRIM_TYPE_TRI_STRIP:
-		if (count < 3) {
-			DRM_ERROR( "Bad nr verts for strip/fan %d\n", count);
-			return;
-		}
-		break;
-	default:
-		DRM_ERROR( "buffer prim %x start %x\n", 
-			   prim->prim, prim->start );
-		return;
-	}	
-
 	if ( start < prim->finish ) {
 		buf_priv->dispatched = 1;
 
@@ -1315,33 +1221,30 @@ int radeon_cp_vertex( struct inode *inode, struct file *filp,
 
 	buf->used = vertex.count; /* not used? */
 
-	if (vertex.count) {
-		if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
-			radeon_emit_state( dev_priv,
-					   &sarea_priv->context_state,
-					   sarea_priv->tex_state,
-					   sarea_priv->dirty );
-			
-			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
-					       RADEON_UPLOAD_TEX1IMAGES |
-					       RADEON_UPLOAD_TEX2IMAGES |
-					       RADEON_REQUIRE_QUIESCENCE);
-		}
+	if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
+		radeon_emit_state( dev_priv,
+				   &sarea_priv->context_state,
+				   sarea_priv->tex_state,
+				   sarea_priv->dirty );
 
-		/* Build up a prim_t record:
-		 */
-		prim.start = 0;
-		prim.finish = vertex.count; /* unused */
-		prim.prim = vertex.prim;
-		prim.stateidx = 0xff;	/* unused */
-		prim.numverts = vertex.count;
-		prim.vc_format = dev_priv->sarea_priv->vc_format;
-		
-		radeon_cp_dispatch_vertex( dev, buf, &prim );
+		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
+				       RADEON_UPLOAD_TEX1IMAGES |
+				       RADEON_UPLOAD_TEX2IMAGES |
+				       RADEON_REQUIRE_QUIESCENCE);
 	}
 
+	/* Build up a prim_t record:
+	 */
+	prim.start = 0;
+	prim.finish = vertex.count; /* unused */
+	prim.prim = vertex.prim;
+	prim.stateidx = 0xff;	/* unused */
+	prim.numverts = vertex.count;
+	prim.vc_format = dev_priv->sarea_priv->vc_format;
+	
+	radeon_cp_dispatch_vertex( dev, buf, &prim );
 	if (vertex.discard) {
-		radeon_cp_discard_buffer( dev, buf );
+	   radeon_cp_discard_buffer( dev, buf );
 	}
 
 	return 0;
@@ -1433,10 +1336,10 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
 	/* Build up a prim_t record:
 	 */
 	prim.start = elts.start;
-	prim.finish = elts.end; 
+	prim.finish = elts.end; /* unused */
 	prim.prim = elts.prim;
 	prim.stateidx = 0xff;	/* unused */
-	prim.numverts = 0;	/* indexed from start of dma area */
+	prim.numverts = count;
 	prim.vc_format = dev_priv->sarea_priv->vc_format;
 	
 	radeon_cp_dispatch_indices( dev, buf, &prim );
diff --git a/linux/s3v.h b/linux/s3v.h
new file mode 100644
index 00000000..9d8f6e10
--- /dev/null
+++ b/linux/s3v.h
@@ -0,0 +1,72 @@
+/*
+ * Author: Max Lingua <sunmax@libero.it>
+ */
+
+#ifndef _S3V_H
+#define _S3V_H
+
+/* This remains constant for all DRM template files.
+ */
+#define DRM(x) s3v_##x
+
+/* #define __FAST 0 */
+/* General customization:
+ */
+#define __HAVE_MTRR		1
+/* #define __HAVE_SG       	1 */
+#define __HAVE_AGP          	1
+#define __MUST_HAVE_AGP         0
+/* #define __HAVE_CTX_BITMAP	1 */
+
+/* DMA customization:
+ */
+#define	__HAVE_DMA			1
+#define __HAVE_PCI_DMA      		1
+#define __HAVE_OLD_DMA			1
+/* "GH: This is a big hack for now..."    *
+ * Gareth? Is it you? What does that mean */
+#define __HAVE_DMA_FLUSH        	0
+#define __HAVE_DMA_SCHEDULE 		0
+#define __HAVE_DMA_WAITQUEUE    	0
+#define __HAVE_MULTIPLE_DMA_QUEUES  	0
+/* #define __HAVE_DMA_QUEUE		1 */ /* check */
+#define __HAVE_DMA_WAITLIST     	1
+#define __HAVE_DMA_FREELIST		1
+#define __HAVE_DMA_IRQ          	0
+
+#define __HAVE_DMA_READY        	0
+#define DRIVER_DMA_READY() do {     \
+ /*   s3v_dma_ready(dev); */        \
+} while (0)
+
+/* Driver customization:
+ */
+
+#define DRIVER_PREINSTALL() do {					\
+	drm_s3v_private_t *dev_priv =					\
+		(drm_s3v_private_t *)dev->dev_private;		\
+	/* write something in regs where needed */		\
+} while (0)
+
+#define DRIVER_POSTINSTALL() do {					\
+	drm_s3v_private_t *dev_priv =					\
+		(drm_s3v_private_t *)dev->dev_private;		\
+	/* write something in regs where needed */      \
+} while (0)
+
+#define DRIVER_UNINSTALL() do {						\
+	drm_s3v_private_t *dev_priv =					\
+		(drm_s3v_private_t *)dev->dev_private;		\
+	/* write something in regs where needed */      \
+} while (0)
+
+/* Buffer customization:
+ */
+
+#define DRIVER_BUF_PRIV_T	drm_s3v_buf_priv_t
+
+/* needed from DRM(mapbufs) even if you don't habe agp ; ( */
+#define DRIVER_AGP_BUFFERS_MAP( dev )                   \
+    ((drm_s3v_private_t *)((dev)->dev_private))->buffer_map
+										/* ... ->buffers */
+#endif
diff --git a/linux/s3v_dma.c b/linux/s3v_dma.c
new file mode 100644
index 00000000..4dacfa03
--- /dev/null
+++ b/linux/s3v_dma.c
@@ -0,0 +1,599 @@
+/*
+ * Author: Max Lingua <sunmax@libero.it>
+ */
+
+#include "s3v.h"
+#include "drmP.h"
+#include "s3v_drv.h"
+
+#include <linux/timex.h>
+#include <linux/interrupt.h>	/* For task queue support */
+#include <linux/delay.h>
+#include <linux/tqueue.h>
+#include <linux/wait.h>
+
+#if 0
+	#define S3V_DEBUG(fmt, arg...) \
+	do { \
+		printk(KERN_DEBUG \
+			"[" DRM_NAME ":" __FUNCTION__ "] " fmt , ##arg); \
+	} while (0)
+#else
+	#define S3V_DEBUG(fmt, arg...)       do { } while (0)
+#endif
+
+/* Uncomment next line if you are using a Virge DX */
+/* It should not hurt on other Virges though */
+/* #define _VIRGEDX */
+#define S3V_UDELAY 1 /* 1000 */
+
+struct tq_struct s3v_dma_task;
+struct semaphore s3v_buf_sem;
+struct semaphore s3v_gfx_sem;
+
+/* FIXME: no global */
+int _got, _sent, _freed, _reset;
+volatile int _check;
+
+void s3v_do_reset(drm_device_t *dev)
+{
+	drm_s3v_private_t *dev_priv =
+		(drm_s3v_private_t *)dev->dev_private;
+	u32 tmp, wp, rp;
+
+	printk(KERN_ERR "*** s3v_do_reset: #%i\n", _reset); 
+	_reset++;
+
+	if (!s3v_dma_is_ready(dev))
+		printk(KERN_ERR "and !s3v_dma_is_ready: -BAD-\n");
+
+        S3V_FIFOSPACE(3);
+		S3V_WRITE(S3V_CMD_DMA_ENABLE_REG, 0x0);
+                S3V_WRITE(0x850C, (0x1 << 1));
+                S3V_WRITE(0x850C, (0x0 << 1));
+
+
+	S3V_FIFOSPACE(2);
+		S3V_WRITE(S3V_CMD_DMA_WRITEP_REG, (0x0000 << 2));
+		S3V_WRITE(S3V_CMD_DMA_READP_REG, (0x0000 << 2));
+
+#if 1
+	outb_p(0x66, 0x3d4);
+	tmp = inb_p(0x3d5);
+	outb_p(tmp | 0x02, 0x3d5);
+	outb_p(tmp & ~0x02, 0x3d5);
+#endif
+
+	wp = (S3V_READ(S3V_CMD_DMA_WRITEP_REG) & 0xFFFC) >> 2;
+	rp = (S3V_READ(S3V_CMD_DMA_READP_REG) & 0xFFFC) >> 2;
+
+	S3V_FIFOSPACE(1);
+		S3V_WRITE(S3V_CMD_DMA_ENABLE_REG, 0x1);
+
+/*	printk(KERN_ERR "wp = 0x%x; rp = 0x%x\n", wp, rp); */
+	S3V_DEBUG("wp = 0x%x; rp = 0x%x\n", wp, rp);
+
+	_got = _sent = _freed = 0;
+}
+
+int s3v_reset( struct inode *inode, struct file *filp,
+	unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	
+	s3v_do_reset(dev);
+
+	return 0;
+}
+
+int s3v_simple_lock( struct inode *inode, struct file *filp,
+        unsigned int cmd, unsigned long arg )
+{
+/*
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+*/
+	/* printk(KERN_ERR "s3v_simple_lock\n"); */
+
+	if (down_interruptible(&s3v_buf_sem))
+		return -ERESTARTSYS;
+	else
+		return 0;
+}
+
+int s3v_simple_flush_lock( struct inode *inode, struct file *filp,
+        unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_device_dma_t *dma = dev->dma;
+
+	/* printk(KERN_ERR "s3v_simple_flush_lock\n"); */
+
+	/* we flush bufs already on queue */
+
+	/* FIXME: do we need the following? */
+	/*
+	if (dma->next_buffer) {
+		wake_up_interruptible(&dma->waiting);
+		printk(KERN_ERR "*** dma->next_buffer ***\n");
+	}
+	*/
+	while (dma->this_buffer || !(s3v_dma_is_ready(dev))) {
+		if (!_check) {
+			_check++;
+			queue_task(&s3v_dma_task, &tq_timer);
+		}
+		/* printk(KERN_ERR "a) dma->this_buffer=%p _check=%i\n",
+			dma->this_buffer, _check); */
+		interruptible_sleep_on(&dma->waiting);
+		/* printk(KERN_ERR "b) dma->this_buffer=%p _check=%i\n",
+			dma->this_buffer, _check); */
+	}
+
+	if (down_interruptible(&s3v_buf_sem))
+		return -ERESTARTSYS;
+	else
+		return 0;
+}
+
+int s3v_simple_unlock( struct inode *inode, struct file *filp,
+        unsigned int cmd, unsigned long arg )
+{
+/*
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+*/
+/*	printk(KERN_ERR "s3v_simple_unlock\n"); */
+
+	up(&s3v_buf_sem);
+
+	return 0;
+}
+
+void s3v_do_status(drm_device_t *dev)
+{
+	drm_s3v_private_t *dev_priv =
+		(drm_s3v_private_t *)dev->dev_private;
+	u32 wp, rp;
+
+	udelay(S3V_UDELAY);
+
+	wp = (S3V_READ(S3V_CMD_DMA_WRITEP_REG) & 0xFFFC) >> 2;
+	rp = (S3V_READ(S3V_CMD_DMA_READP_REG) & 0xFFFC) >> 2;
+
+	printk(KERN_ERR "[status] wp = 0x%x; rp = 0x%x\n", wp, rp);
+
+}
+
+int s3v_status( struct inode *inode, struct file *filp,
+        unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	
+	s3v_do_status(dev);
+
+	return 0;
+}
+
+void s3v_dma_check(void* _dev)
+{
+	drm_device_t *dev = (drm_device_t*) _dev;
+	drm_s3v_private_t *dev_priv =
+                (drm_s3v_private_t *)dev->dev_private;
+	drm_device_dma_t *dma = dev->dma;
+
+	int wp, rp;
+	static u16 times=0;
+
+	if (_check>1)
+		printk(KERN_ERR "_check = %i\n", _check);
+
+	if (times>40) {
+        	s3v_do_reset(dev);
+	}
+
+	udelay(S3V_UDELAY);
+
+	wp = (S3V_READ(S3V_CMD_DMA_WRITEP_REG) & 0xFFFC) >> 2;
+	rp = (S3V_READ(S3V_CMD_DMA_READP_REG) & 0xFFFC) >> 2;
+
+/*	rmb(); */
+
+	if(wp==rp) {
+/*
+		printk(KERN_ERR "*** buf completed after %i times\n",
+			times);
+*/
+		_check = 0;
+		times = 0; 
+		dma->this_buffer->pending = 0;
+		dma->this_buffer = NULL; 
+/*
+		printk(KERN_ERR "[waking up the neighbours]\n");
+		mdelay(1);
+*/
+	/* s3v_lock_free(dev,&dev->lock.hw_lock->lock,DRM_KERNEL_CONTEXT); */
+		up(&s3v_gfx_sem);
+		wake_up_interruptible(&dma->waiting);
+	} else {
+		times++; 
+		queue_task(&s3v_dma_task, &tq_timer);
+	}
+}
+
+static inline void s3v_dma_dispatch(drm_device_t *dev, drm_buf_t *dma_buf)
+{
+	drm_s3v_private_t *dev_priv =
+		(drm_s3v_private_t *)dev->dev_private;
+
+	drm_buf_t    *buf = dev->dma->buflist[S3V_DMA_BUF_NR];
+	unsigned int *pgt = buf->address;
+
+	down_interruptible(&s3v_buf_sem); 
+	
+	S3V_DEBUG("dma_buf->idx = %i\n", dma_buf->idx);
+	S3V_DEBUG("dma_buf->used = %i\n", dma_buf->used);
+	S3V_DEBUG("pgt[dma_buf->idx]) = 0x%x\n", pgt[dma_buf->idx]);
+
+	_sent++;
+
+#if 0
+do {
+	int i, reg, first_reg, num_commands;
+
+	first_reg = *(int*)(dma_buf->address) >> 14;
+	num_commands = *(int*)(dma_buf->address) & 0xFFFF;
+
+	for(i=1; i<dma_buf->used/4; i++)
+	{
+		reg = first_reg+i*4;
+		S3V_DEBUG("LOOK: 0x%x = %x\n", reg,
+                        *(int*)(dma_buf->address+(i)*4));
+	}
+} while(0);		
+#endif
+
+	/* FIXME: this should reset dma read & write regs, but... */
+	S3V_FIFOSPACE(2);
+		S3V_WRITE(0x850C, (0x1 << 1));
+		S3V_WRITE(0x850C, (0x0 << 1));
+
+#ifdef _VIRGEDX
+	S3V_FIFOSPACE(4);
+#else
+	S3V_FIFOSPACE(3);
+#endif
+	S3V_WRITE(S3V_CMD_DMA_BASEADDR_REG, pgt[dma_buf->idx]); 
+
+	S3V_WRITE(S3V_CMD_DMA_WRITEP_REG, (0x0000 << 2));
+	S3V_WRITE(S3V_CMD_DMA_READP_REG, (0x0000 << 2));
+
+	/* FIXME: next one seems to be a must on DX (to avoid lockups) */
+	/* I still could not determine if this help on MX too */
+	/* Anyone with GX? */
+#ifdef _VIRGEDX
+	S3V_WRITE(S3V_CMD_DMA_ENABLE_REG, 0x1);
+#endif
+
+	S3V_FIFOSPACE(1);
+        S3V_WRITE( S3V_CMD_DMA_WRITEP_REG,
+                   (dma_buf->used)
+                   | S3V_CMD_DMA_WRITEP_UPDATE );
+
+	up(&s3v_buf_sem); 
+}
+
+inline int s3v_dma_is_ready(drm_device_t *dev)
+{
+	drm_s3v_private_t *dev_priv =
+		(drm_s3v_private_t *)dev->dev_private;
+
+	int wp, rp;
+
+	udelay(S3V_UDELAY);
+
+	wp = (S3V_READ(S3V_CMD_DMA_WRITEP_REG) & 0xFFFC) >> 2;
+	rp = (S3V_READ(S3V_CMD_DMA_READP_REG) & 0xFFFC) >> 2;
+
+	/* rmb(); */
+
+	return !(wp-rp);	/* !(0) == 1 == TRUE: is ready */
+}
+
+static int s3v_dma_send_buffers(drm_device_t *dev, drm_dma_t *d)
+{
+	drm_buf_t        *buf = NULL;
+	int              idx;
+	drm_device_dma_t *dma = dev->dma;
+
+	S3V_DEBUG("got %d buf of %i size\n", d->send_count, d->send_sizes[0]);
+
+#if 0
+	for (i = 0; i < d->send_count; i++) {
+                idx = d->send_indices[i];
+	}
+#else
+	idx = d->send_indices[0];
+#endif
+	S3V_DEBUG("idx = %i\n", idx);
+
+	buf = dma->buflist[ idx ];
+	buf->used = d->send_sizes[0];
+
+	S3V_DEBUG("buf @ %p\n", buf->address);
+
+	while (!(s3v_dma_is_ready(dev))) {
+	/* a buf is already being processed by gfx card. It could be:
+	 * [a] a buffer of this context (dma->this_buffer)
+	 * [b] a buffer of another context (!dma->this_buffer)
+	 */
+		dma->next_buffer = buf;
+	
+		if (!_check) {
+		/* _check is global. If set our timeout task is
+		 * already running. We do not need to run it twice
+		 * mmm ... use tasklets?
+		 */
+			_check++;
+			queue_task(&s3v_dma_task, &tq_timer);
+		}
+
+		interruptible_sleep_on(&dma->waiting);
+	}
+
+	if (dma->this_buffer) {
+		dma->next_buffer=NULL;
+	/* s3v_lock_free(dev,&dev->lock.hw_lock->lock,DRM_KERNEL_CONTEXT); */
+		up(&s3v_gfx_sem);
+	}
+
+	/* needed? */
+        if(!buf) {
+		printk(KERN_ERR "send: !buf\n");
+		return 0;
+	}
+
+	dma->this_buffer=buf;
+	dma->this_buffer->pending = 1;
+
+	down_interruptible(&s3v_gfx_sem);
+	/* s3v_lock_take(&dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); */
+	s3v_dma_dispatch(dev, dma->this_buffer);
+
+	return 0;
+}
+
+int s3v_dma(struct inode *inode, struct file *filp, unsigned int cmd,
+	      unsigned long arg)
+{
+	drm_file_t	  	 *priv	 = filp->private_data;
+	drm_device_t	 *dev	 = priv->dev;
+	drm_device_dma_t *dma	 = dev->dma;
+	int			 retcode = 0;
+	drm_dma_t	  	 d;
+	int			 idx;
+
+	if (copy_from_user(&d, (drm_dma_t *)arg, sizeof(d)))
+		return -EFAULT;
+
+	if (d.send_count < 0 || d.send_count > dma->buf_count) {
+		DRM_ERROR("Process %d trying to send %d buffers (of %d max)\n",
+			  current->pid, d.send_count, dma->buf_count);
+		return -EINVAL;
+	}
+
+	if (d.request_count < 0 || d.request_count > dma->buf_count) {
+		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
+			  current->pid, d.request_count, dma->buf_count);
+		return -EINVAL;
+	}
+
+	if (d.send_count) {
+		DRM_DEBUG("*** [dma] SENDING ***\n");
+		DRM_DEBUG("d.send_count=%i of (dma->buf_count) %i\n",
+                d.send_count, dma->buf_count);
+		S3V_DEBUG("IDX -d.send_list[0]- =%i; SIZE -d.send_sizes[0]- =%i\n",
+                (d.send_indices)[0], (d.send_sizes)[0]);
+
+		if (d.flags & _DRM_DMA_PRIORITY)
+			retcode = 0; /* s3v_dma_priority(dev, &d); */
+		else
+			retcode = s3v_dma_send_buffers(dev, &d);
+	}
+
+	d.granted_count = 0;
+
+	if (!retcode && d.request_count) {
+		retcode = s3v_dma_get_buffers(dev, &d);
+		idx = (d.request_indices)[0];
+		S3V_DEBUG("****************\n");
+		S3V_DEBUG("* getting #%i  *\n", idx);
+		S3V_DEBUG("****************\n");
+
+		_got++;
+	}
+
+	DRM_DEBUG("%d returning, granted = %d\n",
+		  current->pid, d.granted_count);
+		  
+	if (copy_to_user((drm_dma_t *)arg, &d, sizeof(d)))
+		return -EFAULT;
+
+	return retcode;
+}
+
+/* =============================================================
+ * DMA initialization, cleanup
+ */
+int s3v_do_cleanup_dma( drm_device_t *dev )
+{
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	if ( dev->dev_private ) {
+		drm_s3v_private_t *dev_priv = dev->dev_private;
+#if 0
+		if (!dev_priv->pcimode)
+			DRM_IOREMAPFREE( dev_priv->buffer_map );
+#endif
+		DRM(free)( dev_priv, sizeof(drm_s3v_private_t),	DRM_MEM_DRIVER );
+		dev_priv = NULL;
+	}
+	
+	return 0;
+}
+
+static int s3v_do_init_dma( drm_device_t *dev, drm_s3v_init_t *init )
+{
+	drm_s3v_private_t *dev_priv;
+	drm_device_dma_t  *dma = dev->dma;
+	drm_buf_t         *buf;
+	int i;
+	struct list_head *list;
+	unsigned int     *pgt;
+
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
+
+	dev_priv = DRM(alloc)( sizeof(drm_s3v_private_t),
+                            DRM_MEM_DRIVER );
+	if ( !dev_priv )
+		return -ENOMEM;
+
+	dev->dev_private = (void *)dev_priv;
+
+	/* FIXME: gather all init code */
+
+	_check = 0;
+	init_waitqueue_head(&dma->waiting);
+	s3v_dma_task.routine = s3v_dma_check;
+	s3v_dma_task.data = (void*) dev;
+	sema_init(&s3v_buf_sem, 1);
+	sema_init(&s3v_gfx_sem, 1);
+
+	memset( dev_priv, 0, sizeof(drm_s3v_private_t) );
+
+	list_for_each(list, &dev->maplist->head) {
+		drm_map_list_t *r_list = (drm_map_list_t *)list;
+		if( r_list->map &&
+		r_list->map->type == _DRM_SHM &&
+		r_list->map->flags & _DRM_CONTAINS_LOCK ) {
+			dev_priv->sarea_map = r_list->map;
+			break;
+		}
+	}
+
+	if(!dev_priv->sarea_map) {
+		dev->dev_private = (void *)dev_priv;
+		s3v_do_cleanup_dma(dev);
+		DRM_ERROR("can not find sarea!\n");
+		return -EINVAL;
+	}
+	DRM_DEBUG("SAREA found\n");
+
+	dev_priv->sarea_priv = (drm_s3v_sarea_t *)
+		((u8 *)dev_priv->sarea_map->handle +
+		init->sarea_priv_offset);
+
+	DRM_FIND_MAP( dev_priv->mmio_map, init->mmio_offset );
+	if(!dev_priv->mmio_map) {
+		dev->dev_private = (void *)dev_priv;
+		s3v_do_cleanup_dma(dev);
+		DRM_ERROR("can not find mmio map!\n");
+		return -EINVAL;
+	}
+	DRM_DEBUG("MMIO found\n");
+
+	/* FIXME: ! */
+	init->pcimode = 1;
+    
+	if (init->pcimode) {
+		S3V_DEBUG("Card is PCI\n");
+		for (i=0; i<S3V_DMA_BUF_NR; i++)
+			DRM_DEBUG("buf #%i @%p\n", i, dma->buflist[i]->address);
+
+	        buf = dma->buflist[S3V_DMA_BUF_NR];
+	        pgt = buf->address;
+
+	        for (i = 0; i < S3V_DMA_BUF_NR; i++) {
+			DRM_DEBUG("virt_to_phys: round #%i of %i: ",
+				i, S3V_DMA_BUF_NR);
+			
+			buf = dma->buflist[i];
+			DRM_DEBUG("from (virt) %p ", buf->address);
+
+#ifdef S3V_BUF_4K
+			*pgt = ((virt_to_phys((void*)buf->address)) & 0xfffff000);
+#else
+			*pgt = ((virt_to_phys((void*)buf->address)) & 0xfffff000) |
+				S3V_CMD_DMA_BUFFERSIZE_64K;
+#endif
+/* or simpler: virt_to_phys((void*)buf->address|S3V_CMD_DMA_BUFFERSIZE_64K) */
+
+			DRM_DEBUG("to (phys) 0x%x\n", *pgt);
+			pgt++;
+        	}
+
+		buf = dma->buflist[S3V_DMA_BUF_NR];
+		pgt = buf->address;
+
+		for (i = 0; i < S3V_DMA_BUF_NR; i++)
+			S3V_DEBUG("*** NEW *** buf#%i @ 0x%x\n",
+				i, *pgt++);
+
+        	buf = dma->buflist[S3V_DMA_BUF_NR];
+	} else {
+		/* Where in the world is S3Virge AGP ? */
+		S3V_DEBUG("Card is AGP\n");
+	}
+
+	DRM_DEBUG("init some values\n");
+
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->front_width = init->front_width;
+	dev_priv->front_height = init->front_height;
+	dev_priv->front_pitch = init->front_pitch;  /* stride */
+
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->back_width = init->back_width;
+	dev_priv->back_height = init->back_height;
+	dev_priv->back_pitch = init->back_pitch;
+
+	dev_priv->depth_offset = init->depth_offset;
+	dev_priv->depth_width = init->depth_width;
+	dev_priv->depth_height = init->depth_height;
+	dev_priv->depth_pitch = init->depth_pitch;
+
+/*
+	S3V_FIFOSPACE(1);
+	S3V_WRITE(0x8504, (0x5 << 5));
+*/
+	return 0;
+}
+
+int s3v_dma_init( struct inode *inode, struct file *filp,
+          unsigned int cmd, unsigned long arg )
+{
+	drm_file_t *priv = filp->private_data;
+	drm_device_t *dev = priv->dev;
+	drm_s3v_init_t init;
+
+	_reset=0;
+
+	if ( copy_from_user( &init, (drm_s3v_init_t *)arg, sizeof(init) ) )
+	        return -EFAULT;
+
+	switch ( init.func ) {
+	case S3V_INIT_DMA:
+	        printk(KERN_ERR "init dma\n");
+        	return s3v_do_init_dma( dev, &init );
+	case S3V_CLEANUP_DMA:
+		printk(KERN_ERR "cleanup dma\n");
+		printk(KERN_ERR "_reset = %i\n", _reset);
+        	return s3v_do_cleanup_dma( dev );
+	}
+
+	return -EINVAL;
+}
diff --git a/linux/s3v_drm.h b/linux/s3v_drm.h
new file mode 100644
index 00000000..5d646601
--- /dev/null
+++ b/linux/s3v_drm.h
@@ -0,0 +1,159 @@
+/*
+ * Author: Max Lingua <sunmax@libero.it>
+ */
+
+#ifndef _S3V_DRM_H
+#define _S3V_DRM_H
+
+/* WARNING: These defines must be the same as what the Xserver uses.
+ * if you change them, you must change the defines in the Xserver.
+ */
+
+#ifndef _S3V_DEFINES
+#define _S3V_DEFINES
+
+/* #define S3V_BUF_4K 1 */
+
+#ifdef S3V_BUF_4K
+	#define S3V_DMA_BUF_ORDER 12
+	#define S3V_DMA_BUF_NR    256
+#else
+	#define S3V_DMA_BUF_ORDER 16 /* -much- better */
+	#define S3V_DMA_BUF_NR    16
+#endif
+/* on s3virge you can only choose between *
+ * 4k (2^12) and 64k (2^16) dma bufs      */
+#define S3V_DMA_BUF_SZ        (1<<S3V_DMA_BUF_ORDER)
+
+#define S3V_NR_SAREA_CLIPRECTS 8
+
+/* Each region is a minimum of 16k (64*64@4bpp)
+ * and there are at most 40 of them.
+ */
+#define S3V_NR_TEX_REGIONS 64 /* was 40 */
+#define S3V_LOG_TEX_GRANULARITY 16 /* was 4 */
+/* 40 * (2 ^ 4) = 640k, that's all we have for tex on 4mb gfx card */
+/* FIXME: will it work with card with less than 4mb? */
+/* FIXME: we should set this at run time */
+
+#endif	/* _S3V_DEFINES */
+
+/* FIXME: all of the following have to be checked: do we need them? */
+
+#define S3V_UPLOAD_TEX0IMAGE  0x1 /* handled clientside */
+#define S3V_UPLOAD_TEX1IMAGE  0x2 /* handled clientside */
+#define S3V_UPLOAD_CTX        0x4
+#define S3V_UPLOAD_BUFFERS    0x8
+#define S3V_UPLOAD_TEX0       0x10
+#define S3V_UPLOAD_TEX1       0x20
+#define S3V_UPLOAD_CLIPRECTS  0x40
+
+#define S3V_FRONT   0x1
+#define S3V_BACK    0x2
+#define S3V_DEPTH   0x4
+
+typedef struct _drm_s3v_init {
+	enum {
+		S3V_INIT_DMA = 0x01,
+		S3V_CLEANUP_DMA = 0x02
+	} func;
+
+	unsigned int pcimode;	/* bool: 1=pci 0=agp */
+
+	unsigned int mmio_offset;
+	unsigned int buffers_offset;
+	unsigned int sarea_priv_offset;
+
+	unsigned int front_offset;
+	unsigned int front_width;
+	unsigned int front_height;
+	unsigned int front_pitch;
+
+	unsigned int back_offset;
+	unsigned int back_width;
+	unsigned int back_height;
+	unsigned int back_pitch;
+
+	unsigned int depth_offset;
+	unsigned int depth_width;
+	unsigned int depth_height;
+	unsigned int depth_pitch;
+	
+	unsigned int texture_offset;
+} drm_s3v_init_t;
+
+/* Warning: If you change the SAREA structure you must change the Xserver
+ * structure as well */
+
+typedef struct _drm_s3v_tex_region {
+	unsigned char next, prev; 	/* indices to form a circular LRU  */
+	unsigned char in_use;		/* owned by a client, or free? */
+	int age;			/* tracked by clients to update local LRU's */
+} drm_s3v_tex_region_t;
+
+typedef struct _drm_s3v_sarea {
+
+   	unsigned int dirty;
+
+	unsigned int nbox;
+	drm_clip_rect_t boxes[S3V_NR_SAREA_CLIPRECTS];
+
+	/* Maintain an LRU of contiguous regions of texture space.  If
+	 * you think you own a region of texture memory, and it has an
+	 * age different to the one you set, then you are mistaken and
+	 * it has been stolen by another client.  If global texAge
+	 * hasn't changed, there is no need to walk the list.
+	 *
+	 * These regions can be used as a proxy for the fine-grained
+	 * texture information of other clients - by maintaining them
+	 * in the same lru which is used to age their own textures,
+	 * clients have an approximate lru for the whole of global
+	 * texture space, and can make informed decisions as to which
+	 * areas to kick out.  There is no need to choose whether to
+	 * kick out your own texture or someone else's - simply eject
+	 * them all in LRU order.  
+	 */
+   
+	drm_s3v_tex_region_t texList[S3V_NR_TEX_REGIONS+1]; /* Last elt is sentinal */
+
+	int texAge;		/* last time texture was uploaded */
+	int last_enqueue;	/* last time a buffer was enqueued */
+	int last_dispatch;	/* age of the most recently dispatched buffer */
+	int last_quiescent;	/*  */
+	int ctxOwner;		/* last context to upload state */
+
+	int vertex_prim;
+
+} drm_s3v_sarea_t;
+
+typedef struct _drm_s3v_clear {
+	int clear_color;
+	int clear_depth;
+	int flags;
+} drm_s3v_clear_t;
+
+/* These may be placeholders if we have more cliprects than
+ * S3V_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
+ * false, indicating that the buffer will be dispatched again with a
+ * new set of cliprects.
+ */
+typedef struct _drm_s3v_vertex {
+   	int idx;	/* buffer index */
+	int used;	/* nr bytes in use */
+	int discard;	/* client is finished with the buffer? */
+} drm_s3v_vertex_t;
+
+typedef struct _drm_s3v_copy {
+   	int idx;	/* buffer index */
+	int used;	/* nr bytes in use */
+	void *address;	/* Address to copy from */
+} drm_s3v_copy_t;
+
+typedef struct _drm_s3v_dma {
+	void *virtual;
+	int request_idx;
+	int request_size;
+	int granted;
+} drm_s3v_dma_t;
+
+#endif /* _S3V_DRM_H */
diff --git a/linux/s3v_drv.c b/linux/s3v_drv.c
new file mode 100644
index 00000000..328c833c
--- /dev/null
+++ b/linux/s3v_drv.c
@@ -0,0 +1,74 @@
+/*
+ * Author: Max Lingua <sunmax@libero.it>
+ */
+
+#include <linux/config.h>
+#include "s3v.h"
+#include "drmP.h"
+#include "s3v_drv.h"
+
+#define DRIVER_AUTHOR		"Max Lingua (ladybug)"
+
+#define DRIVER_NAME		"s3v"
+#define DRIVER_DESC		"S3 Virge 3D"
+#define DRIVER_DATE		"20020207"
+
+#define DRIVER_MAJOR		2
+#define DRIVER_MINOR		0
+#define DRIVER_PATCHLEVEL	0
+
+#define DRIVER_IOCTLS \
+  [DRM_IOCTL_NR(DRM_IOCTL_DMA)]     	      = { s3v_dma,           1, 0 }, \
+  [DRM_IOCTL_NR(DRM_IOCTL_S3V_INIT)]          = { s3v_dma_init,      1, 1 }, \
+  [DRM_IOCTL_NR(DRM_IOCTL_S3V_RESET)]         = { s3v_reset,         1, 0 }, \
+  [DRM_IOCTL_NR(DRM_IOCTL_S3V_SIMPLE_LOCK)]   = { s3v_simple_lock,   1, 0 }, \
+  [DRM_IOCTL_NR(DRM_IOCTL_S3V_SIMPLE_FLUSH_LOCK)] = \
+                                          { s3v_simple_flush_lock,   1, 0 }, \
+  [DRM_IOCTL_NR(DRM_IOCTL_S3V_SIMPLE_UNLOCK)] = { s3v_simple_unlock, 1, 0 }, \
+  [DRM_IOCTL_NR(DRM_IOCTL_S3V_STATUS)]        = { s3v_status,        1, 0 }
+
+#define IOCTL_TABLE_NAME    DRM(ioctls)
+#define IOCTL_FUNC_NAME     DRM(ioctl)
+
+#define __HAVE_COUNTERS     3
+#define __HAVE_COUNTER6     _DRM_STAT_DMA
+#define __HAVE_COUNTER7     _DRM_STAT_PRIMARY
+#define __HAVE_COUNTER8     _DRM_STAT_SECONDARY
+
+
+#include "drm_auth.h"
+#include "drm_bufs.h"
+#include "drm_context.h"
+#include "drm_dma.h"
+#include "drm_drawable.h"
+#include "drm_drv.h"
+
+#ifndef MODULE
+/* DRM(options) is called by the kernel to parse command-line options
+ * passed via the boot-loader (e.g., LILO).  It calls the insmod option
+ * routine, drm_parse_drm.
+ */
+
+/* JH- We have to hand expand the string ourselves because of the cpp.  If
+ * anyone can think of a way that we can fit into the __setup macro without
+ * changing it, then please send the solution my way.
+ */
+static int __init s3v_options( char *str )
+{
+	DRM(parse_options)( str );
+	return 1;
+}
+
+__setup( DRIVER_NAME "=", s3v_options );
+#endif
+
+#include "drm_fops.h"
+#include "drm_init.h"
+#include "drm_ioctl.h"
+#include "drm_lock.h"
+#include "drm_lists.h"
+#include "drm_memory.h"
+#include "drm_proc.h"
+#include "drm_vm.h"
+#include "drm_stub.h"
+#include "drm_scatter.h"
diff --git a/linux/s3v_drv.h b/linux/s3v_drv.h
new file mode 100644
index 00000000..40834d3e
--- /dev/null
+++ b/linux/s3v_drv.h
@@ -0,0 +1,138 @@
+/*
+ * Author: Max Lingua <sunmax@libero.it>
+ */
+
+#ifndef _S3V_DRV_H
+#define _S3V_DRV_H
+
+typedef struct _drm_s3v_buf_priv {
+   	u32 *in_use;
+   	int use_idx;
+	int currently_mapped;
+	void *virtual;
+	void *kernel_virtual;
+	int map_count;
+   	struct vm_area_struct *vma;
+} drm_s3v_buf_priv_t;
+
+typedef struct _drm_s3v_private {
+	drm_map_t *sarea_map;
+	drm_map_t *buffer_map;
+	drm_map_t *mmio_map;
+
+	drm_s3v_sarea_t *sarea_priv;
+
+	unsigned int  pcimode;
+   	unsigned long hw_status_page;
+   	unsigned long counter;
+
+   	atomic_t flush_done;
+   	wait_queue_head_t flush_queue;	/* Processes waiting until flush */
+	drm_buf_t *mmap_buffer;
+
+	unsigned int mmio_offset;
+	unsigned int buffers_offset;
+	unsigned int sarea_priv_offset;
+
+	unsigned int front_offset;
+	unsigned int front_width;
+	unsigned int front_height;
+	unsigned int front_pitch;
+
+	unsigned int back_offset;
+	unsigned int back_width;
+	unsigned int back_height;
+	unsigned int back_pitch;
+
+	unsigned int depth_offset;
+	unsigned int depth_width;
+	unsigned int depth_height;
+	unsigned int depth_pitch;
+
+	u32 front_di1, back_di1, zi1;
+
+	unsigned int usec_timeout;
+} drm_s3v_private_t;
+
+			/* s3v_dma.c */
+extern int  s3v_dma_init(struct inode *inode, struct file *filp,
+            unsigned int cmd, unsigned long arg);
+extern int  s3v_dma(struct inode *inode, struct file *filp,
+            unsigned int cmd, unsigned long arg);
+/* extern int  s3v_dma_schedule(drm_device_t *dev, int locked); */
+/* extern void s3v_dma_ready(drm_device_t *dev); */
+extern inline int s3v_dma_is_ready(drm_device_t *dev);
+extern int  s3v_test(struct inode *inode, struct file *filp,
+            unsigned int cmd, unsigned long arg);
+extern int  s3v_reset(struct inode *inode, struct file *filp,
+            unsigned int cmd, unsigned long arg);
+extern int s3v_simple_lock(struct inode *inode, struct file *filp,
+            unsigned int cmd, unsigned long arg);
+extern int s3v_simple_flush_lock(struct inode *inode, struct file *filp,
+            unsigned int cmd, unsigned long arg);
+extern int s3v_simple_unlock(struct inode *inode, struct file *filp,
+            unsigned int cmd, unsigned long arg);
+extern int  s3v_status(struct inode *inode, struct file *filp,
+            unsigned int cmd, unsigned long arg);
+/*
+extern void s3v_dma_quiescent(drm_device_t *dev);
+*/
+
+#define LOCK_TEST_WITH_RETURN( dev )                    \
+do {                                    \
+    if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||       \
+         dev->lock.pid != current->pid ) {              \
+        DRM_ERROR( "%s called without lock held\n",     \
+               __FUNCTION__ );              \
+        return -EINVAL;                     \
+    }                               \
+} while (0)
+
+#define S3V_VERBOSE 		0
+#define S3V_TIMEOUT_USEC        1000000
+
+#define S3V_BASE(reg)		((unsigned long) dev_priv->mmio_map->handle)
+#define S3V_ADDR(reg)		(S3V_BASE(reg) + reg)
+#define S3V_READ(reg)		readl(S3V_ADDR(reg))
+#define S3V_WRITE(reg,val) 	do \
+				  { writel(val, S3V_ADDR(reg)); wmb(); } \
+				while (0)
+#define S3V_READ16(reg)		readw(S3V_ADDR(reg))	
+#define S3V_WRITE16(reg,val)	do \
+				  { writew(val, S3V_ADDR(reg)); wmb(); } \
+				while (0)
+
+
+/* Subsystem control register */
+#define S3V_SUB_CTRL_REG            	0x8504	/* reg base */
+#define S3V_SUB_CTRL_S3DON          	0x0040	/* offset */
+
+/* Subsystem status register */
+#define S3V_SUB_STAT_REG            	0x8504	/* reg base */
+#define S3V_SUB_STAT_VSYNC_INT      	0x0001	/* offsets */
+#define S3V_SUB_STAT_3D_DONE_INT        0x0002
+#define S3V_SUB_STAT_FIFO_OVR_INT       0x0004
+#define S3V_SUB_STAT_FIFO_EMPTY_INT     0x0008
+#define S3V_SUB_STAT_HDMA_DONE_INT      0x0010
+#define S3V_SUB_STAT_CDMA_DONE_INT      0x0020
+#define S3V_SUB_STAT_S3D_FIFO_EMPTY_INT 0x0040
+#define S3V_SUB_STAT_LPB_INT        	0x0080
+#define S3V_SUB_STAT_3DBUSY         	0x0200
+
+#define S3V_FIFOSPACE(n) \
+do { \
+	udelay(1); \
+} while(((S3V_READ(S3V_SUB_STAT_REG) >> 8) & 0x1f) < n)
+
+/* Command DMA buffer stuff */
+#define S3V_CMD_DMA_BASEADDR_REG        0x8590	/* reg base */
+#define S3V_CMD_DMA_BUFFERSIZE_4K       0x0000	/* offsets */
+#define S3V_CMD_DMA_BUFFERSIZE_64K      0x0002
+#define S3V_CMD_DMA_WRITEP_REG      	0x8594	/* reg base */
+#define S3V_CMD_DMA_READP_REG       	0x8598	/* reg base */
+#define S3V_CMD_DMA_RWP_MASK        	0x00FC	/* offsets */
+#define S3V_CMD_DMA_WRITEP_UPDATE       0x010000
+#define S3V_CMD_DMA_ENABLE_REG      	0x859C	/* reg base */
+#define S3V_CMD_DMA_ENABLE          	0x0001	/* offset */
+
+#endif	/* _S3V_DRV_H */
diff --git a/linux/s3v_regs.h b/linux/s3v_regs.h
new file mode 100644
index 00000000..3423d614
--- /dev/null
+++ b/linux/s3v_regs.h
@@ -0,0 +1,348 @@
+/*
+ * Author: Max Lingua <sunmax@libero.it>
+ */
+
+#ifndef _S3V_REG_H
+#define _S3V_REG_H
+
+#define S3V_REGS_NUM 256
+
+/************
+ * DMA REGS *
+ ************/
+
+#define S3V_DMA_ID							0
+#define S3V_DMA_REG                         0x8590
+#define S3V_DMA_WRITEP_ID					1
+#define S3V_DMA_WRITEP_REG                  0x8594
+#define S3V_DMA_READP_ID					2
+#define S3V_DMA_READP_REG                   0x8598
+#define S3V_DMA_ENABLE_ID					3
+#define S3V_DMA_ENABLE_REG                  0x859C
+#define S3V_DMA_UPDATE_ID					4
+#define S3V_DMA_UPDATE_REG					0x10000
+
+/***************
+ * STATUS REGS *
+ ***************/
+
+#define S3V_STAT_ID							10
+#define S3V_STAT_REG                        0x8504
+#define S3V_STAT_VSYNC_ID					11
+#define S3V_STAT_VSYNC_REG                  0x8505
+#define S3V_STAT_3D_DONE_ID					12
+#define S3V_STAT_3D_DONE_REG                0x8506
+#define S3V_STAT_FIFO_OVER_ID				13
+#define S3V_STAT_FIFO_OVER_REG              0x8508
+#define S3V_STAT_FIFO_EMPTY_ID				14
+#define S3V_STAT_FIFO_EMPTY_REG             0x850C
+#define S3V_STAT_HDMA_DONE_ID				15
+#define S3V_STAT_HDMA_DONE_REG              0x8514
+#define S3V_STAT_CDMA_DONE_ID				16
+#define S3V_STAT_CDMA_DONE_REG              0x8524
+#define S3V_STAT_3D_FIFO_EMPTY_ID			17
+#define S3V_STAT_3D_FIFO_EMPTY_REG          0x8544
+#define S3V_STAT_LPB_ID						18
+#define S3V_STAT_LPB_REG                    0x8584
+#define S3V_STAT_3D_BUSY_ID					19
+#define S3V_STAT_3D_BUSY_REG                0x8704
+
+/***********
+ * 2D REGS *
+ ***********/
+
+#define S3V_BITBLT_ID						30
+#define S3V_BITBLT_REG						0xA400
+#define S3V_BITBLT_SRC_BASE_ID				31
+#define S3V_BITBLT_SRC_BASE_REG				0xA4D4
+#define S3V_BITBLT_DEST_BASE_ID				32
+#define S3V_BITBLT_DEST_BASE_REG			0xA4D8
+#define S3V_BITBLT_CLIP_L_R_ID				33
+#define S3V_BITBLT_CLIP_L_R_REG				0xA4DC
+#define S3V_BITBLT_CLIP_T_B_ID				34
+#define S3V_BITBLT_CLIP_T_B_REG				0xA4E0
+#define S3V_BITBLT_DEST_SRC_STRIDE_ID		35
+#define S3V_BITBLT_DEST_SRC_STRIDE_REG		0xA4E4
+#define S3V_BITBLT_MONO_PAT0_ID				36
+#define S3V_BITBLT_MONO_PAT0_REG			0xA4E8
+#define S3V_BITBLT_MONO_PAT1_ID				37
+#define S3V_BITBLT_MONO_PAT1_REG			0xA4EC
+#define S3V_BITBLT_PAT_BG_COLOR_ID			38
+#define S3V_BITBLT_PAT_BG_COLOR_REG			0xA4F0
+#define S3V_BITBLT_PAT_FG_COLOR_ID			39
+#define S3V_BITBLT_PAT_FG_COLOR_REG			0xA4F4
+#define S3V_BITBLT_CMDSET_ID				40
+#define S3V_BITBLT_CMDSET_REG				0xA500
+#define S3V_BITBLT_WIDTH_HEIGHT_ID			41
+#define S3V_BITBLT_WIDTH_HEIGHT_REG			0xA504
+#define S3V_BITBLT_SRC_X_Y_ID				42
+#define S3V_BITBLT_SRC_X_Y_REG				0xA508
+#define S3V_BITBLT_DEST_X_Y_ID				43
+#define S3V_BITBLT_DEST_X_Y_REG				0xA50C
+#define S3V_2DLINE_ID						44
+#define S3V_2DLINE_REG						0xA800
+#define S3V_2DPOLY_ID						45
+#define S3V_2DPOLY_REG						0xAC00
+
+/***************
+ * 3DLINE REGS *
+ ***************/
+/* base regs */
+#define S3V_3DLINE_ID                  		50
+#define S3V_3DLINE_REG						0xB000
+#define S3V_3DLINE_Z_BASE_ID           		51
+#define S3V_3DLINE_Z_BASE_REG				0xB0D4
+#define S3V_3DLINE_SRC_BASE_ID         		52   /* it is the same reg */
+#define S3V_3DLINE_SRC_BASE_REG				0xB0D4
+#define S3V_3DLINE_DEST_BASE_ID        		53
+#define S3V_3DLINE_DEST_BASE_REG			0xB0D8
+#define S3V_3DLINE_CLIP_L_R_ID         		54
+#define S3V_3DLINE_CLIP_L_R_REG				0xB0DC
+#define S3V_3DLINE_CLIP_T_B_ID				55
+#define S3V_3DLINE_CLIP_T_B_REG         	0xB0E0
+#define S3V_3DLINE_DEST_SRC_STRIDE_ID		56
+#define S3V_3DLINE_DEST_SRC_STRIDE_REG  	0xB0E4
+#define S3V_3DLINE_Z_STRIDE_ID       		57
+#define S3V_3DLINE_Z_STRIDE_REG  			0xB0E8
+#define S3V_3DLINE_TEX_BASE_ID				58
+#define S3V_3DLINE_TEX_BASE_REG         	0xB0EC
+#define S3V_3DLINE_TEX_B_COLOR_ID			59
+#define S3V_3DLINE_TEX_B_COLOR_REG      	0xB0F0
+#define S3V_3DLINE_FOG_COLOR_ID  			60
+#define S3V_3DLINE_FOG_COLOR_REG      		0xB0F4
+#define S3V_3DLINE_COLOR0_ID   				61
+#define S3V_3DLINE_COLOR0_REG        		0xB0F8
+#define S3V_3DLINE_COLOR1_ID				62
+#define S3V_3DLINE_COLOR1_REG           	0xB0FC
+#define S3V_3DLINE_CMDSET_ID				63
+#define S3V_3DLINE_CMDSET_REG            	0xB100 /* special */
+/* tex regs */  /* FIXME: shouldn't it be a 1D tex for lines? */
+#define S3V_3DLINE_BASEV_ID 				64
+#define S3V_3DLINE_BASEV_REG          		0xB104 
+#define S3V_3DLINE_BASEU_ID					65
+#define S3V_3DLINE_BASEU_REG            	0xB108
+#define S3V_3DLINE_WXD_ID  					66
+#define S3V_3DLINE_WXD_REG             		0xB10C
+#define S3V_3DLINE_WYD_ID 					67
+#define S3V_3DLINE_WYD_REG              	0xB110
+#define S3V_3DLINE_WSTART_ID				68
+#define S3V_3DLINE_WSTART_REG          		0xB114
+#define S3V_3DLINE_DXD_ID   				69
+#define S3V_3DLINE_DXD_REG          		0xB118
+#define S3V_3DLINE_VXD_ID					70
+#define S3V_3DLINE_VXD_REG              	0xB11C
+#define S3V_3DLINE_UXD_ID					71
+#define S3V_3DLINE_UXD_REG              	0xB120
+#define S3V_3DLINE_DYD_ID					72
+#define S3V_3DLINE_DYD_REG              	0xB124
+#define S3V_3DLINE_VYD_ID					73
+#define S3V_3DLINE_VYD_REG              	0xB128
+#define S3V_3DLINE_UYD_ID					74
+#define S3V_3DLINE_UYD_REG              	0xB12C
+#define S3V_3DLINE_DSTART_ID				75
+#define S3V_3DLINE_DSTART_REG           	0xB130
+#define S3V_3DLINE_VSTART_ID				76
+#define S3V_3DLINE_VSTART_REG           	0xB134
+#define S3V_3DLINE_USTART_ID				77
+#define S3V_3DLINE_USTART_REG           	0xB138
+/* gourad regs */
+#define S3V_3DLINE_GBD_ID   				78
+#define S3V_3DLINE_GBD_REG            		0xB144
+#define S3V_3DLINE_ARD_ID 					79
+#define S3V_3DLINE_ARD_REG             		0xB148
+#define S3V_3DLINE_GS_BS_ID					80
+#define S3V_3DLINE_GS_BS_REG            	0xB14C
+#define S3V_3DLINE_AS_RS_ID					81
+#define S3V_3DLINE_AS_RS_REG             	0xB150
+/* vertex regs */
+#define S3V_3DLINE_DZ_ID    				82
+#define S3V_3DLINE_DZ_REG            		0xB158
+#define S3V_3DLINE_ZSTART_ID				83
+#define S3V_3DLINE_ZSTART_REG            	0xB15C
+#define S3V_3DLINE_XEND0_END1_ID			84
+#define S3V_3DLINE_XEND0_END1_REG       	0xB16C
+#define S3V_3DLINE_DX_ID        			85
+#define S3V_3DLINE_DX_REG        			0xB170
+#define S3V_3DLINE_XSTART_ID				86
+#define S3V_3DLINE_XSTART_REG           	0xB174
+#define S3V_3DLINE_YSTART_ID 				87
+#define S3V_3DLINE_YSTART_REG          		0xB178
+#define S3V_3DLINE_YCNT_ID  				88
+#define S3V_3DLINE_YCNT_REG           		0xB17C
+
+/**************
+ * 3DTRI REGS *
+ **************/
+/* base regs */
+#define S3V_3DTRI_ID                   		100
+#define S3V_3DTRI_REG						0xB400
+#define S3V_3DTRI_Z_BASE_ID					101
+#define S3V_3DTRI_Z_BASE_REG            	0xB4D4
+#define S3V_3DTRI_SRC_BASE_ID          		102 /* it is the same reg */
+#define S3V_3DTRI_SRC_BASE_REG				0xB4D4
+#define S3V_3DTRI_DEST_BASE_ID         		103
+#define S3V_3DTRI_DEST_BASE_REG				0xB4D8
+#define S3V_3DTRI_CLIP_L_R_ID          		104
+#define S3V_3DTRI_CLIP_L_R_REG 				0xB4DC
+#define S3V_3DTRI_CLIP_T_B_ID          		105
+#define S3V_3DTRI_CLIP_T_B_REG				0xB4E0
+#define S3V_3DTRI_DEST_SRC_STRIDE_ID   		106
+#define S3V_3DTRI_DEST_SRC_STRIDE_REG		0xB4E4
+#define S3V_3DTRI_Z_STRIDE_ID          		107
+#define S3V_3DTRI_Z_STRIDE_REG				0xB4E8
+#define S3V_3DTRI_TEX_BASE_ID          		108
+#define S3V_3DTRI_TEX_BASE_REG				0xB4EC
+#define S3V_3DTRI_TEX_B_COLOR_ID       		109
+#define S3V_3DTRI_TEX_B_COLOR_REG			0xB4F0
+#define S3V_3DTRI_FOG_COLOR_ID         		110
+#define S3V_3DTRI_FOG_COLOR_REG				0xB4F4
+#define S3V_3DTRI_COLOR0_ID            		111
+#define S3V_3DTRI_COLOR0_REG				0xB4F8
+#define S3V_3DTRI_COLOR1_ID            		112
+#define S3V_3DTRI_COLOR1_REG				0xB4FC
+#define S3V_3DTRI_CMDSET_ID            		113  /* special */
+#define S3V_3DTRI_CMDSET_REG				0xB500
+/* tex regs */
+#define S3V_3DTRI_BASEV_ID             		114
+#define S3V_3DTRI_BASEV_REG					0xB504
+#define S3V_3DTRI_BASEU_ID             		115
+#define S3V_3DTRI_BASEU_REG					0xB508
+#define S3V_3DTRI_WXD_ID               		116
+#define S3V_3DTRI_WXD_REG					0xB50C
+#define S3V_3DTRI_WYD_ID               		117
+#define S3V_3DTRI_WYD_REG					0xB510
+#define S3V_3DTRI_WSTART_ID            		118
+#define S3V_3DTRI_WSTART_REG 				0xB514
+#define S3V_3DTRI_DXD_ID               		119
+#define S3V_3DTRI_DXD_REG					0xB518
+#define S3V_3DTRI_VXD_ID               		120
+#define S3V_3DTRI_VXD_REG					0xB51C
+#define S3V_3DTRI_UXD_ID            		121
+#define S3V_3DTRI_UXD_REG					0xB520
+#define S3V_3DTRI_DYD_ID            		122
+#define S3V_3DTRI_DYD_REG					0xB524
+#define S3V_3DTRI_VYD_ID            		123
+#define S3V_3DTRI_VYD_REG					0xB528
+#define S3V_3DTRI_UYD_ID            		124
+#define S3V_3DTRI_UYD_REG					0xB52C
+#define S3V_3DTRI_DSTART_ID         		125
+#define S3V_3DTRI_DSTART_REG				0xB530
+#define S3V_3DTRI_VSTART_ID         		126
+#define S3V_3DTRI_VSTART_REG				0xB534
+#define S3V_3DTRI_USTART_ID         		127
+#define S3V_3DTRI_USTART_REG				0xB538
+/* gourad regs */
+#define S3V_3DTRI_GBX_ID               		128
+#define S3V_3DTRI_GBX_REG					0xB53C
+#define S3V_3DTRI_ARX_ID               		129
+#define S3V_3DTRI_ARX_REG					0xB540
+#define S3V_3DTRI_GBY_ID					130
+#define S3V_3DTRI_GBY_REG               	0xB544
+#define S3V_3DTRI_ARY_ID					131
+#define S3V_3DTRI_ARY_REG               	0xB548
+#define S3V_3DTRI_GS_BS_ID					132
+#define S3V_3DTRI_GS_BS_REG             	0xB54C
+#define S3V_3DTRI_AS_RS_ID					133
+#define S3V_3DTRI_AS_RS_REG             	0xB550
+/* vertex regs */
+#define S3V_3DTRI_ZXD_ID               		134
+#define S3V_3DTRI_ZXD_REG					0xB554
+#define S3V_3DTRI_ZYD_ID               		135
+#define S3V_3DTRI_ZYD_REG					0xB558
+#define S3V_3DTRI_ZSTART_ID            		136
+#define S3V_3DTRI_ZSTART_REG				0xB55C
+#define S3V_3DTRI_TXDELTA12_ID         		137
+#define S3V_3DTRI_TXDELTA12_REG				0xB560
+#define S3V_3DTRI_TXEND12_ID           		138
+#define S3V_3DTRI_TXEND12_REG				0xB564
+#define S3V_3DTRI_TXDELTA01_ID         		139
+#define S3V_3DTRI_TXDELTA01_REG				0xB568
+#define S3V_3DTRI_TXEND01_ID           		140
+#define S3V_3DTRI_TXEND01_REG				0xB56C
+#define S3V_3DTRI_TXDELTA02_ID         		141
+#define S3V_3DTRI_TXDELTA02_REG				0xB570
+#define S3V_3DTRI_TXSTART02_ID         		142
+#define S3V_3DTRI_TXSTART02_REG 			0xB574
+#define S3V_3DTRI_TYS_ID               		143
+#define S3V_3DTRI_TYS_REG					0xB578
+#define S3V_3DTRI_TY01_Y12_ID          		144
+#define S3V_3DTRI_TY01_Y12_REG				0xB57C
+
+/* COMMANDS (to 0xB100 [lines] or 0xB500 [tris]) */
+
+/* Auto execute */
+#define AUTO_EXEC_OFF		(0x0)
+#define AUTO_EXEC_ON		(0x1)
+/* HW clipping */
+#define HW_CLIP_OFF			(0x0 << 1)
+#define HW_CLIP_ON			(0x1 << 1)
+/* Destination color */
+#define DEST_COL_PAL		(0x0 << 2)	/* 8 bpp - palettized */
+#define DEST_COL_1555		(0x1 << 2)	/* 16 bpp - ZRGB */
+#define DEST_COL_888  		(0x2 << 2)	/* 24 bpp - RGB */
+/* Texture color */
+#define TEX_COL_ARGB8888	(0x0 << 5)	/* 32 bpp - ARGB */
+#define TEX_COL_ARGB4444	(0x1 << 5)  /* 16 bpp - ARGB */
+#define TEX_COL_ARGB1555	(0x2 << 5)  /* 16 bpp - ARGB */
+#define TEX_COL_ALPHA4		(0x3 << 5)  /* 8 bpp - ALPHA4 */
+#define TEX_COL_BLEND4_LOW 	(0x4 << 5)  /* 4 bpp - BLEND4 low nibble */
+#define TEX_COL_BLEND4_HIGH	(0x5 << 5)  /* 4 bpp - BLEND4 high nibble */
+#define TEX_COL_PAL			(0x6 << 5)	/* 8 bpp - palettized */
+#define TEX_COL_YUV			(0x7 << 5)	/* 16 bpp - YUV */
+/* Mipmap level */
+#define MIPMAP_LEVEL(s)		(s << 8)	/* 8 -> 11 bits */
+/* Texture filtering */
+#define MIP_NEAREST			(0x0 << 12)
+#define LINEAR_MIP_NEAREST  (0x1 << 12)
+#define MIP_LINEAR	        (0x2 << 12)
+#define LINEAR_MIP_LINEAR   (0x3 << 12)
+#define NEAREST		        (0x4 << 12)
+#define FAST_BILINEAR       (0x5 << 12)
+#define LINEAR		        (0x6 << 12)
+/* Texture blending */
+#define TEX_REFLECT			(0x0 << 15)
+#define TEX_MODULATE        (0x1 << 15)
+#define TEX_DECAL	        (0x2 << 15)
+/* Fog */
+#define FOG_OFF				(0x0 << 17)
+#define FOG_ON              (0x1 << 17)
+/* Alpha blending */
+#define ALPHA_OFF			(0x0 << 18) | (0x0 << 19)
+#define ALPHA_TEX			(0x2 << 18)
+#define ALPHA_SRC           (0x3 << 18)
+/* Depth compare mode */
+#define Z_NEVER     		(0x0 << 20)
+#define Z_GREATER   		(0x1 << 20)
+#define Z_EQUAL     		(0x2 << 20)
+#define Z_GEQUAL    		(0x3 << 20)
+#define Z_LESS      		(0x4 << 20)
+#define Z_NOTEQUAL  		(0x5 << 20)
+#define Z_LEQUAL    		(0x6 << 20) 
+#define Z_ALWAYS   			(0x7 << 20)
+/* Depth update */
+#define Z_UPDATE_OFF		(0x0 << 23)	/* disable z update */
+#define Z_UPDATE_ON         (0x1 << 23)
+/* Depth buffering mode */
+#define Z_BUFFER			(0x0 << 24) | (0x0 << 25)
+#define Z_MUX_BUF			(0x1 << 24) | (0x0 << 25)
+#define Z_MUX_DRAW			(0x2 << 24)
+#define Z_OFF				(0x3 << 24) /* no z buffering */
+/* Texture wrapping */
+#define TEX_WRAP_OFF		(0x0 << 26)
+#define TEX_WRAP_ON			(0x1 << 26)
+/* 3d command */
+#define DO_GOURAD_TRI		 (0x0 << 27)
+#define DO_TEX_LIT_TRI_OLD	 (0x1 << 27) 
+#define DO_TEX_UNLIT_TRI_OLD (0x2 << 27)
+#define DO_TEX_LIT_TRI		 (0x5 << 27)
+#define DO_TEX_UNLIT_TRI	 (0x6 << 27)
+#define DO_3D_LINE			 (0x8 << 27)
+#define	DO_NOP				 (0xf << 27) /* turn on autoexec */
+/* status */
+#define CMD_2D				 (0x0 << 31) /* execute a 2d cmd */
+#define CMD_3D				 (0x1 << 31) /* execute a 3d cmd */
+
+/* to remove */
+#define Z_MASK      		(0x1 << 23)
+
+#endif
diff --git a/linux/sis_drm.h b/linux/sis_drm.h
index 8aaee224..339ed5a0 100644
--- a/linux/sis_drm.h
+++ b/linux/sis_drm.h
@@ -2,16 +2,6 @@
 #ifndef _sis_drm_public_h_
 #define _sis_drm_public_h_
 
-/* SiS specific ioctls */
-#define SIS_IOCTL_FB_ALLOC		DRM_IOWR(0x44, drm_sis_mem_t)
-#define SIS_IOCTL_FB_FREE		DRM_IOW( 0x45, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_INIT		DRM_IOWR(0x53, drm_sis_agp_t)
-#define SIS_IOCTL_AGP_ALLOC		DRM_IOWR(0x54, drm_sis_mem_t)
-#define SIS_IOCTL_AGP_FREE		DRM_IOW( 0x55, drm_sis_mem_t)
-#define SIS_IOCTL_FLIP			DRM_IOW( 0x48, drm_sis_flip_t)
-#define SIS_IOCTL_FLIP_INIT		DRM_IO(  0x49)
-#define SIS_IOCTL_FLIP_FINAL		DRM_IO(  0x50)
-
 typedef struct {
   int context;
   unsigned int offset;
diff --git a/shared-core/drm.h b/shared-core/drm.h
index d116f375..1ad21860 100644
--- a/shared-core/drm.h
+++ b/shared-core/drm.h
@@ -99,6 +99,19 @@ typedef struct drm_tex_region {
 	unsigned int	age;
 } drm_tex_region_t;
 
+/* Seperate include files for the i810/mga/r128 specific structures */
+#include "mga_drm.h"
+#include "i810_drm.h"
+#include "r128_drm.h"
+#include "radeon_drm.h"
+#include "sis_drm.h"
+/* #include "i830_drm.h" */
+#include "gamma_drm.h"
+#include "s3v_drm.h"
+#ifdef CONFIG_DRM_SIS
+#include "sis_drm.h"
+#endif
+
 typedef struct drm_version {
 	int    version_major;	  /* Major version			    */
 	int    version_minor;	  /* Minor version			    */
@@ -419,8 +432,104 @@ typedef struct drm_scatter_gather {
 #define DRM_IOCTL_SG_ALLOC		DRM_IOW( 0x38, drm_scatter_gather_t)
 #define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, drm_scatter_gather_t)
 
-/* Device specfic ioctls should only be in their respective headers
- * The device specific ioctl range is 0x40 to 0x79.                  */
-#define DRM_COMMAND_BASE                0x40
+/* MGA specific ioctls */
+#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
+#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x41, drm_lock_t)
+#define DRM_IOCTL_MGA_RESET		DRM_IO(  0x42)
+#define DRM_IOCTL_MGA_SWAP		DRM_IO(  0x43)
+#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x44, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x45, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x47, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x48, drm_mga_blit_t)
+
+/* i810 specific ioctls */
+#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)
+#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)
+#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)
+#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)
+#define DRM_IOCTL_I810_OV0INFO		DRM_IOR( 0x49, drm_i810_overlay_t)
+#define DRM_IOCTL_I810_FSTATUS		DRM_IO ( 0x4a)
+#define DRM_IOCTL_I810_OV0FLIP		DRM_IO ( 0x4b)
+#define DRM_IOCTL_I810_MC		DRM_IOW( 0x4c, drm_i810_mc_t)
+#define DRM_IOCTL_I810_RSTATUS		DRM_IO ( 0x4d )
+
+
+/* Rage 128 specific ioctls */
+#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)
+#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)
+#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)
+#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_INDIRECT		DRM_IOWR(0x4f, drm_r128_indirect_t)
+#define DRM_IOCTL_R128_FULLSCREEN	DRM_IOW( 0x50, drm_r128_fullscreen_t)
+#define DRM_IOCTL_R128_CLEAR2		DRM_IOW( 0x51, drm_r128_clear2_t)
+
+/* Radeon specific ioctls */
+#define DRM_IOCTL_RADEON_CP_INIT	DRM_IOW( 0x40, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START	DRM_IO(  0x41)
+#define DRM_IOCTL_RADEON_CP_STOP	DRM_IOW( 0x42, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_RADEON_CP_IDLE	DRM_IO(  0x44)
+#define DRM_IOCTL_RADEON_RESET		DRM_IO(  0x45)
+#define DRM_IOCTL_RADEON_FULLSCREEN	DRM_IOW( 0x46, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_RADEON_CLEAR		DRM_IOW( 0x48, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX		DRM_IOW( 0x49, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES	DRM_IOW( 0x4a, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_STIPPLE	DRM_IOW( 0x4c, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_INDIRECT	DRM_IOWR(0x4d, drm_radeon_indirect_t)
+#define DRM_IOCTL_RADEON_TEXTURE	DRM_IOWR(0x4e, drm_radeon_texture_t)
+#define DRM_IOCTL_RADEON_VERTEX2	DRM_IOW( 0x4f, drm_radeon_vertex_t)
+
+/* Gamma specific ioctls */
+#define DRM_IOCTL_GAMMA_INIT		DRM_IOW( 0x40, drm_gamma_init_t)
+#define DRM_IOCTL_GAMMA_COPY		DRM_IOW( 0x41, drm_gamma_copy_t)
+
+/* SiS specific ioctls */
+#define SIS_IOCTL_FB_ALLOC		DRM_IOWR(0x44, drm_sis_mem_t)
+#define SIS_IOCTL_FB_FREE		DRM_IOW( 0x45, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_INIT		DRM_IOWR(0x53, drm_sis_agp_t)
+#define SIS_IOCTL_AGP_ALLOC		DRM_IOWR(0x54, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_FREE		DRM_IOW( 0x55, drm_sis_mem_t)
+#define SIS_IOCTL_FLIP			DRM_IOW( 0x48, drm_sis_flip_t)
+#define SIS_IOCTL_FLIP_INIT		DRM_IO(  0x49)
+#define SIS_IOCTL_FLIP_FINAL		DRM_IO(  0x50)
+
+/* I830 specific ioctls */
+#if 0
+#define DRM_IOCTL_I830_INIT		DRM_IOW( 0x40, drm_i830_init_t)
+#define DRM_IOCTL_I830_VERTEX		DRM_IOW( 0x41, drm_i830_vertex_t)
+#define DRM_IOCTL_I830_CLEAR		DRM_IOW( 0x42, drm_i830_clear_t)
+#define DRM_IOCTL_I830_FLUSH		DRM_IO ( 0x43)
+#define DRM_IOCTL_I830_GETAGE		DRM_IO ( 0x44)
+#define DRM_IOCTL_I830_GETBUF		DRM_IOWR(0x45, drm_i830_dma_t)
+#define DRM_IOCTL_I830_SWAP		DRM_IO ( 0x46)
+#define DRM_IOCTL_I830_COPY		DRM_IOW( 0x47, drm_i830_copy_t)
+#define DRM_IOCTL_I830_DOCOPY		DRM_IO ( 0x48)
+#endif
 
+/* s3v specific ioctls */
+#define DRM_IOCTL_S3V_INIT      	DRM_IOW( 0x60, drm_s3v_init_t)
+#define DRM_IOCTL_S3V_SIMPLE_LOCK   	DRM_IO(  0x6a)
+#define DRM_IOCTL_S3V_SIMPLE_FLUSH_LOCK DRM_IO(  0x6b)
+#define DRM_IOCTL_S3V_SIMPLE_UNLOCK 	DRM_IO(  0x6c)
+#define DRM_IOCTL_S3V_RESET     	DRM_IO(  0x61)
+#define DRM_IOCTL_S3V_STATUS        	DRM_IO(  0x62)
+/*
+#define DRM_IOCTL_S3V_COPY      		DRM_IOW( 0x6d, drm_s3v_copy_t)
+*/
 #endif
diff --git a/shared/drm.h b/shared/drm.h
index d116f375..1ad21860 100644
--- a/shared/drm.h
+++ b/shared/drm.h
@@ -99,6 +99,19 @@ typedef struct drm_tex_region {
 	unsigned int	age;
 } drm_tex_region_t;
 
+/* Seperate include files for the i810/mga/r128 specific structures */
+#include "mga_drm.h"
+#include "i810_drm.h"
+#include "r128_drm.h"
+#include "radeon_drm.h"
+#include "sis_drm.h"
+/* #include "i830_drm.h" */
+#include "gamma_drm.h"
+#include "s3v_drm.h"
+#ifdef CONFIG_DRM_SIS
+#include "sis_drm.h"
+#endif
+
 typedef struct drm_version {
 	int    version_major;	  /* Major version			    */
 	int    version_minor;	  /* Minor version			    */
@@ -419,8 +432,104 @@ typedef struct drm_scatter_gather {
 #define DRM_IOCTL_SG_ALLOC		DRM_IOW( 0x38, drm_scatter_gather_t)
 #define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, drm_scatter_gather_t)
 
-/* Device specfic ioctls should only be in their respective headers
- * The device specific ioctl range is 0x40 to 0x79.                  */
-#define DRM_COMMAND_BASE                0x40
+/* MGA specific ioctls */
+#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
+#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x41, drm_lock_t)
+#define DRM_IOCTL_MGA_RESET		DRM_IO(  0x42)
+#define DRM_IOCTL_MGA_SWAP		DRM_IO(  0x43)
+#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x44, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x45, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x47, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x48, drm_mga_blit_t)
+
+/* i810 specific ioctls */
+#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)
+#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)
+#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)
+#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)
+#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)
+#define DRM_IOCTL_I810_OV0INFO		DRM_IOR( 0x49, drm_i810_overlay_t)
+#define DRM_IOCTL_I810_FSTATUS		DRM_IO ( 0x4a)
+#define DRM_IOCTL_I810_OV0FLIP		DRM_IO ( 0x4b)
+#define DRM_IOCTL_I810_MC		DRM_IOW( 0x4c, drm_i810_mc_t)
+#define DRM_IOCTL_I810_RSTATUS		DRM_IO ( 0x4d )
+
+
+/* Rage 128 specific ioctls */
+#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)
+#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)
+#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)
+#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)
+#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_INDIRECT		DRM_IOWR(0x4f, drm_r128_indirect_t)
+#define DRM_IOCTL_R128_FULLSCREEN	DRM_IOW( 0x50, drm_r128_fullscreen_t)
+#define DRM_IOCTL_R128_CLEAR2		DRM_IOW( 0x51, drm_r128_clear2_t)
+
+/* Radeon specific ioctls */
+#define DRM_IOCTL_RADEON_CP_INIT	DRM_IOW( 0x40, drm_radeon_init_t)
+#define DRM_IOCTL_RADEON_CP_START	DRM_IO(  0x41)
+#define DRM_IOCTL_RADEON_CP_STOP	DRM_IOW( 0x42, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET	DRM_IO(  0x43)
+#define DRM_IOCTL_RADEON_CP_IDLE	DRM_IO(  0x44)
+#define DRM_IOCTL_RADEON_RESET		DRM_IO(  0x45)
+#define DRM_IOCTL_RADEON_FULLSCREEN	DRM_IOW( 0x46, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP		DRM_IO(  0x47)
+#define DRM_IOCTL_RADEON_CLEAR		DRM_IOW( 0x48, drm_radeon_clear_t)
+#define DRM_IOCTL_RADEON_VERTEX		DRM_IOW( 0x49, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES	DRM_IOW( 0x4a, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_STIPPLE	DRM_IOW( 0x4c, drm_radeon_stipple_t)
+#define DRM_IOCTL_RADEON_INDIRECT	DRM_IOWR(0x4d, drm_radeon_indirect_t)
+#define DRM_IOCTL_RADEON_TEXTURE	DRM_IOWR(0x4e, drm_radeon_texture_t)
+#define DRM_IOCTL_RADEON_VERTEX2	DRM_IOW( 0x4f, drm_radeon_vertex_t)
+
+/* Gamma specific ioctls */
+#define DRM_IOCTL_GAMMA_INIT		DRM_IOW( 0x40, drm_gamma_init_t)
+#define DRM_IOCTL_GAMMA_COPY		DRM_IOW( 0x41, drm_gamma_copy_t)
+
+/* SiS specific ioctls */
+#define SIS_IOCTL_FB_ALLOC		DRM_IOWR(0x44, drm_sis_mem_t)
+#define SIS_IOCTL_FB_FREE		DRM_IOW( 0x45, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_INIT		DRM_IOWR(0x53, drm_sis_agp_t)
+#define SIS_IOCTL_AGP_ALLOC		DRM_IOWR(0x54, drm_sis_mem_t)
+#define SIS_IOCTL_AGP_FREE		DRM_IOW( 0x55, drm_sis_mem_t)
+#define SIS_IOCTL_FLIP			DRM_IOW( 0x48, drm_sis_flip_t)
+#define SIS_IOCTL_FLIP_INIT		DRM_IO(  0x49)
+#define SIS_IOCTL_FLIP_FINAL		DRM_IO(  0x50)
+
+/* I830 specific ioctls */
+#if 0
+#define DRM_IOCTL_I830_INIT		DRM_IOW( 0x40, drm_i830_init_t)
+#define DRM_IOCTL_I830_VERTEX		DRM_IOW( 0x41, drm_i830_vertex_t)
+#define DRM_IOCTL_I830_CLEAR		DRM_IOW( 0x42, drm_i830_clear_t)
+#define DRM_IOCTL_I830_FLUSH		DRM_IO ( 0x43)
+#define DRM_IOCTL_I830_GETAGE		DRM_IO ( 0x44)
+#define DRM_IOCTL_I830_GETBUF		DRM_IOWR(0x45, drm_i830_dma_t)
+#define DRM_IOCTL_I830_SWAP		DRM_IO ( 0x46)
+#define DRM_IOCTL_I830_COPY		DRM_IOW( 0x47, drm_i830_copy_t)
+#define DRM_IOCTL_I830_DOCOPY		DRM_IO ( 0x48)
+#endif
 
+/* s3v specific ioctls */
+#define DRM_IOCTL_S3V_INIT      	DRM_IOW( 0x60, drm_s3v_init_t)
+#define DRM_IOCTL_S3V_SIMPLE_LOCK   	DRM_IO(  0x6a)
+#define DRM_IOCTL_S3V_SIMPLE_FLUSH_LOCK DRM_IO(  0x6b)
+#define DRM_IOCTL_S3V_SIMPLE_UNLOCK 	DRM_IO(  0x6c)
+#define DRM_IOCTL_S3V_RESET     	DRM_IO(  0x61)
+#define DRM_IOCTL_S3V_STATUS        	DRM_IO(  0x62)
+/*
+#define DRM_IOCTL_S3V_COPY      		DRM_IOW( 0x6d, drm_s3v_copy_t)
+*/
 #endif