path: root/xc/programs/Xserver/hw/xfree86/doc/sgml/agx.sgml

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<title>Notes on the AGX Server
<author>Henry Worth
<date>24 June 1995

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<toc>

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<sect>General Notes<p>

     This server currently supports the IIT AGX-016, AGX-015, AGX-014
     and XGA-2 chipsets. The AGX chipset is based on XGA architecture, 
     but is missing several features and differs on others. There's 
     also untested support for the XGA-1 and AGX-010 chipsets.    
     Pixel depths of 8bpp, 15bpp, 16bpp are generally supported.
     Unpacked 24bpp (RGBX 32bpp) is not yet stable enough to release.
<p>
     RAMDACs currently supported are the Brooktree (BT481, BT482,
     and BT485) and AT&amp;T (20C505) RAMDACs used by the Hercules 
     Graphite series, and Sierra RAMDACs (15025 and 15021), and
     Generic VGA RAMDAC. Untested support has been added for the
     AT&amp;T 20C490 series.
<p>  
     The current driver has a number of acceleration routines:
     solid and dashed zero-width lines (except AGX-014), bitblt
     fills, tiles, and stipples, solid arc and polygon fills, 
     character glyphs and font cache for 8-bit characters.
<p>
     Boards that have had some testing include ISA and VLB 
     versions of most of the Hercules Graphite series, Spider 
     Black Widow VLB and Black Widow Plus VLB, Boca Vortek VL,
     CatsEye/X XGA-2, and the PS/2-57 planar XGA-2. The Orchid
     Celsius is very similar to the Spider and Boca boards, except 
     some batches may use one of the AT&amp;T 20C490 series RAMDACs, 
     instead of the Sierra 15025. There has also been a report of
     a generic board that uses a UMC RAMDAC that may be an AT&amp;T 
     20C490 Clone. 

<sect> Acknowledgments
<p>
     First, to Hercules Customer Support for providing a loaner 
     board to get things started.
<p>
     Second, to the XFree86 team, and those who who have contributed
     to their efforts to the project, for the foundation of work that 
     provided a basis for bootstrapping this server.

<sect> Known Problems
<p>
<itemize>
<item>The accelerated line routines don't match lines written
        by the mi/cfb routines. This is noticeable when switching 
        between virtual consoles while running routines that draw 
        and erase lines. Seems to have been reduced/fixed in previous
        releases but need more testing.<p>

<item>Some special-case speedup added to cached font rendering
        in 3.1.1 has been disabled as is over-aggressive in some
        cases. This cuts the performance on terminal-fonts in half,
        and font performance is already low for the AGX chips compared
        to their contemporaries.<p>

<item>As in all software, needs more testing.<p>

</itemize>
<sect> ToDo
<p>
 <itemize>
<item>Address the above known problems.<p>

<item>Additional acceleration routines and general performance 
        improvements. Many existing acceleration routines are Q&amp;D 
        adaptations of existing routines from other servers that support
        graphics chips that differ significantly, architecturally, from
        that XGA and are undoubtedly less than optimal. In particular
        some of the general per-operation overhead to set-up the
        graphics context should be moved to the ValidateGC() routines.<p>

<item>Complete HW cursor support, most of the code is done (or
        borrowed from other servers). There just remains a little
        setup code and then finding a lot of time to debug and test
        the numerous permutations.<p>

<item>Complete support for the Graphite Pro's 84-pin RAMDAC.
        (the 2MB version of the Graphite Pro has both RAMDACs, 
        the 1Mb only the 44-pin RAMDAC). Currently, the 84-pin RAMDAC 
        is only supported in clock-doubled pixmux mode, the server
        will switch between RAMDACs as required by the video mode
        In >8bpp modes this switching does not occur. <p>

<item>Implement more HW probing, this will be difficult as it
        appears some (all?) AGX-based vendors don't implement 
        the VESA VXE POS registers, although the AGX chip does 
        support it (and some vendors claim VXE compliance&hellip). 
        There are a few rev/vendor registers in the AGX chip but 
        they are not documented. Note: SuperProbe also does not 
        support probing for AGX/XGA chips. ISA POS probing is
        supported for the XGA chips and some code for EISA POS 
        is also included but not tested.<p>

<item>Micro-optimizations, in particularly reducing processing overhead 
        for common special cases that don't require full generality. <p>
</itemize>
<sect> XF86Config
<p>    
Device Section Entries and Options Currently Supported:

<p>
    The minimum that must be specified in the XF86Config device
    section for the AGX-014, AGX-015, AGX-016, and ISA-based XGA-1 
    and XGA-2 is the Chipset. However to get full capability out
    of the AGX-01&lsqb;456&rsqb; chips, the RAMDAC should be specified.
    Other parms may select additional capabilities, or may used to
    override the defaults or reduce start-up time be suppressing
    probing. XGA specific configuration is covered at the end of
    this document. The XGA entries can generally be used to override
    defaults for the AGX-01&lsqb;456&rsqb; as well.

<descrip>
<tag/Ramdac/

           Be sure to check the clock rating of the RAMDAC(s) on
           your video board and don't exceed that rating even
           if the server allows it, overclocking RAMDACs will
           damage them. 
<p>
           The clock rating generally appears as a suffix to the part 
           number, may only have the most significant digit(s),
           and may be mixed with other codes (e.g. package
           type). For example, an 85MHz Bt481 in a plastic J-lead
           package has a part number of Bt481KPJ85 and a 135MHz 
           AT&amp;T20C505 has a part number of ATT20C505-13. Sierra
           stamps the rated speed below the part numbers in a
           dark ink.

<descrip>
<tag/&dquot;normal&dquot;/          
				 normal VGA style RAMDAC (6-bit DAC),
                                 default if none specified. Most
                                 boards should work with this parm,
                                 but some capabilities will be 
                                 unavailable. Only 8bpp is available.

<tag/&dquot;bt481&dquot;/             
				 bt481 RAMDAC (supports 8-bit DAC)
<tag/&dquot;bt482&dquot;/             
				 bt482 RAMDAC (supports 8-bit DAC)
                                 The Hercules Graphite HG210 uses 
                                 the BT481 or BT482, the only 
                                 difference between these two is the
                                 BT482's HW cursor (not yet supported).
                                 The BT481/2 are limited to 85Mhz.
                                 8bpp, 15bpp, 16bpp are supported. 

<tag/&dquot;ATT20c490&dquot;/
                                 AT&amp;T490 RAMDAC (includes
                                 49&lsqb;123&rsqb;  
                                 - supports 8-bit DAC). Limited
                                 to 110Mhz at 8bpp. 8bpp, 15bpp, 
                                 and 16bpp are supported.

<tag/&dquot;SC15025&dquot;/          
				 Sierra SC15025 and SC15021 RAMDAC
                                 (support 8-bit DAC). The SC15025 is
                                 limited to 125Mhz, and the SC15021
                                 135Mhz. Check the RAMDAC's actual rating,
                                 some SC15025's used in AGX based boards
                                 are only rated to 110Mhz. 8bpp, 15bpp,
                                 and 16bpp are supported. 
 
<tag/&dquot;herc_dual_dac&dquot;/     
				 Hercules Graphite Pro RAMDAC probe.
                                 If the 84-pin Big-RAMDAC is installed
                                 (2MB models), will use the Big RAMDAC,
                                 but only clocks-doubled, pixel-
                                 multiplexed modes (higher clock values
                                 only!). Lower clocks and resolutions 
                                 in 8bpp mode are supported by switching 
                                 to the Small 44-pin RAMDAC. 15bpp and
                                 16bpp are supported.
<p>
                                 There has been one report of the 
                                 "dac-8-bit" option not working with a
                                 Graphite Pro equipped with a BT485 RAMDAC, 
                                 puzzling since it should be identical to the
                                 AT&amp;T20C505 in this regard. No startup 
                                 messages or XF86Config were submitted to
                                 aid problem isolation.
<p>
                                 Not supported by the HG210 Graphite.

<tag/&dquot;herc_small_dac&dquot;/    
				 Hercules Graphite Pro RAMDAC probe.
                                 Forces use of only the BT481/482
                                 RAMDAC. 8bpp, 15bpp, 16bpp, and unpacked
                                 24/32bpp are supported.

                                 Not supported by the HG210 Graphite.

<tag/&dquot;xga&dquot;/
                                 To allow overriding the default
                                 VGA style RAMDAC control for the AGX-010. 
</descrip> 

<tag/Ramdac related Option Flags:/

<descrip>
<tag/&dquot;dac_6_bit&dquot;/   
				 Sets RAMDAC to VGA default 6-bit DAC mode
                                 (default for "normal").

<tag/&dquot;dac_8_bit&dquot;/   
				 Sets supported RAMDAC's to 8-bit DAC mode
                                 (default for all but "normal").

<tag/&dquot;sync_on_green&dquot;/ 
				 Composite sync on green for RAMDAC's that 
                                 support this feature (BT481/481 and 
                                 AT&amp;T20c490). However, whether any 
                                 boards have necessary traces and glue 
                                 logic is doubtful. 
</descrip> 
      
<tag/Chipset:/

           Must be specified, possible values: "AGX-016", "AGX-015",
           "AGX-014", "AGX-010", "XGA-2", or "XGA-1". Some AGX
           vendors place stickers over the chip, in general, if it's 
           a VLB board it's probably an AGX-015 and if it's an ISA 
           board it may be an AGX-014. The Hercules Graphite Power Pro 
           and Spider Black Widow Plus use the AGX-016 chipset. In general, 
           specifying a lower revision in the AGX-0{14,15,16} series
           does not seem to causes problems (except lower performance
           from the AGX-014's non-accelerated line drawing). 
<p>
           <bf>Note:</bf> Only the AGX-016, AGX-015, AGX-014 and XGA-2
           have had any testing. Most of the development has been with
           an AGX-015 based 2MB Hercules Graphite VL PRO (HG720) and
           most of testers for previous releases had AGX-014 based 1MB 
           Hercules Graphite (HG210).
<p>
           The limited documentation I have for the AGX-010 is that 
           is is a clone of the XGA architecture with a few additional 
           configuration registers. What is not clear is whether to 
           use XGA or extended-VGA RAMDAC control registers. 
           The post-3.1.1 default is now VGA control registers, but 
           XGA control registers can be forced with the XGA RAMDAC parm. 
           Likewise the configuration parms described in the XGA 
           section can be used to override the AGX defaults for I/O 
           and memory addresses. 
           
<tag/VideoRam:/

           Will be probed if not specified. The startup will be a 
           little faster if specified. 

<tag/Tuning Option flags:/

<descrip>
<tag>Bus I/O interface:</tag>

<descrip>
<tag/&dquot;8_bit_bus&dquot;/      Force 8-bit I/O bus.
<tag/&dquot;wait_state&dquot;, &dquot;no_wait_state&dquot;/     
Set or clear CPU access wait state, default is the POST setting.
<tag/&dquot;fifo_conserv&dquot;/    Disable Memory I/O Buffer, AGX-015 and AGX-016. 
                               MS-Windows driver default. Required by some
                               VLB systems with `aggressive timing'. 
			       The default for this server is to disable 
                               the buffer.

<tag/&dquot;fifo_moderate&dquot;/   Enable the AGX-015/016's Memory I/O buffer.
<tag/&dquot;fifo_aggressive&dquot;/ Enable the AGX-016's extra-large buffer.
                               Either option may result in garbage being left 
                               about the screen, disabled by default. 
                               A good test is the xbench or x11perf dashed 
                               lines tests, if random dots are drawn, 
                               fifo_conserv is required. So far, no boards 
                               have been reported that worked correctly 
                               with the buffers enabled.
</descrip>
<tag/Memory Timing:/

           POST defaults should be ok.

<descrip>
<tag/&dquot;vram_delay_latch&dquot;, 
     &dquot;vram delay_ras&dquot;, 
     &dquot;vram_extend_ras&dquot;/  Vram timing options.
         
<tag/&dquot;slow_vram&dquot;, 
     &dquot;slow_dram&dquot;/       Set all of the vram timing options.
<tag/&dquot;med_dram&dquot;/        Set vram latch delay, clear others.
<tag/&dquot;fast_vram&dquot;,
     &dquot;fast_dram&dquot;/       All of the vram timing options are cleared.  
                               Should be specified if directly specifying
                               VRAM options in order to clear POST settings. 
</descrip>

<tag/Debugging:/

           These shouldn't generally be required:
     
<descrip>
<tag/&dquot;noaccel&dquot;/    (AGX,XGA) Disable Font Cache.          
                               
<tag/&dquot;crtc_delay&dquot;/    (AGX) Force XGA mode CRTC delay.
                               
<tag/&dquot;engine_delay&dquot;/    AGX-015 only? adds additional VLB wait state.
<tag/&dquot;vram_128&dquot;, &dquot;vram_256&dquot;/        Sets VRAM shift frequency, vram_128 is for
                     128Kx8 VRAM. Default is to leave this bit
                               unchanged from POST setting.
<tag/&dquot;refresh_20&dquot;, &dquot;refresh_25&dquot;/     Number of clock cycles between screen 
                 refreshes. Default is to leave this bit
                               unchanged from POST setting.
<tag/&dquot;screen_refresh&dquot;/  Disable screen refresh during non-blanked
                               intervals, AGX-016. Default is leave them
                               enabled.
<tag/&dquot;vlb_a&dquot;, &dquot;vlb_b&dquot;/         VLB transaction type, default is to leave
                        this bit unchanged from POST value.

</descrip>
</descrip>
</descrip>
<descrip>
<tag/Virtual resolution:/

           The server now accepts any virtual width, however the
           actual usable CRTC line width is restricted when using the
           graphics engine and depends upon the chip revision. The
           CRTC line width and not the virtual width determine the 
           amount of memory used. The server currently does not make
           use of any of the unused CRTC line's memory. CRTC line 
           width is restricted by the following rules:
<p><quote>
               <bf>AGX-014 :</bf> 512, 1024 and 2048. (also AGX-010)
</quote><quote>
               <bf>AGX-015 :</bf> 512, 1024, 1280, and 2048. 
</quote><quote>
               <bf>AGX-016 :</bf> 512, 640, 800, 1024, 1280, and 2048.
</quote><quote>
               <bf>XGA,AGX-010 :</bf> 512, 640, 800, 1024, 1280, 1152, and 2048.
</quote>

<p>
           When panning I occasionally get streaks if the virtual 
           resolution is much greater than the physical resolution. 
           Moving the mouse a little makes it disappear. The Hercules 
           manual indicates this also happens with the MS-Windows drivers.
<p>
           The server requires at least a 64KB scratchpad (16KB for XGA's).
           Additional memory is useful for font cache and a larger scratchpad.
          


<tag/AGX Clocks:/

          Probing is supported, but of course the usual warnings and
          disclaimers apply. Probing may momentarily subject your
          monitor to sweep frequencies in excess of its rating.
          The cautious may wish to turn off the monitor while the 
          probe is running.
<p>
          Once clocks are known, they can be entered into XF86Config,
          then subsequent runs won't probe clocks and will be quicker
          to startup. For the clock probe it is recommended that the 
          X server be run with the -probeonly option. The values 
          in the clocks statement are the hardware input clocks and
          correspond to the pixel clock only at 8bpp in direct-clocking 
          RAMDAC modes. The server will divide/multiply those values 
          as appropriate for the RAMDAC modes available at the current 
          pixel depth. The available pixel clocks will be displayed
          in the startup messages.
<p>
          For the 2MB Hercules Graphites, with the "herc-dual-dac"
          RAMDAC specified, earlier versions of the server generated
          an additional 16 clocks with values doubled and some zeroed.
          Those are no longer needed and you should re-probe and re-enter 
          the clock values to ensure all clocks are available to you.
            
            The AGX-015 2MB Hercules Graphite VL Pro with an 
            ICS1494M 9251-516 clock chip has probed clock values of:
<verb>
               25.18  28.80  32.70  36.00  40.00  45.00  50.40  64.70
               70.10  76.10  80.60  86.30  90.40  95.90 100.70 109.40
</verb>
            Actual values according to Hercules are:
<verb>
               25.175 28.322 32.512 36.000 40.00 44.90 50.35 65.00
               70.00  75.00  80.00  85.00  90.00 95.00 100.0 108.0
</verb>
            These are the values to be used in the clock statement
            if specifying the "normal", "bt481", or "herc_small_dac"
            RAMDAC in your XF86Config and your clockchip matches
            that above. 
<p>
          Clock probing assumes that the first clock is 25.175Mhz and
          uses that to derive the rest. A warning is displayed if the
          second is not near 28.322Mhz. If this warning appears, you
          should not use the probed clock values without additional
          verification from other sources.
<p>
          In the case of the AGX-014 and later AGX's, only the external 
          clock select lines are used, this means the clock values
          correspond to the values of the video board's clock chip.
<p>
          For the AGX-010, the first 8 clocks use the standard XGA 
          internal clock selects and the second 8 are based on  
          AGX extensions. For the XGA-1 only 8 clocks are available.
          The XGA-2 uses a programmable clock and no clocks or 
          clockchip line is required.
<p>
          The maximum pixel clock generally allowed is 85MHz, but
          some RAMDACs support higher values. In any case you, should
          check your RAMDAC, some RAMDACs used on AGX based boards are 
          produced in versions rated to lesser values than the server
          assumes. You should check the rating and limit yourself to 
          that value. 

<tag/Modes:/

          One difference I've noted from the Mach8, is that the AGX's
          CRTC doesn't like the start of the horizontal sync to be 
          equal to horiz blank start (vert sync may have the same problem, 
          I need to test some more). Interlaced and +/-sync flags are
          supported but have had very little testing. For interlaced
          modes make sure the number of lines is an odd number.
<p>
          The doublescan flag is now supported, however the minimum
          clock supported is generally 25MHz, so resolutions of less
          than 400x300 are not likely to be supported by most monitors.
          In creating doublescan mode timings, the vertical timings
          will match the apparent resolutions, e.g. for 400x300
          the timings should describe 300 lines, not 600.
  
<tag/Examples:/

<p>          For the Hercules HG720 (2MB VLB AGX-015, with BT481 and 
          AT&amp;T20C5050 RAMDACs), I use the following XF86Config 
          "Device" section:
<verb>
             Section "Device"
                 Identifier "HG720"
                 VendorName "Hercules"
                 BoardName  "Graphite VL Pro"
                 Chipset    "AGX-015"
                 Clocks     25.2  28.3  32.5  36.0  40.0  45.0  50.4  65.0
                            70.00  75.00  80.00  85.00  90.00 95.00 100.0 108.0
                 Videoram   2048
                 RamDac     "herc_dual_dac"
                 Option     "dac_8_bit"
                 Option     "no_wait_state"
             EndSection
</verb>
          For the Spider Black Widow Plus (2MB VLB AGX-016, with
          Sierra SC15021 RAMDAC): 
<verb>
             Section "Device"
                 Identifier "SBWP"
                 VendorName "Spider"
                 BoardName  "Black Widow Plus"
                 Chipset    "AGX-016"
                 Clocks      25.2  28.3  39.9  72.2  50.0  76.9  36.1  44.8
                             89.0  119.8 79.9  31.5 110.0  64.9  74.9  94.9
                 Videoram   2048
                 RamDac     "SC15025"
                 Option     "dac_8_bit"
                 Option     "no_wait_state"
             EndSection
</verb>
</descrip>
<sect> Xga configuration<p>


<p>          This server now has tested support for XGA-2 compatible 
          boards (aka. XGA-NI). The main issue for XGA-1 support is 
          whether clock probing works. At this time probing for board 
          configuration is limited and detailed configuration may need to be 
          done manually. 

<p>       By default the ISA POS register will be performed. If the
          XGA Instance number is specified the scope of probing will
          be narrowed a bit. To override or disable probing, a minimum
          of the Instance, COPbase, and MEMbase must be specified
          in the XF86Config device section for the XGA card. MCA 
          probing is not supported.

<p>
<descrip>            
<tag/Instance       nn/       XGA instance number (0-7).

<tag/IObase        nnnn/      The I/O address of the the XGA
                                      general control registers. The
                                      standard, and default, is 0x21i0,
                                      where i is the instance number.

<tag/MEMbase        nnnn/      The XGA display memory address (the
                                      address the XGA coprocessor uses
                                      for video memory). This is also  
                                      the system memory address of the
                                      linear aperture on boards that
                                      support it.

                                      POS register 4 bits 7-1 contains
                                      bits 31-25 of the XGA's display
                                      memory address. Bits 24-22 of
                                      of the display memory address
                                      contains the XGA instance number.
                                      Bit 0 of POS register 4 is not
                                      used by this server as the XGA's
                                      linear aperture is not used.
                                      However, the coprocessor must 
                                      still be configured with this.

                                      The AGX-01&lsqb;456&rsqb;
                                      chips have a fixed 
                                      display memory address.

<tag/COPbase     nnnnnn/      Address of the graphics engine's
                                      memory mapped control registers.

                                      Typically: 

                                      0xC1C00 + (ext_mem_addr * 0x2000)
                                        + (instance * 0x80)

                                      where ext_mem_addr is the high
                                      order 4-bits of POS register 2
                                      (0-16 the server assumes zero).

                                      The AGX-01&lsqb;456&rsqb; chips support 
                                      0xB1F00 (default) and 0xD1F00.

<tag/BIOSbase     nnnnnn/      Address of the XGA BIOS (not VGA BIOS).
                                     Can be specified as an alternate to COPbase.

                                      Typically: 

                                      0xC0000 + (ext_mem_addr * 0x2000)

                                      where ext_mem_addr is the high
                                      order 4-bits of POS register 2
                                      (0-16 -- the server assumes zero).

<tag/VGAbase        nnnn/      Can be used to override the default 0xA0000 
                                      address for the 64KB video memory
                                      address used by the server. The
                                      only values acceptable are 0xA0000
                                      and 0xB0000. VGA text mode restore
                                      does not work under Linux if 0xB0000
                                      is specified. 

                                      AGX-01&lsqb;456&rsqb;
                                      also default to 0xA0000.

<tag/POSbase       nnnn/      Can be used to specify an alternate POS register
                                      probe address base from the ISA  
                                      default of 0x100. The VESA VXE
                                      standard for EISA is 0xzC80, where 
                                      z is the slot number).

                                      A value of zero will disable POS 
                                      register probing (required for MCA). 
  
<tag/DACspeed      nnnn/      Can be used to override the servers default
                                      maximum Pixel Clock for XGA-2 of 80Mhz. 
                                      The limit can be raised as high as 90Mhz,
                                      or set to lower values.

</descrip>
<p>        An alternate way to determine the POS register values is
           with the setup/diag programs that should have been included
           with your video board, or possibly from jumper values.
<p>          
           The XGA-2 has programmable clocks up to 90MHz, however
           at 1024x768, 72MHz is generally the max that will produce
           a stable display with the CatsEye/XGA-2 used for testing
           (IBM coprocessor and INMOS RAMDAC/serializer). Higher clocks 
           will often generate artifacts at the top and left edges of 
           the screen. Such artifacts can sometimes be tuned out by
           increasing the vertical and horizontal blanking intervals
           or slightly changing the clock. At pixel clock rates above 
           80Mhz I have seen the chip lose sync after running for several
           minutes, so 80Mhz has been set as the default limit for XGA-2
           pixel clocks. I don't have specs on actual limits, and as 
           there are a number of different XGA chipsets, you should use 
           the modes documented in your owner's manual as a guide to 
           max refresh rates. No clocks or clockchip parm are required 
           to specify use of programmable clocks for the XGA-2. 
<p>
           8bpp and 16bpp are supported for the XGA-2.
<p>
           For XGA-1 cards the clocks must be specified as for
           the AGX chips, it is not known whether the clockprobing
           will work. Some XGA-1 chips may support 16bpp. 
<p>

<verb>
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