summaryrefslogtreecommitdiff
path: root/xc/lib/GL/mesa/src/drv/i810/i810dma.c
blob: f745d272f79553209beb7285d7accbb9733ac446 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
/* -*- mode: C; c-basic-offset:8 -*- */
/*
 * GLX Hardware Device Driver for Intel i810
 * Copyright (C) 1999 Keith Whitwell
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 
 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * based on the original mgadma.c by Jeff Hartmann <slicer@ionet.net>
 * as rewritten by John Carmack <johnc@idsoftware.com>
 */

#include <stdlib.h>
#include <errno.h>
#include <unistd.h>
#include <sys/mman.h>
#include <stdio.h>
#include <sys/time.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <signal.h>

#include "mm.h"
#include "i810buf.h"
#include "i810dd.h"
#include "i810lib.h"
#include "i810log.h"
#include "i810tris.h"
#include "i810direct.h"
#include "i810state.h"

#include "pb.h"

/* X server include:
 */
#include "i810.h"



/* This will be overwritten from the default values when glx.so is
 * loaded on the client.
 */
void i810ServerDmaFlush( int wait );
GLuint i810ActiveDmaBuffer = 0;	



#ifndef I810_DEBUG
int I810_DEBUG = (0
/*     		  | DEBUG_ALWAYS_SYNC  */
/*    		  | DEBUG_VERBOSE_ACCEL  */
/*  		  | DEBUG_VERBOSE_SYNC */
/*  		  | DEBUG_VERBOSE_VGA */
/*  		  | DEBUG_VERBOSE_RING    */
/*  		  | DEBUG_VERBOSE_OUTREG  */
/*  		  | DEBUG_VERBOSE_MEMORY */
/*  		  | DEBUG_ALWAYS_SYNC */
/*  		  | DEBUG_VERBOSE_MSG */
		  );
#endif



static void delay( void ) {
}



int i810WaitForDmaCompletion( void ) 
{
	int start, end;

	if (I810LpRing.head == I810LpRing.tail && I810LpRing.space) 
		return 0;

	start = i810_usec();
	I810LpRing.head = INREG(I810LpRing.base_reg + RING_HEAD);
	end = i810_usec();

	if (0 && start + 100 < end)
		fprintf(stderr, "INREG in WaitForDma: %d usec\n", end - start);

	I810LpRing.head &= HEAD_ADDR;
	I810LpRing.space = I810LpRing.head - (I810LpRing.tail + 8);
	if (I810LpRing.space < 0) 
		I810LpRing.space += I810LpRing.mem.Size;

	if (I810LpRing.head == I810LpRing.tail) 
		return 0;

	start = i810_usec();
  	I810Sync(); 
	end = i810_usec();

	return 1;
}



/*
 * i810DmaResetBuffer
 */
void i810DmaResetBuffer( void ) {

	i810glx.dma_buffer = dmaBuffers[ i810ActiveDmaBuffer ];
	i810glx.dma_buffer->head = 0;
	i810glx.dma_buffer->space = 0;
	i810glx.dma_buffer->additional_space = 
		i810glx.dma_buffer->mem.Size - 256;
	
	i810DmaOverflow( 0 );

	if (i810glx.dma_buffer_age < i810glx.dma_buffer->texture_age) 
		i810glx.dma_buffer_age = i810glx.dma_buffer->texture_age; 
}




/*
 * i810FlushRealDma
 */
void i810FlushRealDma( void ) {

	GLuint start;

	if (MESA_VERBOSE&VERBOSE_DRIVER)
		fprintf(stderr, "i810FlushRealDma()\n" );


	if ( i810glx.skipDma || !I810_USE_BATCH )
		return;
	

	if (i810glx.dma_buffer->head & 0x4) {
		FatalError( "Misaligned batch buffer\n" );
	}

	if ( (I810_DEBUG&DEBUG_VERBOSE_OUTREG) && 0)
	{
		int i;
		for (i = 0 ; i <= i810glx.dma_buffer->head ; i+=4) 
			fprintf(stderr, 
				" 0x%05x : 0x%08x\n", 
				i/4, 
				*(GLuint *)(i810glx.dma_buffer->virtual_start +
					    i));
	}


	/* fire the batch buffer */       
	for (start = 0 ; start < i810glx.dma_buffer->head ; start += MAX_BATCH)
	{
		GLuint ofs = i810glx.dma_buffer->mem.Start;
		GLuint end = MIN2(start + MAX_BATCH, i810glx.dma_buffer->head);
		
		BEGIN_LP_RING(4);
		OUT_RING( CMD_OP_BATCH_BUFFER );
		OUT_RING( (ofs + start) | BB1_PROTECTED );
		OUT_RING( (ofs + end) - 4 );
		OUT_RING( 0 );
		ADVANCE_LP_RING();
	}

	{
		BEGIN_LP_RING(2);
		OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | 
			  INST_FLUSH_MAP_CACHE );
		OUT_RING( 0 );
	}
}

/*
 * i810DmaFlush
 * Send all pending commands off to the hardware.
 * If we are running async, the hardware will be drawing
 * while we return to do other things.
 */
void i810ServerDmaFlush( int wait ) {
	int		start, end;

	if (I810_DEBUG)
		fprintf(stderr, 
			"i810ServerDmaFlush, buffer %d, head %x space %x\n",
			i810ActiveDmaBuffer, 
			i810glx.dma_buffer->head,
			i810glx.dma_buffer->space);

	if ( i810glx.dma_buffer->head == 0 ) 
	{
		if (wait && !i810WaitForDmaCompletion())
			i810glx.hardwareWentIdle = 1;

		return;
	}

	i810glx.c_dmaFlush++;
	
	/* wait for the last buffer to complete */
	if ( !i810WaitForDmaCompletion() ) 
		i810glx.hardwareWentIdle = 1;
	

	/* collect timing information if we are going syncronously */
	if ( i810glx.dmaDriver != 3 ) {
 		start = i810_usec();
 	} else {
 		start = end = 0;
 	}
 	
	i810FlushRealDma();
 
	if ( i810glx.dmaDriver == 2 ) {
		/* wait until the dma completes */
		i810WaitForDmaCompletion();
	}

 	if ( i810glx.dmaDriver != 3 ) {
		end = i810_usec();
	}

	i810Msg(10, "flushmode %i, buffer %i: prim dwords:%i usec:%i\n", 
		i810glx.dmaDriver,  i810ActiveDmaBuffer,
		i810glx.dma_buffer->head / 4,
		end - start );	

	/* swap to using the other buffer */
	i810ActiveDmaBuffer ^= 1;
	i810DmaResetBuffer();
	
	if ( wait ) 
		i810WaitForDmaCompletion();
}


/*
 * i810DmaFlush
 */
void i810DmaFlush( void ) {
	i810FinishPrimitive();
	i810glx.dma_buffer->texture_age = ++i810glx.current_texture_age;

	if ( i810Ctx && i810Ctx->CurrentTex0Obj ) 
		i810Ctx->CurrentTex0Obj->age = ++i810glx.current_texture_age; 

	if ( i810Ctx && i810Ctx->CurrentTex1Obj ) 
		i810Ctx->CurrentTex1Obj->age = ++i810glx.current_texture_age; 
		
	i810ServerDmaFlush( 0 );
}


/*
 * i810DmaFinish
 */
void i810DmaFinish( void ) {
	i810FinishPrimitive();
	i810ServerDmaFlush( 1 );

	i810glx.dma_buffer_age = ++i810glx.current_texture_age;
  
	if ( i810Ctx && i810Ctx->CurrentTex0Obj ) 
		i810Ctx->CurrentTex0Obj->age = ++i810glx.current_texture_age; 

	if ( i810Ctx && i810Ctx->CurrentTex1Obj ) 
		i810Ctx->CurrentTex1Obj->age = ++i810glx.current_texture_age; 
}


/*
 * i810DmaOverflow
 * This is called when I810DMAGETPTR is at the end of the buffer
 */
void i810DmaOverflow( int newDwords ) {

	if (i810glx.dma_buffer->additional_space) {
		GLuint incr = MAX_BATCH;

		if (i810glx.dma_buffer->additional_space < incr) 
			incr = i810glx.dma_buffer->additional_space;

		while (i810glx.dma_buffer->head & (MAX_BATCH - 1)) {
			GLuint outbatch = i810glx.dma_buffer->head; 
			GLubyte *virt = i810glx.dma_buffer->virtual_start; 

			*(volatile unsigned int *)(virt + outbatch) = 0; 
			i810glx.dma_buffer->head += 4;
		}

		i810glx.dma_buffer->space += incr;
		i810glx.dma_buffer->additional_space -= incr;

		if (0)
		fprintf(stderr, "overflow, head %x space %x\n",
			i810glx.dma_buffer->head,
			i810glx.dma_buffer->space);
		return;
	}
	
	i810Msg( 9, "i810DmaOverflow(%i)\n", newDwords );

	/* flush all the current commands so we will have another
           empty buffer */
	i810DmaFlush();

	i810glx.c_overflows++;

	if ( newDwords > i810glx.dma_buffer->space ) 
 		FatalError("i810DmaOverflow > maxPrimaryDwords");
}


/*
 * i810WaitDrawingEngine
 * This will not return until the drawing engine has completed
 * drawing pixels and it is safe to read or write the framebuffer
 * for software rendering.
 */
int i810WaitDrawingEngine( void ) {
	/* note this for the performance block display */
	i810glx.c_drawWaits++;

	/* make sure all pending dma has completed */
	i810DmaFinish();
	return 0;
}


/*
 * i810DmaExecute
 * Add a block of data to the dma buffer
 */
void i810DmaExecute( GLuint *code, int dwords ) 
{	
	int i;
	BEGIN_BATCH(dwords);

	if (dwords & 1) 
		FatalError( "Misaligned buffer in i810DmaExecute\n" );

	for ( i = 0 ; i < dwords ; i++ )
		OUT_BATCH( code[i] );
	ADVANCE_BATCH();
}