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2004-07-10Patch by Mike A. Harris <mharris@redhat.com> for X.Org X11airlied2-24/+12
2004-06-22The depth buffer pitch must be a multiple of 32 pixels. Thanks to Steffendaenzer1-4/+9
2004-06-07Fix SiS DRI visual configs with guidance from idr:anholt1-9/+27
2004-06-04fix GARTSize optionsroland1-3/+6
2004-06-04Duplicate the changes made to src/mesa/drivers/dri/r128/server/r128_reg.hidr1-66/+29
2004-06-03Minor build fixes now that drm_sarea.h is used instead of sarea.h.idr1-1/+1
2004-06-02Remove the last remnants of drmClipRect.idr1-1/+1
2004-06-02Replace drmHandle, drmContext, drmDrawable, drmMagic and related types withidr28-122/+122
2004-06-01Replace all occurances of XF86DRIClipRect (and related typedefs) withidr14-48/+59
2004-05-28Build fixes.ajax2-0/+2
2004-05-18add R200_EMIT_RB3D_BLENDCOLOR packet (sync up to radeon_drm.h)sroland1-1/+2
2004-04-13Mark visuals with 16-bit depth buffer and (software simulated) stencilidr1-1/+1
2004-04-12Import mach64 into trunk - still insecure but don't build it by default..airlied23-8/+2968
2004-04-09Build fix.fxkuehl1-1/+1
2004-03-29- MergedFB and UseFBDev are not compatible. Disable MergedFB and warn theagd5f2-3/+13
2004-03-26- make savage4 use 2 as a cobIndex as well. Apparently only rev.A savage4s u...agd5f1-7/+3
2004-03-26- explicitly disable XvMC support on Savage3D based chips. I don't know ifagd5f1-0/+4
2004-03-26- Fix tile mode and enable it by default. It can still be disabled with theagd5f3-57/+12
2004-03-24- fix accel bug again. accidently reverted in my last change.agd5f1-0/+4
2004-03-23- re-enable AGPMode optionagd5f6-29/+76
2004-03-22fix AdjustFrame() for mobile savagesagd5f1-9/+5
2004-03-22- Update savage man page (add 2d/3d status and new options)agd5f2-11/+54
2004-03-22- Fix off by one bug in HW cursor location and cob alignment (Felix Kühling)agd5f1-67/+9
2004-03-20- Rework non-Xv streams codeagd5f4-98/+212
2004-03-12Fixes need to clean up the mess I made with the mesa merge. This codejonsmirl8-3/+5
2004-03-08add missing FOURCC_IA44 bits (needed for xvmc) to savage_video.c (Sarath Menon)agd5f1-0/+4
2004-03-04Adding missing XvMC initialization code. This may not fix XvMC on savage it ...agd5f1-0/+7
2004-03-02remove videodev2.h, savage_util.c/h. S3 remnants no longer neededagd5f3-1552/+0
2004-03-02- Add check to make sure there is enough ram for 3D with the mode/depthdriinterface-0-0-3-20040303-premergeagd5f4-71/+50
2004-02-27Make DPMS work for flatpanels when the BIOS is not setting modes.agd5f1-1/+31
2004-02-24remove un-needed/unused function declaration.agd5f1-1/+0
2004-02-24build fix for old gcc'salanh1-1/+2
2004-02-22Merged the DRI-enabled Savage 2D driver from the savage-2-0-0-branch into the...fxkuehl20-362/+7107
2004-02-07Missed IGP line in the radeon man page (Albert Astals Cid)agd5f1-1/+1
2004-02-04fix transparentPixel type to GLX_NONEalanh3-5/+5
2004-02-02make code more consistent with respect to agp alloc/bind failuresairlied1-9/+12
2004-01-27- Remove the 2048 limit code. using the DRI beyond 2048 has yet to cause anyagd5f3-49/+34
2004-01-11Fix vertical virtual desktops larger than 2048 in mergedfb mode.agd5f1-2/+2
2004-01-10Simplify test for R200 3D coredaenzer1-13/+7
2004-01-05Add support for Radeon IGP chipsets, based off of mcgrof-radeon-igp-v3.diffanholt3-18/+18
2003-12-30make InRegion() staticalanh2-3/+1
2003-12-30make InRegion staticalanh1-3/+1
2003-12-15Further fix for crtc2 mode problem. Only use default ranges if DDC info is n...agd5f1-3/+7
2003-12-14Fix crtc2 mode validation (seen as random/wrong hsync values for modes) due toagd5f2-9/+8
2003-12-09merge newmesa branch to the trunknewmesa-0-0-1-20031209-mergealanh1-1/+1
2003-12-03Added comments / defines from Radeon kernel header. At some point theidr1-7/+17
2003-11-10Revert changes accidentally included in last commit...daenzer2-40/+14
2003-11-10Try flipping back to the front page if necessary in DRITransitionTo2d()daenzer4-17/+59
2003-11-04Remove Option "ForcePCIMode" (deprecated by Option "BusType"; see XFree86daenzer2-14/+2
2003-11-04If RADEONDRIFinishScreenInit() fails, use MMIO XAA functions (instead ofdaenzer3-5/+10
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