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-rw-r--r--xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h1334
-rw-r--r--xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h31
-rw-r--r--xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c284
-rw-r--r--xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h92
4 files changed, 1085 insertions, 656 deletions
diff --git a/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h b/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h
index 084bfc7dd..c6e6c889a 100644
--- a/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h
+++ b/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h,v 1.39 1999/08/29 12:42:55 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h,v 1.51 2000/02/24 20:39:14 dawes Exp $ */
/*
* PCI Probe
*
@@ -169,17 +169,36 @@
#define PCI_CHIP_MACH64GB 0x4742
#define PCI_CHIP_MACH64GD 0x4744
#define PCI_CHIP_MACH64GI 0x4749
+#define PCI_CHIP_MACH64GL 0x474C
+#define PCI_CHIP_MACH64GM 0x474D
+#define PCI_CHIP_MACH64GN 0x474E
+#define PCI_CHIP_MACH64GO 0x474F
#define PCI_CHIP_MACH64GP 0x4750
#define PCI_CHIP_MACH64GQ 0x4751
+#define PCI_CHIP_MACH64GR 0x4752
+#define PCI_CHIP_MACH64GS 0x4753
#define PCI_CHIP_MACH64GT 0x4754
#define PCI_CHIP_MACH64GU 0x4755
+#define PCI_CHIP_MACH64GV 0x4756
+#define PCI_CHIP_MACH64GW 0x4757
#define PCI_CHIP_MACH64GX 0x4758
#define PCI_CHIP_MACH64GZ 0x475A
#define PCI_CHIP_MACH64LB 0x4C42
#define PCI_CHIP_MACH64LD 0x4C44
+#define PCI_CHIP_RAGE128LE 0x4C45
+#define PCI_CHIP_RAGE128LF 0x4C46
#define PCI_CHIP_MACH64LG 0x4C47
#define PCI_CHIP_MACH64LI 0x4C49
+#define PCI_CHIP_MACH64LM 0x4C4D
+#define PCI_CHIP_MACH64LN 0x4C4E
#define PCI_CHIP_MACH64LP 0x4C50
+#define PCI_CHIP_MACH64LR 0x4C52
+#define PCI_CHIP_MACH64LS 0x4C53
+#define PCI_CHIP_RAGE128PF 0x5046
+#define PCI_CHIP_RAGE128RE 0x5245
+#define PCI_CHIP_RAGE128RF 0x5246
+#define PCI_CHIP_RAGE128RK 0x524B
+#define PCI_CHIP_RAGE128RL 0x524C
#define PCI_CHIP_MACH64VT 0x5654
#define PCI_CHIP_MACH64VU 0x5655
#define PCI_CHIP_MACH64VV 0x5656
@@ -268,6 +287,7 @@
#define PCI_CHIP_9440 0x9440
#define PCI_CHIP_9520 0x9520
#define PCI_CHIP_9525 0x9525
+#define PCI_CHIP_9540 0x9540
#define PCI_CHIP_9660 0x9660
#define PCI_CHIP_9750 0x9750
#define PCI_CHIP_9850 0x9850
@@ -333,6 +353,9 @@
#define PCI_CHIP_SIS530 0x6306
#define PCI_CHIP_SIS6326 0x6326
#define PCI_CHIP_SIS7001 0x7001
+#define PCI_CHIP_SIS300 0x0300
+#define PCI_CHIP_SIS630 0x6300
+#define PCI_CHIP_SIS540 0x5300
/* HP */
#define PCI_CHIP_J2585A 0x1030
@@ -404,6 +427,9 @@
#define PCI_CHIP_VTNT2 0x002C
#define PCI_CHIP_UVTNT2 0x002D
#define PCI_CHIP_ITNT2 0x00A0
+#define PCI_CHIP_GEFORCE256 0x0100
+#define PCI_CHIP_GEFORCEDDR 0x0101
+#define PCI_CHIP_QUADRO 0x0103
/* NVIDIA & SGS */
#define PCI_CHIP_RIVA128 0x0018
@@ -412,6 +438,7 @@
#define PCI_CHIP_AP6410 0x3210
#define PCI_CHIP_AP6422 0x6422
#define PCI_CHIP_AT24 0x6424
+#define PCI_CHIP_AT3D 0x643D
/* 3Dfx Interactive */
#define PCI_CHIP_VOODOO_GRAPHICS 0x0001
@@ -450,10 +477,13 @@
#define PCI_CHIP_TRIO64V2_DXGX 0x8901
#define PCI_CHIP_PLATO_PX 0x8902
#define PCI_CHIP_Trio3D 0x8904
+#define PCI_CHIP_Trio3D_2X 0x8A13
#define PCI_CHIP_VIRGE_DXGX 0x8A01
#define PCI_CHIP_VIRGE_GX2 0x8A10
#define PCI_CHIP_Savage3D 0x8A20
#define PCI_CHIP_Savage3D_MV 0x8A21
+#define PCI_CHIP_Savage4 0x8A22
+#define PCI_CHIP_Savage2000 0x9102
#define PCI_CHIP_VIRGE_MX 0x8C01
#define PCI_CHIP_VIRGE_MXPLUS 0x8C01
#define PCI_CHIP_VIRGE_MXP 0x8C03
@@ -482,10 +512,9 @@
* first the VendorId - VendorName mapping
*/
extern SymTabPtr xf86PCIVendorNameInfo;
-extern SymTabRec xf86PCIVendorNameInfoData[];
#ifdef INIT_PCI_VENDOR_NAME_INFO
-SymTabRec xf86PCIVendorNameInfoData[] = {
+static SymTabRec xf86PCIVendorNameInfoData[] = {
{PCI_VENDOR_REAL3D, "Real 3D"},
{PCI_VENDOR_COMPAQ, "Compaq"},
{PCI_VENDOR_NCR_1, "NCR"},
@@ -600,688 +629,719 @@ typedef struct {
struct pciDevice {
unsigned short DeviceID;
char *DeviceName;
+ CARD16 class;
} Device[MAX_DEV_PER_VENDOR];
} pciVendorDeviceInfo;
extern pciVendorDeviceInfo* xf86PCIVendorInfo;
-extern pciVendorDeviceInfo xf86PCIVendorInfoData[];
#ifdef INIT_PCI_VENDOR_INFO
-pciVendorDeviceInfo xf86PCIVendorInfoData[] = {
+static pciVendorDeviceInfo xf86PCIVendorInfoData[] = {
{PCI_VENDOR_REAL3D, {
- {PCI_CHIP_I740_PCI, "i740 (PCI)" },
- {0x0000, NULL}}},
+ {PCI_CHIP_I740_PCI, "i740 (PCI)",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_COMPAQ, {
- {0x3033, "QVision 1280/p" },
- {0xae10, "Smart-2/P RAID Controller" },
- {0xae32, "Netellignet 10/100" },
- {0xae34, "Netellignet 10" },
- {0xae35, "NetFlex 3" },
- {0xae40, "Netellignet 10/100 Dual" },
- {0xae43, "Netellignet 10/100 ProLiant" },
- {0xb011, "Netellignet 10/100 Integrated" },
- {0xf130, "ThunderLAN" },
- {0xf150, "NetFlex 3 BNC" },
- {0x0000, NULL}}},
+ {0x3033, "QVision 1280/p",0 },
+ {0xae10, "Smart-2/P RAID Controller",0},
+ {0xae32, "Netellignet 10/100",0 },
+ {0xae34, "Netellignet 10",0 },
+ {0xae35, "NetFlex 3",0 },
+ {0xae40, "Netellignet 10/100 Dual",0 },
+ {0xae43, "Netellignet 10/100 ProLiant",0 },
+ {0xb011, "Netellignet 10/100 Integrated",0 },
+ {0xf130, "ThunderLAN",0 },
+ {0xf150, "NetFlex 3 BNC",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_NCR_1, {
- {PCI_CHIP_53C810, "53c810"},
- {PCI_CHIP_53C820, "53c820"},
- {PCI_CHIP_53C825, "53c825"},
- {PCI_CHIP_53C815, "53c815"},
- {PCI_CHIP_53C810AP, "53c810AP"},
- {PCI_CHIP_53C860, "53c860"},
- {PCI_CHIP_53C896, "53c896"},
- {PCI_CHIP_53C895, "53c895"},
- {PCI_CHIP_53C885, "53c885"},
- {PCI_CHIP_53C875, "53c875"},
- {PCI_CHIP_53C875J, "53c875J"},
- {0x0000, NULL}}},
+ {PCI_CHIP_53C810, "53c810",0},
+ {PCI_CHIP_53C820, "53c820",0},
+ {PCI_CHIP_53C825, "53c825",0},
+ {PCI_CHIP_53C815, "53c815",0},
+ {PCI_CHIP_53C810AP, "53c810AP",0},
+ {PCI_CHIP_53C860, "53c860",0},
+ {PCI_CHIP_53C896, "53c896",0},
+ {PCI_CHIP_53C895, "53c895",0},
+ {PCI_CHIP_53C885, "53c885",0},
+ {PCI_CHIP_53C875, "53c875",0},
+ {PCI_CHIP_53C875J, "53c875J",0},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_ATI, {
- {PCI_CHIP_MACH32, "Mach32"},
- {PCI_CHIP_MACH64CT, "Mach64 CT"},
- {PCI_CHIP_MACH64CX, "Mach64 CX"},
- {PCI_CHIP_MACH64ET, "Mach64 ET"},
- {PCI_CHIP_MACH64GB, "Mach64 GB"},
- {PCI_CHIP_MACH64GD, "Mach64 GD"},
- {PCI_CHIP_MACH64GI, "Mach64 GI"},
- {PCI_CHIP_MACH64GP, "Mach64 GP"},
- {PCI_CHIP_MACH64GQ, "Mach64 GQ"},
- {PCI_CHIP_MACH64GT, "Mach64 GT"},
- {PCI_CHIP_MACH64GU, "Mach64 GT"},
- {PCI_CHIP_MACH64GX, "Mach64 GX"},
- {PCI_CHIP_MACH64GZ, "Mach64 GZ"},
- {PCI_CHIP_MACH64LB, "Mach64 LB"},
- {PCI_CHIP_MACH64LD, "Mach64 LD"},
- {PCI_CHIP_MACH64LG, "Mach64 LG"},
- {PCI_CHIP_MACH64LI, "Mach64 LI"},
- {PCI_CHIP_MACH64LP, "Mach64 LP"},
- {PCI_CHIP_MACH64VT, "Mach64 VT"},
- {PCI_CHIP_MACH64VU, "Mach64 VU"},
- {PCI_CHIP_MACH64VV, "Mach64 VV"},
- {0x0000, NULL}}},
+ {PCI_CHIP_MACH32, "Mach32",0},
+ {PCI_CHIP_MACH64CT, "Mach64 CT",0},
+ {PCI_CHIP_MACH64CX, "Mach64 CX",0},
+ {PCI_CHIP_MACH64ET, "Mach64 ET",0},
+ {PCI_CHIP_MACH64GB, "Mach64 GB",0},
+ {PCI_CHIP_MACH64GD, "Mach64 GD",0},
+ {PCI_CHIP_MACH64GI, "Mach64 GI",0},
+ {PCI_CHIP_MACH64GL, "Mach64 GL",0},
+ {PCI_CHIP_MACH64GM, "Mach64 GM",0},
+ {PCI_CHIP_MACH64GN, "Mach64 GN",0},
+ {PCI_CHIP_MACH64GO, "Mach64 GO",0},
+ {PCI_CHIP_MACH64GP, "Mach64 GP",0},
+ {PCI_CHIP_MACH64GQ, "Mach64 GQ",0},
+ {PCI_CHIP_MACH64GR, "Mach64 GR",0},
+ {PCI_CHIP_MACH64GS, "Mach64 GS",0},
+ {PCI_CHIP_MACH64GT, "Mach64 GT",0},
+ {PCI_CHIP_MACH64GU, "Mach64 GU",0},
+ {PCI_CHIP_MACH64GV, "Mach64 GV",0},
+ {PCI_CHIP_MACH64GW, "Mach64 GW",0},
+ {PCI_CHIP_MACH64GX, "Mach64 GX",0},
+ {PCI_CHIP_MACH64GZ, "Mach64 GZ",0},
+ {PCI_CHIP_MACH64LB, "Mach64 LB",0},
+ {PCI_CHIP_MACH64LD, "Mach64 LD",0},
+ {PCI_CHIP_RAGE128LE, "Rage 128 Mobility LE",0},
+ {PCI_CHIP_RAGE128LF, "Rage 128 Mobility LF",0},
+ {PCI_CHIP_MACH64LG, "Mach64 LG",0},
+ {PCI_CHIP_MACH64LI, "Mach64 LI",0},
+ {PCI_CHIP_MACH64LM, "Mach64 LM",0},
+ {PCI_CHIP_MACH64LN, "Mach64 LN",0},
+ {PCI_CHIP_MACH64LP, "Mach64 LP",0},
+ {PCI_CHIP_MACH64LR, "Mach64 LR",0},
+ {PCI_CHIP_MACH64LS, "Mach64 LS",0},
+ {PCI_CHIP_RAGE128PF, "Rage 128 Pro PF",0},
+ {PCI_CHIP_RAGE128RE, "Rage 128 RE",0},
+ {PCI_CHIP_RAGE128RF, "Rage 128 RF",0},
+ {PCI_CHIP_RAGE128RK, "Rage 128 RK",0},
+ {PCI_CHIP_RAGE128RL, "Rage 128 RL",0},
+ {PCI_CHIP_MACH64VT, "Mach64 VT",0},
+ {PCI_CHIP_MACH64VU, "Mach64 VU",0},
+ {PCI_CHIP_MACH64VV, "Mach64 VV",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_VLSI, {
- {0x0005, "82C592-FC1" },
- {0x0006, "82C593-FC1" },
- {0x0007, "82C594-AFC2" },
- {0x0009, "82C597-AFC2" },
- {0x000C, "82C541 Lynx" },
- {0x000D, "82C543 Lynx ISA" },
- {0x0702, "VAS96011" },
- {0x0000, NULL}}},
+ {0x0005, "82C592-FC1",0 },
+ {0x0006, "82C593-FC1",0 },
+ {0x0007, "82C594-AFC2",0 },
+ {0x0009, "82C597-AFC2",0 },
+ {0x000C, "82C541 Lynx",0 },
+ {0x000D, "82C543 Lynx ISA",0 },
+ {0x0702, "VAS96011",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_AVANCE, {
- {PCI_CHIP_ALG2301, "ALG2301"},
- {0x0000, NULL}}},
+ {PCI_CHIP_ALG2301, "ALG2301",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_NS, {
- {0x0002, "87415" },
- {0xD001, "87410" },
- {0x0000, NULL}}},
+ {0x0002, "87415",0 },
+ {0xD001, "87410",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_TSENG, {
- {PCI_CHIP_ET4000_W32P_A, "ET4000W32P revA"},
- {PCI_CHIP_ET4000_W32P_B, "ET4000W32P revB"},
- {PCI_CHIP_ET4000_W32P_C, "ET4000W32P revC"},
- {PCI_CHIP_ET4000_W32P_D, "ET4000W32P revD"},
- {PCI_CHIP_ET6000, "ET6000/6100"},
- {PCI_CHIP_ET6300, "ET6300"},
- {0x0000, NULL}}},
+ {PCI_CHIP_ET4000_W32P_A, "ET4000W32P revA",0},
+ {PCI_CHIP_ET4000_W32P_B, "ET4000W32P revB",0},
+ {PCI_CHIP_ET4000_W32P_C, "ET4000W32P revC",0},
+ {PCI_CHIP_ET4000_W32P_D, "ET4000W32P revD",0},
+ {PCI_CHIP_ET6000, "ET6000/6100",0},
+ {PCI_CHIP_ET6300, "ET6300",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_WEITEK, {
- {PCI_CHIP_P9000, "P9000"},
- {PCI_CHIP_P9100, "P9100"},
- {0x0000, NULL}}},
+ {PCI_CHIP_P9000, "P9000",0},
+ {PCI_CHIP_P9100, "P9100",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_DIGITAL, {
- {PCI_CHIP_DEC21030, "21030/TGA"},
- {0x0001, "DC21050 PCI-PCI Bridge",
- /* print_pcibridge} */ },
- {0x0002, "DC21040 10Mb/s Ethernet" },
- {0x0009, "DC21140 10/100 Mb/s Ethernet" },
- {0x000D, "TGA2" },
- {0x000F, "DEFPA (FDDI PCI)" },
- {0x0014, "DC21041 10Mb/s Ethernet Plus" },
- {0x0019, "DC21142 10/100 Mb/s Ethernet" },
- {0x0021, "DC21052" },
- {0x0024, "DC21152" },
- {0x0000, NULL}}},
+ {PCI_CHIP_DEC21030, "21030/TGA",0},
+ {0x0001, "DC21050 PCI-PCI Bridge"
+ /* print_pcibridge} */,0 },
+ {0x0002, "DC21040 10Mb/s Ethernet",0 },
+ {0x0009, "DC21140 10/100 Mb/s Ethernet",0 },
+ {0x000D, "TGA2",0 },
+ {0x000F, "DEFPA (FDDI PCI)",0 },
+ {0x0014, "DC21041 10Mb/s Ethernet Plus",0 },
+ {0x0019, "DC21142 10/100 Mb/s Ethernet",0 },
+ {0x0021, "DC21052",0 },
+ {0x0024, "DC21152",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_CIRRUS, {
- {PCI_CHIP_GD5430, "GD5430"},
- {PCI_CHIP_GD5434_4, "GD5434"},
- {PCI_CHIP_GD5434_8, "GD5434"},
- {PCI_CHIP_GD5436, "GD5436"},
- {PCI_CHIP_GD5446, "GD5446"},
- {PCI_CHIP_GD5480, "GD5480"},
- {PCI_CHIP_GD5462, "GD5462"},
- {PCI_CHIP_GD5464, "GD5464"},
- {PCI_CHIP_GD5464BD, "GD5464BD"},
- {PCI_CHIP_GD5465, "GD5465"},
- {PCI_CHIP_GD7541, "GD7541"},
- {PCI_CHIP_GD7542, "GD7542"},
- {PCI_CHIP_GD7543, "GD7543"},
- {PCI_CHIP_GD7548, "GD7548"},
- {PCI_CHIP_GD7555, "GD7555"},
+ {PCI_CHIP_GD5430, "GD5430",0},
+ {PCI_CHIP_GD5434_4, "GD5434",0},
+ {PCI_CHIP_GD5434_8, "GD5434",0},
+ {PCI_CHIP_GD5436, "GD5436",0},
+ {PCI_CHIP_GD5446, "GD5446",0},
+ {PCI_CHIP_GD5480, "GD5480",0},
+ {PCI_CHIP_GD5462, "GD5462",0},
+ {PCI_CHIP_GD5464, "GD5464",0},
+ {PCI_CHIP_GD5464BD, "GD5464BD",0},
+ {PCI_CHIP_GD5465, "GD5465",0},
+ {PCI_CHIP_GD7541, "GD7541",0},
+ {PCI_CHIP_GD7542, "GD7542",0},
+ {PCI_CHIP_GD7543, "GD7543",0},
+ {PCI_CHIP_GD7548, "GD7548",0},
+ {PCI_CHIP_GD7555, "GD7555",0},
#ifdef VENDOR_INCLUDE_NONVIDEO
- {0x6001, "CS4236B/CS4611 Audio" },
+ {0x6001, "CS4236B/CS4611 Audio" ,0},
#endif
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_IBM, {
- {0x000A, "Fire Coral" },
- {0x0018, "Token Ring" },
- {0x001D, "82G2675" },
- {0x0022, "82351 pci-pci bridge" },
- {0x0000, NULL}}},
+ {0x000A, "Fire Coral",0 },
+ {0x0018, "Token Ring",0 },
+ {0x001D, "82G2675",0 },
+ {0x0022, "82351 pci-pci bridge",0 },
+ {0x0000, NULL,0}}},
#endif
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_NCR_2, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_WD, {
- {0x3296, "WD 7197" },
- {0x0000, NULL}}},
+ {0x3296, "WD 7197",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_AMD, {
- {0x2000, "79C970 Lance" },
- {0x2020, "53C974 SCSI" },
- {0x0000, NULL}}},
+ {0x2000, "79C970 Lance",0 },
+ {0x2020, "53C974 SCSI",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_TRIDENT, {
- {PCI_CHIP_9320, "TGUI 9320"},
- {PCI_CHIP_9420, "TGUI 9420"},
- {PCI_CHIP_9440, "TGUI 9440"},
- {PCI_CHIP_9660, "TGUI 96xx"},
- {PCI_CHIP_9388, "Cyber 9388"},
- {PCI_CHIP_9397, "Cyber 9397"},
- {PCI_CHIP_939A, "Cyber 939A/DVD"},
- {PCI_CHIP_9520, "Cyber 9520"},
- {PCI_CHIP_9525, "Cyber 9525/DVD"},
- {PCI_CHIP_9750, "3DImage975"},
- {PCI_CHIP_9850, "3DImage985"},
- {PCI_CHIP_9880, "Blade3D"},
- {PCI_CHIP_8400, "CyberBlade/i7"},
- {PCI_CHIP_8420, "CyberBlade/DSTN/i7"},
- {PCI_CHIP_8500, "CyberBlade/i1"},
- {0x0000, NULL}}},
+ {PCI_CHIP_9320, "TGUI 9320",0},
+ {PCI_CHIP_9420, "TGUI 9420",0},
+ {PCI_CHIP_9440, "TGUI 9440",0},
+ {PCI_CHIP_9660, "TGUI 96xx",0},
+ {PCI_CHIP_9388, "Cyber 9388",0},
+ {PCI_CHIP_9397, "Cyber 9397",0},
+ {PCI_CHIP_939A, "Cyber 939A/DVD",0},
+ {PCI_CHIP_9520, "Cyber 9520",0},
+ {PCI_CHIP_9525, "Cyber 9525/DVD",0},
+ {PCI_CHIP_9540, "Cyber 9540",0},
+ {PCI_CHIP_9750, "3DImage975",0},
+ {PCI_CHIP_9850, "3DImage985",0},
+ {PCI_CHIP_9880, "Blade3D",0},
+ {PCI_CHIP_8400, "CyberBlade/i7",0},
+ {PCI_CHIP_8420, "CyberBlade/DSTN/i7",0},
+ {PCI_CHIP_8500, "CyberBlade/i1",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_ALI, {
- {0x1435, "M1435"},
- {0x0000, NULL}}},
+ {0x1435, "M1435",0},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_MATROX, {
- {PCI_CHIP_MGA2085, "MGA 2085PX"},
- {PCI_CHIP_MGA2064, "MGA 2064W"},
- {PCI_CHIP_MGA1064, "MGA 1064SG"},
- {PCI_CHIP_MGA2164, "MGA 2164W"},
- {PCI_CHIP_MGA2164_AGP, "MGA 2164W AGP"},
- {PCI_CHIP_MGAG200_PCI, "MGA G200 PCI"},
- {PCI_CHIP_MGAG200, "MGA G200 AGP"},
- {PCI_CHIP_MGAG400, "MGA G400 AGP"},
- {PCI_CHIP_MGAG100_PCI, "MGA G100 PCI"},
- {PCI_CHIP_MGAG100, "MGA G100 AGP"},
- {0x0000, NULL}}},
+ {PCI_CHIP_MGA2085, "MGA 2085PX",0},
+ {PCI_CHIP_MGA2064, "MGA 2064W",0},
+ {PCI_CHIP_MGA1064, "MGA 1064SG",0},
+ {PCI_CHIP_MGA2164, "MGA 2164W",0},
+ {PCI_CHIP_MGA2164_AGP, "MGA 2164W AGP",0},
+ {PCI_CHIP_MGAG200_PCI, "MGA G200 PCI",0},
+ {PCI_CHIP_MGAG200, "MGA G200 AGP",0},
+ {PCI_CHIP_MGAG400, "MGA G400 AGP",0},
+ {PCI_CHIP_MGAG100_PCI, "MGA G100 PCI",0},
+ {PCI_CHIP_MGAG100, "MGA G100 AGP",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_CHIPSTECH, {
- {PCI_CHIP_65545, "65545"},
- {PCI_CHIP_65548, "65548"},
- {PCI_CHIP_65550, "65550"},
- {PCI_CHIP_65554, "65554"},
- {PCI_CHIP_65555, "65555"},
- {PCI_CHIP_68554, "68554"},
- {PCI_CHIP_69000, "69000"},
- {PCI_CHIP_69030, "69030"},
- {0x0000, NULL}}},
+ {PCI_CHIP_65545, "65545",0},
+ {PCI_CHIP_65548, "65548",0},
+ {PCI_CHIP_65550, "65550",0},
+ {PCI_CHIP_65554, "65554",0},
+ {PCI_CHIP_65555, "65555",0},
+ {PCI_CHIP_68554, "68554",0},
+ {PCI_CHIP_69000, "69000",0},
+ {PCI_CHIP_69030, "69030",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_MIRO, {
- {0x5601, "ZR36050" },
- {0x0000, NULL}}},
+ {0x5601, "ZR36050",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_NEC, {
- {0x0046, "PowerVR PCX2" },
- {0x0000, NULL}}},
+ {0x0046, "PowerVR PCX2",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_FD, {
- {0x0000, "TMC-18C30 (36C70)" },
- {0x0000, NULL}}},
+ {0x0000, "TMC-18C30 (36C70)",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_SIS, {
- {PCI_CHIP_SG86C201, "SG86C201"},
- {PCI_CHIP_SG86C202, "SG86C202"},
- {PCI_CHIP_SG86C205, "SG86C205"},
- {PCI_CHIP_SG86C215, "SG86C215"},
- {PCI_CHIP_SG86C225, "SG86C225"},
- {PCI_CHIP_SIS5597, "5597"},
- {PCI_CHIP_SIS530, "530"},
- {PCI_CHIP_SIS6326, "6326"},
- {0x0000, NULL}}},
+ {PCI_CHIP_SG86C201, "SG86C201",0},
+ {PCI_CHIP_SG86C202, "SG86C202",0},
+ {PCI_CHIP_SG86C205, "SG86C205",0},
+ {PCI_CHIP_SG86C215, "SG86C215",0},
+ {PCI_CHIP_SG86C225, "SG86C225",0},
+ {PCI_CHIP_SIS5597, "5597",0},
+ {PCI_CHIP_SIS530, "530",0},
+ {PCI_CHIP_SIS6326, "6326",0},
+ {PCI_CHIP_SIS300, "300",0},
+ {PCI_CHIP_SIS630, "630",0},
+ {PCI_CHIP_SIS540, "540",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_HP, {
- {0x1030, "J2585A" },
- {0x1031, "J2585B" },
- {0x0000, NULL}}},
+ {0x1030, "J2585A",0 },
+ {0x1031, "J2585B",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_SMC_PCTECH, {
- {0x1000, "FDC 37C665/RZ1000" },
- {0x1001, "FDC /RZ1001" },
- {0x0000, NULL}}},
+ {0x1000, "FDC 37C665/RZ1000",0 },
+ {0x1001, "FDC /RZ1001",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_DPT, {
- {0xA400, "SmartCache/Raid" },
- {0x0000, NULL}}},
+ {0xA400, "SmartCache/Raid",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_SGS, {
- {PCI_CHIP_STG2000, "STG2000"},
- {PCI_CHIP_STG1764, "STG1764"},
- {0x0000, NULL}}},
+ {PCI_CHIP_STG2000, "STG2000",0},
+ {PCI_CHIP_STG1764, "STG1764",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_BUSLOGIC, {
- {PCI_CHIP_946C_01, "946C 01"},
- {PCI_CHIP_946C_10, "946C 10"},
- {PCI_CHIP_FLASH_POINT, "FlashPoint"},
- {0x0000, NULL}}},
+ {PCI_CHIP_946C_01, "946C 01",0},
+ {PCI_CHIP_946C_10, "946C 10",0},
+ {PCI_CHIP_FLASH_POINT, "FlashPoint",0},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_TI, {
- {PCI_CHIP_TI_PERMEDIA, "Permedia"},
- {PCI_CHIP_TI_PERMEDIA2, "Permedia 2"},
- {PCI_CHIP_PCI_1130, "PCI 1130"},
- {PCI_CHIP_PCI_1131, "PCI 1131"},
- {0x0000, NULL}}},
+ {PCI_CHIP_TI_PERMEDIA, "Permedia",0},
+ {PCI_CHIP_TI_PERMEDIA2, "Permedia 2",0},
+ {PCI_CHIP_PCI_1130, "PCI 1130",0},
+ {PCI_CHIP_PCI_1131, "PCI 1131",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_OAK, {
- {PCI_CHIP_OTI107, "OTI107"},
- {0x0000, NULL}}},
+ {PCI_CHIP_OTI107, "OTI107",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_WINBOND, {
- {PCI_CHIP_89C940, "89C940 NE2000-PCI"},
- {0x0000, NULL}}},
+ {PCI_CHIP_89C940, "89C940 NE2000-PCI",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_MOTOROLA, {
- {PCI_CHIP_MPC105_EAGLE, "MPC105 Eagle"},
- {PCI_CHIP_MPC105_GRACKLE,"MPC105 Grackle"},
- {PCI_CHIP_RAVEN, "Raven"},
- {0x0000, NULL}}},
+ {PCI_CHIP_MPC105_EAGLE, "MPC105 Eagle",0},
+ {PCI_CHIP_MPC105_GRACKLE,"MPC105 Grackle",0},
+ {PCI_CHIP_RAVEN, "Raven",0},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_OAK, {
- {PCI_CHIP_ULTRA_DMA, "IDE UltraDMA/33"},
- {PCI_CHIP_DC5030, "DC5030"},
- {0x0000, NULL}}},
+ {PCI_CHIP_ULTRA_DMA, "IDE UltraDMA/33",0},
+ {PCI_CHIP_DC5030, "DC5030",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_NUMNINE, {
- {PCI_CHIP_I128, "Imagine 128"},
- {PCI_CHIP_I128_2, "Imagine 128 II"},
- {PCI_CHIP_I128_T2R, "Imagine 128 T2R"},
- {PCI_CHIP_I128_T2R4, "Imagine 128 T2R4"},
- {0x0000, NULL}}},
+ {PCI_CHIP_I128, "Imagine 128",0},
+ {PCI_CHIP_I128_2, "Imagine 128 II",0},
+ {PCI_CHIP_I128_T2R, "Imagine 128 T2R",0},
+ {PCI_CHIP_I128_T2R4, "Imagine 128 T2R4",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_UMC, {
- {0x0101, "UM8673F"},
- {0x673A, "UM8886BF"},
- {0x886A, "UM8886A"},
- {0x8881, "UM8881F"},
- {0x8886, "UM8886F"},
- {0x8891, "UM8891A"},
- {0x9017, "UM9017F"},
- {0xE886, "UM8886N"},
- {0xE891, "UM8891N"},
- {0x0000, NULL}}},
+ {0x0101, "UM8673F",0},
+ {0x673A, "UM8886BF",0},
+ {0x886A, "UM8886A",0},
+ {0x8881, "UM8881F",0},
+ {0x8886, "UM8886F",0},
+ {0x8891, "UM8891A",0},
+ {0x9017, "UM9017F",0},
+ {0xE886, "UM8886N",0},
+ {0xE891, "UM8891N",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_X, {
- {0x0001, "ITT AGX016"},
- {0x0000, NULL}}},
+ {0x0001, "ITT AGX016",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_PICOP, {
- {0x0001, "PT86C52x Vesuvius" },
- {0x0000, NULL}}},
+ {0x0001, "PT86C52x Vesuvius",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_MYLEX, {
- {0x0010, "AccelRAID 250" },
- {0x0000, NULL}}},
+ {0x0010, "RAID Controller",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_APPLE, {
- {0x0001, "Bandit" },
- {0x0002, "Grand Central" },
- {0x000E, "Hydra" },
- {0x0000, NULL}}},
+ {0x0001, "Bandit",0 },
+ {0x0002, "Grand Central",0 },
+ {0x000E, "Hydra",0 },
+ {0x0000, NULL,0}}},
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_NEXGEN, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_QLOGIC, {
- {0x1020, "ISP1020" },
- {0x1022, "ISP1022" },
- {0x0000, NULL}}},
+ {0x1020, "ISP1020",0 },
+ {0x1022, "ISP1022",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_CYRIX, {
- {0x0000, "5510" },
- {0x0001, "PCI Master" },
- {0x0002, "5520" },
- {0x0100, "5530 Kahlua Legacy" },
- {0x0101, "5530 Kahlua SMI" },
- {0x0102, "5530 Kahlua IDE" },
- {0x0103, "5530 Kahlua Audio" },
- {0x0104, "5530 Kahlua Video" },
- {0x0000, NULL}}},
+ {0x0000, "5510",0 },
+ {0x0001, "PCI Master",0 },
+ {0x0002, "5520",0 },
+ {0x0100, "5530 Kahlua Legacy",0 },
+ {0x0101, "5530 Kahlua SMI",0 },
+ {0x0102, "5530 Kahlua IDE",0 },
+ {0x0103, "5530 Kahlua Audio",0 },
+ {0x0104, "5530 Kahlua Video",0 },
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_LEADTEK, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_CONTAQ, {
- {0x0600, "82C599" },
- {0xc693, "82C693" },
- {0x0000, NULL}}},
+ {0x0600, "82C599",0 },
+ {0xc693, "82C693",0 },
+ {0x0000, NULL,0}}},
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_FOREX, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_OLICOM, {
- {0x0001, "OC-3136" },
- {0x0011, "OC-2315" },
- {0x0012, "OC-2325" },
- {0x0013, "OC-2183" },
- {0x0014, "OC-2326" },
- {0x0021, "OC-6151" },
- {0x0000, NULL}}},
+ {0x0001, "OC-3136",0 },
+ {0x0011, "OC-2315",0 },
+ {0x0012, "OC-2325",0 },
+ {0x0013, "OC-2183",0 },
+ {0x0014, "OC-2326",0 },
+ {0x0021, "OC-6151",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_SUN, {
- {0x1000, "EBUS" },
- {0x1001, "Happy Meal" },
- {0x8000, "PCI Bus Module" },
- {0x0000, NULL}}},
+ {0x1000, "EBUS",0 },
+ {0x1001, "Happy Meal",0 },
+ {0x8000, "PCI Bus Module",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_CMD, {
- {0x0640, "640A" },
- {0x0643, "643" },
- {0x0646, "646" },
- {0x0670, "670" },
- {0x0000, NULL}}},
+ {0x0640, "640A",0 },
+ {0x0643, "643",0 },
+ {0x0646, "646",0 },
+ {0x0670, "670",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_VISION, {
- {0x0001, "QD 8500" },
- {0x0002, "QD 8580" },
- {0x0000, NULL}}},
+ {0x0001, "QD 8500",0 },
+ {0x0002, "QD 8580",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_BROOKTREE, {
- {PCI_CHIP_BT848, "848"},
- {PCI_CHIP_BT849, "849"},
- {0x0000, NULL}}},
+ {PCI_CHIP_BT848, "848",0},
+ {PCI_CHIP_BT849, "849",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_SIERRA, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ACC, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_WINBOND_2, {
- {0x0001, "W83769F" },
- {0x0105, "SL82C105" },
- {0x0565, "W83C553" },
- {0x0000, NULL}}},
+ {0x0001, "W83769F",0 },
+ {0x0105, "SL82C105",0 },
+ {0x0565, "W83C553",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_DATABOOK, {
- {0xB106, "DB87144" },
- {0x0000, NULL}}},
+ {0xB106, "DB87144",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_3COM, {
- {0x5900, "3C590 10bT" },
- {0x5950, "3C595 100bTX" },
- {0x5951, "3C595 100bT4" },
- {0x5952, "3C595 10b-MII" },
- {0x9000, "3C900 10bTPO" },
- {0x9001, "3C900 10b Combo" },
+ {0x5900, "3C590 10bT",0 },
+ {0x5950, "3C595 100bTX",0 },
+ {0x5951, "3C595 100bT4",0 },
+ {0x5952, "3C595 10b-MII",0 },
+ {0x9000, "3C900 10bTPO",0 },
+ {0x9001, "3C900 10b Combo",0 },
/* Is it OK for 2 devices to have the same name ? */
- {0x9005, "3C900 10b Combo" },
- {0x9050, "3C905 100bTX" },
- {0x0000, NULL}}},
+ {0x9005, "3C900 10b Combo",0 },
+ {0x9050, "3C905 100bTX",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_SMC, {
- {0x0005, "9432 TX" },
- {0x0000, NULL}}},
+ {0x0005, "9432 TX",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ALI_2, {
- {0x1445, "M1445" },
- {0x1449, "M1449" },
- {0x1451, "M1451" },
- {0x1461, "M1461" },
- {0x1489, "M1489" },
- {0x1511, "M1511" },
- {0x1513, "M1513" },
- {0x1521, "M1521" },
- {0x1523, "M1523" },
- {0x1531, "M1531 Aladdin IV" },
- {0x1533, "M1533 Aladdin IV" },
- {0x5215, "M4803" },
- {0x5219, "M5219" },
- {0x5229, "M5229 TXpro" },
- {0x0000, NULL}}},
+ {0x1445, "M1445",0 },
+ {0x1449, "M1449",0 },
+ {0x1451, "M1451",0 },
+ {0x1461, "M1461",0 },
+ {0x1489, "M1489",0 },
+ {0x1511, "M1511",0 },
+ {0x1513, "M1513",0 },
+ {0x1521, "M1521",0 },
+ {0x1523, "M1523",0 },
+ {0x1531, "M1531 Aladdin IV",0 },
+ {0x1533, "M1533 Aladdin IV",0 },
+ {0x5215, "M4803",0 },
+ {0x5219, "M5219",0 },
+ {0x5229, "M5229 TXpro",0 },
+ {0x0000, NULL,0}}},
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_MITSUBISHI, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_SURECOM, {
- {0x0E34, "NE-34PCI Lan" },
- {0x0000, NULL}}},
+ {0x0E34, "NE-34PCI Lan",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_NEOMAGIC, {
- {PCI_CHIP_NM2070, "NM2070"},
- {PCI_CHIP_NM2090, "NM2090"},
- {PCI_CHIP_NM2093, "NM2093"},
- {PCI_CHIP_NM2160, "NM2160"},
- {PCI_CHIP_NM2200, "NM2200"},
- {0x0000, NULL}}},
+ {PCI_CHIP_NM2070, "NM2070",0},
+ {PCI_CHIP_NM2090, "NM2090",0},
+ {PCI_CHIP_NM2093, "NM2093",0},
+ {PCI_CHIP_NM2160, "NM2160",0},
+ {PCI_CHIP_NM2200, "NM2200",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_ASP, {
- { 0x1200, "ABP940" },
- { 0x1300, "ABP940U" },
- {0x0000, NULL}}},
+ { 0x1200, "ABP940",0 },
+ { 0x1300, "ABP940U",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_CERN, {
- { 0x0001, "STAR/RD24 SCI-PCI (PMC)" },
- { 0x0002, "STAR/RD24 SCI-PCI (PMC)" },
- {0x0000, NULL}}},
+ { 0x0001, "STAR/RD24 SCI-PCI (PMC)",0 },
+ { 0x0002, "STAR/RD24 SCI-PCI (PMC)",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_NVIDIA, {
- {PCI_CHIP_NV1, "NV1"},
- {PCI_CHIP_DAC64, "DAC64"},
- {PCI_CHIP_TNT, "Riva TNT"},
- {PCI_CHIP_TNT2, "Riva TNT2"},
- {PCI_CHIP_UTNT2, "Riva Ultra TNT2"},
- {PCI_CHIP_VTNT2, "Riva Vanta"},
- {PCI_CHIP_UVTNT2, "Riva Ultra 64"},
- {PCI_CHIP_ITNT2, "Riva Integrated"},
- {0x0000, NULL}}},
+ {PCI_CHIP_NV1, "NV1",0},
+ {PCI_CHIP_DAC64, "DAC64",0},
+ {PCI_CHIP_TNT, "Riva TNT",0},
+ {PCI_CHIP_TNT2, "Riva TNT2",0},
+ {PCI_CHIP_UTNT2, "Riva Ultra TNT2",0},
+ {PCI_CHIP_VTNT2, "Riva Vanta",0},
+ {PCI_CHIP_UVTNT2, "Riva Ultra 64",0},
+ {PCI_CHIP_ITNT2, "Riva Integrated",0},
+ {PCI_CHIP_GEFORCE256, "GeForce 256",0},
+ {PCI_CHIP_GEFORCEDDR, "GeForce DDR",0},
+ {PCI_CHIP_QUADRO, "Quadro",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_IMS, {
- {0x8849, "8849" },
- {0x0000, NULL}}},
+ {0x8849, "8849",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_TEKRAM, {
- {0x690C, "DC690C" },
- {0x0000, NULL}}},
+ {0x690C, "DC690C",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_TUNDRA, {
- {0x0000, "CA91C042 Universe" },
- {0x0000, NULL}}},
+ {0x0000, "CA91C042 Universe",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_AMCC, {
- {0x8043, "Myrinet PCI (M2-PCI-32)" },
- {0x807D, "S5933 PCI44" },
- {0x809C, "S5933 Traquair HEPC3" },
- {0x0000, NULL}}},
+ {0x8043, "Myrinet PCI (M2-PCI-32)",0 },
+ {0x807D, "S5933 PCI44",0 },
+ {0x809C, "S5933 Traquair HEPC3",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_INTEGRAPHICS, {
- {0x1680, "IGA-1680" },
- {0x1682, "IGA-1682" },
- {0x0000, NULL}}},
+ {0x1680, "IGA-1680",0 },
+ {0x1682, "IGA-1682",0 },
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_REALTEC, {
- {0x8029, "8029" },
- {0x8129, "8129" },
- {0x8139, "RTL8139 Ethernet Controller" },
- {0x0000, NULL}}},
+ {0x8029, "8029",0 },
+ {0x8129, "8129",0 },
+ {0x8139, "RTL8139 Ethernet Controller",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_TRUEVISION, {
- {0x000C, "Targa 1000" },
- {0x0000, NULL}}},
+ {0x000C, "Targa 1000",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_INITIO, {
- {0x9100, "320 P" },
- {0x0000, NULL}}},
+ {0x9100, "320 P",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_VIA, {
- {0x0501, "VT 8501 MVP4 Host Bridge" },
- {0x0505, "VT 82C505" },
- {0x0561, "VT 82C505" },
- {0x0571, "VT 82C586 MVP3 IDE Bridge" },
- {0x0576, "VT 82C576 3V" },
- {0x0586, "VT 82C586 MVP3 ISA Bridge" },
- {0x0686, "VT 82C686 MVP4 ISA Bridge" },
- {0x0597, "VT 82C598 MVP3 Host Bridge" },
- {0x3038, "VT 82C586 MVP3 USB Controller" },
- {0x3040, "VT 82C586B MVP3 ACPI Bridge" },
- {0x3057, "VT 8501 MVP4 ACPI Bridge" },
- {0x3058, "VT 8501 MVP4 MultiMedia" },
- {0x3068, "VT 8501 MVP4 Modem" },
- {0x8501, "VT 8501 MVP4 PCI/AGP Bridge" },
- {0x8598, "VT 82C598 MVP3 PCI/AGP Bridge" },
- {0x0000, NULL}}},
+ {0x0501, "VT 8501 MVP4 Host Bridge",0 },
+ {0x0505, "VT 82C505",0 },
+ {0x0561, "VT 82C505",0 },
+ {0x0571, "VT 82C586 MVP3 IDE Bridge",0 },
+ {0x0576, "VT 82C576 3V",0 },
+ {0x0586, "VT 82C586 MVP3 ISA Bridge",0 },
+ {0x0686, "VT 82C686 MVP4 ISA Bridge",0 },
+ {0x0597, "VT 82C598 MVP3 Host Bridge",0 },
+ {0x3038, "VT 82C586 MVP3 USB Controller",0 },
+ {0x3040, "VT 82C586B MVP3 ACPI Bridge",0 },
+ {0x3057, "VT 8501 MVP4 ACPI Bridge",0 },
+ {0x3058, "VT 8501 MVP4 MultiMedia",0 },
+ {0x3068, "VT 8501 MVP4 Modem",0 },
+ {0x8501, "VT 8501 MVP4 PCI/AGP Bridge",0 },
+ {0x8598, "VT 82C598 MVP3 PCI/AGP Bridge",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_VORTEX, {
- {0x0001, "GDT 6000b" },
- {0x0000, NULL}}},
+ {0x0001, "GDT 6000b",0 },
+ {0x0000, NULL,0}}},
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_EF, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_FORE, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_IMAGTEC, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_PLX, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
#endif
{PCI_VENDOR_NVIDIA_SGS, {
- {PCI_CHIP_RIVA128, "Riva128"},
- {0x0000, NULL}}},
+ {PCI_CHIP_RIVA128, "Riva128",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ALLIANCE, {
- {PCI_CHIP_AP6410, "ProMotion 6410"},
- {PCI_CHIP_AP6422, "ProMotion 6422"},
- {PCI_CHIP_AT24, "ProMotion AT24"},
- {0x0000, NULL}}},
+ {PCI_CHIP_AP6410, "ProMotion 6410",0},
+ {PCI_CHIP_AP6422, "ProMotion 6422",0},
+ {PCI_CHIP_AT24, "ProMotion AT24",0},
+ {PCI_CHIP_AT3D, "ProMotion AT3D",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_VMIC, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_DIGI, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_MUTECH, {
- {0x0001, "MV1000" },
- {0x0000, NULL}}},
+ {0x0001, "MV1000",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_RENDITION, {
- {PCI_CHIP_V1000, "Verite 1000"},
- {PCI_CHIP_V2x00, "Verite 2x00"},
- {0x0000, NULL}}},
+ {PCI_CHIP_V1000, "Verite 1000",0},
+ {PCI_CHIP_V2x00, "Verite 2100/2200",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_TOSHIBA, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ZEINET, {
- {0x0001, "1221" },
- {0x0000, NULL}}},
+ {0x0001, "1221",0 },
+ {0x0000, NULL,0}}},
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_SPECIALIX, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_CONTROL, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_CYCLADES, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
#endif
{PCI_VENDOR_3DFX, {
- {PCI_CHIP_VOODOO_GRAPHICS, "Voodoo Graphics"},
- {PCI_CHIP_VOODOO2, "Voodoo2"},
- {PCI_CHIP_BANSHEE, "Banshee"},
- {0x0000, NULL}}},
+ {PCI_CHIP_VOODOO_GRAPHICS, "Voodoo Graphics",0},
+ {PCI_CHIP_VOODOO2, "Voodoo2",0},
+ {PCI_CHIP_BANSHEE, "Banshee",0},
+ {PCI_CHIP_VOODOO3, "Voodoo3",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_SIGMADESIGNS, {
- {0x6401, "REALmagic64/GX (SD 6425)" },
- {0x0000, NULL}}},
+ {0x6401, "REALmagic64/GX (SD 6425)",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ENSONIQ, {
- {0x5000, "es1370 (AudioPCI)" },
- {0x1371, "es1371" },
- {0x0000, NULL}}},
+ {0x5000, "es1370 (AudioPCI)",0 },
+ {0x1371, "es1371",0 },
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
#ifdef INCLUDE_EMPTY_LISTS
{PCI_VENDOR_YOKOGAWA, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
#endif
#endif
{PCI_VENDOR_TRITECH, {
- {PCI_CHIP_TR25202, "Pyramid3D TR25202"},
- {0x0000, NULL}}},
+ {PCI_CHIP_TR25202, "Pyramid3D TR25202",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_NVIDIA_SGS, {
- {0x0018, "Riva128" },
- {0x0000, NULL}}},
+ {0x0018, "Riva128",0 },
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_SYMPHONY, {
- {0x0001, "82C101" },
- {0x0000, NULL}}},
+ {0x0001, "82C101",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_TEKRAM_2, {
- {0xDC29, "DC290" },
- {0x0000, NULL}}},
+ {0xDC29, "DC290",0 },
+ {0x0000, NULL,0}}},
#endif
{PCI_VENDOR_3DLABS, {
- {PCI_CHIP_300SX, "GLINT 300SX"},
- {PCI_CHIP_500TX, "GLINT 500TX"},
- {PCI_CHIP_DELTA, "GLINT Delta"},
- {PCI_CHIP_PERMEDIA, "GLINT Permedia"},
- {PCI_CHIP_MX, "GLINT MX"},
- {PCI_CHIP_PERMEDIA2, "GLINT Permedia 2"},
- {PCI_CHIP_GAMMA, "GLINT Gamma"},
- {PCI_CHIP_PERMEDIA2V, "GLINT Permedia 2v"},
- {0x0000, NULL}}},
+ {PCI_CHIP_300SX, "GLINT 300SX",0},
+ {PCI_CHIP_500TX, "GLINT 500TX",0},
+ {PCI_CHIP_DELTA, "GLINT Delta",0},
+ {PCI_CHIP_PERMEDIA, "GLINT Permedia",0},
+ {PCI_CHIP_MX, "GLINT MX",0},
+ {PCI_CHIP_PERMEDIA2, "GLINT Permedia 2",0},
+ {PCI_CHIP_GAMMA, "GLINT Gamma",0},
+ {PCI_CHIP_PERMEDIA2V, "GLINT Permedia 2v",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_AVANCE_2, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_S3, {
- {PCI_CHIP_PLATO, "PLATO/PX"},
- {PCI_CHIP_VIRGE, "ViRGE"},
- {PCI_CHIP_TRIO, "Trio32/64"},
- {PCI_CHIP_AURORA64VP, "Aurora64V+"},
- {PCI_CHIP_TRIO64UVP, "Trio64UV+"},
- {PCI_CHIP_TRIO64V2_DXGX,"Trio64V2/DX or /GX"},
- {PCI_CHIP_PLATO_PX, "PLATO/PX"},
- {PCI_CHIP_Trio3D, "Trio3D"},
- {PCI_CHIP_VIRGE_VX, "ViRGE/VX"},
- {PCI_CHIP_VIRGE_DXGX, "ViRGE/DX or /GX"},
- {PCI_CHIP_VIRGE_GX2, "ViRGE/GX2"},
- {PCI_CHIP_Savage3D, "Savage3D (86E391)"},
- {PCI_CHIP_Savage3D_MV, "Savage3D+MacroVision (86E390)"},
- {PCI_CHIP_VIRGE_MX, "ViRGE/MX"},
- {PCI_CHIP_VIRGE_MXPLUS, "ViRGE/MX+"},
- {PCI_CHIP_VIRGE_MXP, "ViRGE/MX+MV"},
- {PCI_CHIP_868, "868"},
- {PCI_CHIP_928, "928"},
- {PCI_CHIP_864_0, "864"},
- {PCI_CHIP_864_1, "864"},
- {PCI_CHIP_964_0, "964"},
- {PCI_CHIP_964_1, "964"},
- {PCI_CHIP_968, "968"},
- {0x0000, NULL}}},
+ {PCI_CHIP_PLATO, "PLATO/PX",0},
+ {PCI_CHIP_VIRGE, "ViRGE",0},
+ {PCI_CHIP_TRIO, "Trio32/64",0},
+ {PCI_CHIP_AURORA64VP, "Aurora64V+",0},
+ {PCI_CHIP_TRIO64UVP, "Trio64UV+",0},
+ {PCI_CHIP_TRIO64V2_DXGX,"Trio64V2/DX or /GX",0},
+ {PCI_CHIP_PLATO_PX, "PLATO/PX",0},
+ {PCI_CHIP_Trio3D, "Trio3D",0},
+ {PCI_CHIP_Trio3D_2X, "Trio3D/2X",0},
+ {PCI_CHIP_VIRGE_VX, "ViRGE/VX",0},
+ {PCI_CHIP_VIRGE_DXGX, "ViRGE/DX or /GX",0},
+ {PCI_CHIP_VIRGE_GX2, "ViRGE/GX2",0},
+ {PCI_CHIP_Savage3D, "Savage3D (86E391)",0},
+ {PCI_CHIP_Savage3D_MV, "Savage3D+MacroVision (86E390)",0},
+ {PCI_CHIP_Savage4, "Savage4",0},
+ {PCI_CHIP_Savage2000, "Savage2000",0},
+ {PCI_CHIP_VIRGE_MX, "ViRGE/MX",0},
+ {PCI_CHIP_VIRGE_MXPLUS, "ViRGE/MX+",0},
+ {PCI_CHIP_VIRGE_MXP, "ViRGE/MX+MV",0},
+ {PCI_CHIP_868, "868",0},
+ {PCI_CHIP_928, "928",0},
+ {PCI_CHIP_864_0, "864",0},
+ {PCI_CHIP_864_1, "864",0},
+ {PCI_CHIP_964_0, "964",0},
+ {PCI_CHIP_964_1, "964",0},
+ {PCI_CHIP_968, "968",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_INTEL,{
- {0x0482, "82375EB pci-eisa bridge"},
- {0x0483, "82424ZX cache dram controller"},
- {0x0484, "82378IB/ZB pci-isa bridge"},
- {0x0486, "82430ZX Aries"},
- {0x04A3, "82434LX/NX pci cache mem controller"},
- {0x0960, "960RD processor/bridge"},
- {0x1221, "82092AA"},
- {0x1222, "82092AA"},
- {0x1223, "SAA7116"},
- {0x1226, "82596"},
- {0x1227, "82865"},
- {0x1229, "82557/8 10/100MBit network controller"},
- {0x122D, "82437 Triton"},
- {0x122E, "82471 Triton"},
- {0x1230, "82371 bus-master IDE controller"},
- {0x1234, "82371MX bus-master IDE controller"},
- {0x1235, "82437MX"},
- {0x1237, "82441FX Natoma"},
- {0x124B, "82380FB"},
- {0x1250, "82439"},
- {0x7000, "82371 pci-isa bridge"},
- {0x7010, "82371 bus-master IDE controller"},
- {0x7020, "82371 bus-master IDE controller"},
- {0x7030, "82437VX"},
- {0x7100, "82439TX"},
- {0x7110, "82371AB PIIX4 ISA"},
- {0x7111, "82371AB PIIX4 IDE"},
- {0x7112, "82371AB PIIX4 USB"},
- {0x7113, "82371AB PIIX4 ACPI"},
- {0x7180, "82443LX PAC Host"},
- {0x7181, "82443LX PAC AGP"},
- {0x7190, "82443BX Host"},
- {0x7191, "82443BX AGP"},
- {0x7192, "82443BX Host (no AGP)"},
- {0x71a0, "82443GX Host"},
- {0x71a1, "82443GX AGP"},
- {0x71a2, "82443GX Host (no AGP)"},
- {0x84C4, "P6"},
- {0x84C5, "82450GX20"},
- {PCI_CHIP_I740_AGP, "i740 (AGP)"},
- {0x0000, NULL}}},
+ {0x0482, "82375EB pci-eisa bridge",0},
+ {0x0483, "82424ZX cache dram controller",0},
+ {0x0484, "82378IB/ZB pci-isa bridge",0x0601},
+ {0x0486, "82430ZX Aries",0},
+ {0x04A3, "82434LX/NX pci cache mem controller",0},
+ {0x0960, "960RD processor/bridge",0},
+ {0x1221, "82092AA",0},
+ {0x1222, "82092AA",0},
+ {0x1223, "SAA7116",0},
+ {0x1226, "82596",0},
+ {0x1227, "82865",0},
+ {0x1229, "82557/8/9 10/100MBit network controller",0 },
+ {0x122D, "82437 Triton",0},
+ {0x122E, "82471 Triton",0},
+ {0x1230, "82371 bus-master IDE controller",0},
+ {0x1234, "82371MX bus-master IDE controller",0},
+ {0x1235, "82437MX",0},
+ {0x1237, "82441FX Natoma",0},
+ {0x124B, "82380FB",0},
+ {0x1250, "82439",0},
+ {0x7000, "82371 pci-isa bridge",0},
+ {0x7010, "82371 bus-master IDE controller",0},
+ {0x7020, "82371 bus-master IDE controller",0},
+ {0x7030, "82437VX",0},
+ {0x7100, "82439TX",0},
+ {0x7110, "82371AB PIIX4 ISA",0},
+ {0x7111, "82371AB PIIX4 IDE",0},
+ {0x7112, "82371AB PIIX4 USB",0},
+ {0x7113, "82371AB PIIX4 ACPI",0},
+ {0x7180, "82443LX PAC Host",0},
+ {0x7181, "82443LX PAC AGP",0},
+ {0x7190, "82443BX Host",0},
+ {0x7191, "82443BX AGP",0},
+ {0x7192, "82443BX Host (no AGP)",0},
+ {0x71a0, "82443GX Host",0},
+ {0x71a1, "82443GX AGP",0},
+ {0x71a2, "82443GX Host (no AGP)",0},
+ {0x84C4, "P6",0},
+ {0x84C5, "82450GX20",0},
+ {PCI_CHIP_I740_AGP, "i740 (AGP)",0},
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ADAPTEC, {
- {0x0010, "2940U2" },
- {0x1078, "7810" },
- {0x5078, "7850" },
- {0x5578, "7855" },
- {0x6078, "7860" },
- {0x6178, "2940AU" },
- {0x7078, "7870" },
- {0x7178, "2940" },
- {0x7278, "7872" },
- {0x7378, "398X" },
- {0x7478, "2944" },
- {0x7895, "7895" },
- {0x8078, "7880" },
- {0x8178, "2940U/UW" },
- {0x8278, "3940U/UW" },
- {0x8378, "389XU" },
- {0x8478, "2944U" },
- {0x0000, NULL}}},
+ {0x0010, "2940U2",0 },
+ {0x1078, "7810",0 },
+ {0x5078, "7850",0 },
+ {0x5578, "7855",0 },
+ {0x6078, "7860",0 },
+ {0x6178, "2940AU",0 },
+ {0x7078, "7870",0 },
+ {0x7178, "2940",0 },
+ {0x7278, "7872",0 },
+ {0x7378, "398X",0 },
+ {0x7478, "2944",0 },
+ {0x7895, "7895",0 },
+ {0x8078, "7880",0 },
+ {0x8178, "2940U/UW",0 },
+ {0x8278, "3940U/UW",0 },
+ {0x8378, "389XU",0 },
+ {0x8478, "2944U",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ADAPTEC_2, {
- {0x001F, "7890/7891" },
- {0x0000, NULL}}},
+ {0x001F, "7890/7891",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ATRONICS, {
- {0x2015, "IDE-2015PL" },
- {0x0000, NULL}}},
+ {0x2015, "IDE-2015PL",0 },
+ {0x0000, NULL,0}}},
{PCI_VENDOR_ARK, {
- {PCI_CHIP_1000PV, "1000PV"},
- {PCI_CHIP_2000PV, "2000PV"},
- {PCI_CHIP_2000MT, "2000MT"},
- {PCI_CHIP_2000MI, "2000MI"},
- {0x0000, NULL}}},
+ {PCI_CHIP_1000PV, "1000PV",0},
+ {PCI_CHIP_2000PV, "2000PV",0},
+ {PCI_CHIP_2000MT, "2000MT",0},
+ {PCI_CHIP_2000MI, "2000MI",0},
+ {0x0000, NULL,0}}},
#ifdef VENDOR_INCLUDE_NONVIDEO
{PCI_VENDOR_YAMAHA, {
- {0x000a, "YMF740-V Audio"},
- {0x0000, NULL}}},
+ {0x000a, "YMF740-V Audio",0},
+ {0x0000, NULL,0}}},
#endif
{0x0000, {
- {0x0000, NULL}}},
+ {0x0000, NULL,0}}},
};
#endif
@@ -1296,184 +1356,178 @@ typedef struct {
struct pciCard {
unsigned short SubsystemID;
char *CardName;
+ CARD16 class;
pciPrintProcPtr printFunc;
} Device[MAX_CARD_PER_VENDOR];
} pciVendorCardInfo;
-extern pciVendorCardInfo *xf86PCICardInfo;
-extern pciVendorCardInfo xf86PCICardInfoData[];
+extern pciVendorCardInfo* xf86PCICardInfo;
+
#ifdef INIT_PCI_CARD_INFO
#define NF (pciPrintProcPtr)NULL
-pciVendorCardInfo xf86PCICardInfoData[] = {
+static pciVendorCardInfo xf86PCICardInfoData[] = {
#ifdef VENDOR_INCLUDE_NONVIDEO
{ PCI_VENDOR_3COM, {
- { 0x9005, "PCI Combo ethernet card" },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x9005, "PCI Combo ethernet card",0,NF },
+ { 0x0000, (char *)NULL,0, NF } } },
#endif
#ifdef VENDOR_INCLUDE_NONVIDEO
{ PCI_VENDOR_ADAPTEC, {
- { 0x7881, "AHA-2940U/UW SCSI", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x7881, "AHA-2940U/UW SCSI",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
#endif
- { PCI_VENDOR_ATI, {
- { 0x4750, "XPERT XL", NF },
- { 0x4755, "Mach64-GT-B+DVD", NF },
- { 0x0084, "Xpert'98", NF },
- { 0x4d55, "264GT3 (Rage3D III)", NF },
- { 0x0088, "Mach64 (SuSE Econ)", NF },
- { 0x4c42, "XPERT LCD", NF },
- { 0x0000, (char *)NULL, NF } } },
+ /* ATI card info deleted; unmaintainable */
#ifdef VENDOR_INCLUDE_NONVIDEO
#ifdef INCLUDE_EMPTY_LISTS
{ PCI_VENDOR_COMPAQ, {
- { 0x0000, (char *)NULL, NF } } },
+ { 0x0000, (char *)NULL,0, NF } } },
#endif
#ifdef VENDOR_INCLUDE_NONVIDEO
{ PCI_VENDOR_NCR_1, {
- { 0x1000, "SCSI HBA", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x1000, "SCSI HBA",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{ PCI_VENDOR_REALTEC, {
- { 0x8139, "Generic", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x8139, "Generic",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
#endif
{ PCI_VENDOR_CREATIVE_2, {
- { 0x1017, "3D Blaster Banshee", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x1017, "3D Blaster Banshee",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{PCI_VENDOR_DIGITAL, {
- { 0x500A, "EtherWORKS 10/100", NF},
- { 0x0000, (char *)NULL, NF } } },
+ { 0x500A, "EtherWORKS 10/100",0, NF},
+ { 0x0000, (char *)NULL,0, NF } } },
#endif
{ PCI_VENDOR_DIAMOND, {
- { 0x8000, "C&T 69000", NF },
- { 0x1103, "Fire GL 1000", NF },
- { 0x0154, "Fire GL 1000 PRO", NF },
- { 0x0003, "Monster Fusion", NF },
- { 0x8a10, "Stealth 3D 4000", NF },
- { 0x0100, "Stealth II G460", NF },
- { 0x2000, "Stealth II S220", NF },
- { 0x1092, "Viper 330", NF },
- { 0x0550, "Viper 550", NF },
- { 0x8760, "Fireport 40 Dual", NF },
- { 0x2110, "Sonic Impact S70", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x8000, "C&T 69000",0, NF },
+ { 0x1103, "Fire GL 1000",0, NF },
+ { 0x0154, "Fire GL 1000 PRO",0, NF },
+ { 0x0003, "Monster Fusion",0, NF },
+ { 0x8a10, "Stealth 3D 4000",0, NF },
+ { 0x0100, "Stealth II G460",0, NF },
+ { 0x2000, "Stealth II S220",0, NF },
+ { 0x1092, "Viper 330",0, NF },
+ { 0x0550, "Viper 550",0, NF },
+ { 0x8760, "Fireport 40 Dual",0, NF },
+ { 0x2110, "Sonic Impact S70",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{ PCI_VENDOR_ELSA, {
- { 0x0914, "Winner 1000", NF },
- { 0x0930, "Winner 1000PRO 864", NF },
- { 0x0931, "Winner 1000PRO Trio32", NF },
- { 0x0932, "Winner 1000Trio Trio64", NF },
- { 0x0933, "Winner 1000TrioV Trio64V+", NF },
- { 0x0934, "Victory 3D", NF },
- { 0x0935, "Winner 1000 T2D", NF },
- { 0x0936, "Winner 1000PRO 868", NF },
- { 0x0937, "Winner 1000PRO/X 868", NF },
- { 0x0938, "Winner 1000ViRGE", NF },
- { 0x0939, "Winner 1000ViRGE/DX", NF },
- { 0x093a, "Winner 1000/T2DX", NF },
- { 0x093b, "Winner DUO M5", NF },
- { 0x093c, "Victory 1000", NF },
- { 0x0940, "Winner 2000PRO 964/TVP3020", NF },
- { 0x0941, "Winner 2000PRO/X 968/TVP3020", NF },
- { 0x0942, "Winner 2000PRO/X 968/TVP3026", NF },
- { 0x0943, "Winner 2000AVI 968/TVP3026", NF },
- { 0x0948, "Winner 2000PRO-8 964/RGB528", NF },
- { 0x094a, "Winner 2000PRO-8 968/RGB528", NF },
- { 0x094b, "Winner 2000PRO-8 968/TVP3030", NF },
- { 0x0950, "ViRGE/VX", NF },
- { 0x0951, "Winner 2000AVI 3D", NF },
- { 0x0952, "Winner 2000AVI 220", NF },
- { 0x0960, "Winner 3000M", NF },
- { 0x0962, "Winner 3000L", NF },
- { 0x0964, "Winner 3000XL", NF },
- { 0x096a, "Winner 3000Twin", NF },
- { 0x096c, "Winner 3000LT", NF },
- { 0x0980, "GLoria 4 TVP3026", NF },
- { 0x0982, "GLoria 4 TVP3030", NF },
- { 0x0981, "GLoria 8", NF },
- { 0x0a10, "GLoria M", NF },
- { 0x0a14, "GLoria S", NF },
- { 0x0a31, "Winner 2000 Office", NF },
- { 0x0a32, "GLoria Synergy P2C", NF },
- { 0x0a33, "GLoria Synergy P2C", NF },
- { 0x0a34, "GLoria Synergy P2V", NF },
- { 0x0a35, "GLoria Synergy P2A", NF },
- { 0x0a36, "Quad GLoria Synergy P2A", NF },
- { 0x0a40, "GLoria MX", NF },
- { 0x0a41, "GLoria XL", NF },
- { 0x0a42, "GLoria XXL", NF },
- { 0x0a43, "Winner 2000 Office P2V", NF },
- { 0x0a44, "Winner 2000 Office P2A", NF },
- { 0x0a80, "GLoria S MAC", NF },
- { 0x0c10, "Victory Erazor 4", NF },
- { 0x0c11, "Victory Erazor 8", NF },
- { 0x0c12, "Winner 1000 R3D", NF },
- { 0x0c13, "Winner 1000 ZX4", NF },
- { 0x0c14, "Victory Erazor/LT SGRAM", NF },
- { 0x0c15, "Victory Erazor/LT SDRAM", NF },
- { 0x0c18, "Erazor II SGRAM", NF },
- { 0x0c19, "Erazor II SDRAM video", NF },
- { 0x0c1a, "Synergy Pro", NF },
- { 0x0c1c, "Erazor II SDRAM", NF },
- { 0x0c20, "Synergy II 32", NF },
- { 0x0c21, "Synergy II 16", NF },
- { 0x0c22, "Erazor III", NF },
- { 0x0c23, "Erazor III video", NF },
- { 0x0d10, "Victory II SGRAM", NF },
- { 0x0d11, "Victory II SDRAM", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x0914, "Winner 1000",0, NF },
+ { 0x0930, "Winner 1000PRO 864",0, NF },
+ { 0x0931, "Winner 1000PRO Trio32",0, NF },
+ { 0x0932, "Winner 1000Trio Trio64",0, NF },
+ { 0x0933, "Winner 1000TrioV Trio64V+",0, NF },
+ { 0x0934, "Victory 3D",0, NF },
+ { 0x0935, "Winner 1000 T2D",0, NF },
+ { 0x0936, "Winner 1000PRO 868",0, NF },
+ { 0x0937, "Winner 1000PRO/X 868",0, NF },
+ { 0x0938, "Winner 1000ViRGE",0, NF },
+ { 0x0939, "Winner 1000ViRGE/DX",0, NF },
+ { 0x093a, "Winner 1000/T2DX",0, NF },
+ { 0x093b, "Winner DUO M5",0, NF },
+ { 0x093c, "Victory 1000",0, NF },
+ { 0x0940, "Winner 2000PRO 964/TVP3020",0, NF },
+ { 0x0941, "Winner 2000PRO/X 968/TVP3020",0, NF },
+ { 0x0942, "Winner 2000PRO/X 968/TVP3026",0, NF },
+ { 0x0943, "Winner 2000AVI 968/TVP3026",0, NF },
+ { 0x0948, "Winner 2000PRO-8 964/RGB528",0, NF },
+ { 0x094a, "Winner 2000PRO-8 968/RGB528",0, NF },
+ { 0x094b, "Winner 2000PRO-8 968/TVP3030",0, NF },
+ { 0x0950, "ViRGE/VX",0, NF },
+ { 0x0951, "Winner 2000AVI 3D",0, NF },
+ { 0x0952, "Winner 2000AVI 220",0, NF },
+ { 0x0960, "Winner 3000M",0, NF },
+ { 0x0962, "Winner 3000L",0, NF },
+ { 0x0964, "Winner 3000XL",0, NF },
+ { 0x096a, "Winner 3000Twin",0, NF },
+ { 0x096c, "Winner 3000LT",0, NF },
+ { 0x0980, "GLoria 4 TVP3026",0, NF },
+ { 0x0982, "GLoria 4 TVP3030",0, NF },
+ { 0x0981, "GLoria 8",0, NF },
+ { 0x0a10, "GLoria M",0, NF },
+ { 0x0a14, "GLoria S",0, NF },
+ { 0x0a31, "Winner 2000 Office",0, NF },
+ { 0x0a32, "GLoria Synergy P2C",0, NF },
+ { 0x0a33, "GLoria Synergy P2C",0, NF },
+ { 0x0a34, "GLoria Synergy P2V",0, NF },
+ { 0x0a35, "GLoria Synergy P2A",0, NF },
+ { 0x0a36, "Quad GLoria Synergy P2A",0, NF },
+ { 0x0a40, "GLoria MX",0, NF },
+ { 0x0a41, "GLoria XL",0, NF },
+ { 0x0a42, "GLoria XXL",0, NF },
+ { 0x0a43, "Winner 2000 Office P2V",0, NF },
+ { 0x0a44, "Winner 2000 Office P2A",0, NF },
+ { 0x0a80, "GLoria S MAC",0, NF },
+ { 0x0c10, "Victory Erazor 4",0, NF },
+ { 0x0c11, "Victory Erazor 8",0, NF },
+ { 0x0c12, "Winner 1000 R3D",0, NF },
+ { 0x0c13, "Winner 1000 ZX4",0, NF },
+ { 0x0c14, "Victory Erazor/LT SGRAM",0, NF },
+ { 0x0c15, "Victory Erazor/LT SDRAM",0, NF },
+ { 0x0c18, "Erazor II SGRAM",0, NF },
+ { 0x0c19, "Erazor II SDRAM video",0, NF },
+ { 0x0c1a, "Synergy Pro",0, NF },
+ { 0x0c1c, "Erazor II SDRAM",0, NF },
+ { 0x0c20, "Synergy II 32",0, NF },
+ { 0x0c21, "Synergy II 16",0, NF },
+ { 0x0c22, "Erazor III",0, NF },
+ { 0x0c23, "Erazor III video",0, NF },
+ { 0x0d10, "Victory II SGRAM",0, NF },
+ { 0x0d11, "Victory II SDRAM",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{ PCI_VENDOR_HERCULES, {
- { 0x0001, "Thriller3D", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x0001, "Thriller3D",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{ PCI_VENDOR_IBM, {
- { 0x00ba, "Thinkpad 600 NeoMagic NM2160", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x00ba, "Thinkpad 600 NeoMagic NM2160",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{PCI_VENDOR_INTEL, {
#ifdef VENDOR_INCLUDE_NONVIDEO
- { 0x0009, "PCI 10/100Mb/s ethernet card", NF },
+ { 0x0009, "PCI 10/100Mb/s ethernet card",0, NF },
/* Seattle AL440BX is 0x8080, is anything else ? */
- { 0x8080, "motherboard", NF },
- { 0x4d55, "Maui (MU) motherboard", NF },
+ { 0x8080, "motherboard",0, NF },
+ { 0x4d55, "Maui (MU) motherboard",0, NF },
#endif
- { 0x0000, (char *)NULL, NF } } },
+ { 0x0000, (char *)NULL,0, NF } } },
{ PCI_VENDOR_MATROX, {
- { 0x1100, "Mystique", NF },
- { 0x1000, "Millennium II", NF },
- { 0x0100, "Millennium II", NF },
- { 0x1200, "Millennium II", NF },
- { PCI_CARD_MILL_G200_SD, "Millennium G200 SD", NF },
- { PCI_CARD_PROD_G100_SD, "Produktiva G100 SD", NF },
- { PCI_CARD_MYST_G200_SD, "Mystique G200 SD", NF },
- { PCI_CARD_MILL_G200_SG, "Millennium G200 SG", NF },
- { PCI_CARD_MARV_G200_SD, "Marvel G200 SD", NF },
- { 0x1001, "Productiva G100 SG", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x1100, "Mystique",0, NF },
+ { 0x1000, "Millennium II",0, NF },
+ { 0x0100, "Millennium II",0, NF },
+ { 0x1200, "Millennium II",0, NF },
+ { PCI_CARD_MILL_G200_SD, "Millennium G200 SD",0, NF },
+ { PCI_CARD_PROD_G100_SD, "Produktiva G100 SD",0, NF },
+ { PCI_CARD_MYST_G200_SD, "Mystique G200 SD",0, NF },
+ { PCI_CARD_MILL_G200_SG, "Millennium G200 SG",0, NF },
+ { PCI_CARD_MARV_G200_SD, "Marvel G200 SD",0, NF },
+ { 0x1001, "Productiva G100 SG",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{ PCI_VENDOR_SIS, {
- { 0x6306, "530 based motherboard", NF },
- { 0x6326, "6326 based card", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x6306, "530 based motherboard",0, NF },
+ { 0x6326, "6326 based card",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
#ifdef VENDOR_INCLUDE_NONVIDEO
{ PCI_VENDOR_CREATIVE, {
- { 0x4c4c, "Sound Blaster PCI128", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x4c4c, "Sound Blaster PCI128",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
#endif
{ PCI_VENDOR_S3, {
- { 0x8904, "Trio3D", NF },
- { 0x8a10, "ViRGE/GX2", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x8904, "Trio3D",0, NF },
+ { 0x8a10, "ViRGE/GX2",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{ PCI_VENDOR_NUMNINE, {
- { 0x8a10, "Reality 334", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x8a10, "Reality 334",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
{ PCI_VENDOR_TOSHIBA, {
- { 0x0001, "4010CDT CT65555", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x0001, "4010CDT CT65555",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
#ifdef VENDOR_INCLUDE_NONVIDEO
{ PCI_VENDOR_BUSLOGIC, {
- { 0x1040, "BT958", NF },
- { 0x0000, (char *)NULL, NF } } },
+ { 0x1040, "BT958",0, NF },
+ { 0x0000, (char *)NULL,0, NF } } },
#endif
{0x0000, {
- {0x0000, NULL, NF } } },
+ {0x0000, NULL,0, NF } } },
};
#endif
#endif
diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h
index 29fa87a5b..e948cb6b9 100644
--- a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h
+++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h
@@ -103,7 +103,7 @@ typedef struct {
CARD32 amcgpio_en_reg;
CARD32 amcgpio_mask;
- /* Crtc registers */
+ /* CRTC registers */
CARD32 crtc_gen_cntl;
CARD32 crtc_ext_cntl;
CARD32 dac_cntl;
@@ -115,6 +115,21 @@ typedef struct {
CARD32 crtc_offset_cntl;
CARD32 crtc_pitch;
+ /* CRTC2 registers */
+ CARD32 crtc2_gen_cntl;
+
+ /* Flat panel registers */
+ CARD32 fp_crtc_h_total_disp;
+ CARD32 fp_crtc_v_total_disp;
+ CARD32 fp_gen_cntl;
+ CARD32 fp_h_sync_strt_wid;
+ CARD32 fp_horz_stretch;
+ CARD32 fp_panel_cntl;
+ CARD32 fp_v_sync_strt_wid;
+ CARD32 fp_vert_stretch;
+ CARD32 lvds_gen_cntl;
+ CARD32 tmds_crc;
+
/* Computed values for PLL */
int dot_clock_freq;
int pll_output_freq;
@@ -164,6 +179,20 @@ typedef struct {
unsigned long FbMapSize; /* Size of frame buffer, in bytes */
int Flags; /* Saved copy of mode flags */
+ Bool EnableFP; /* Enable use of FP registers */
+ Bool CRTOnly; /* Only use External CRT instead of FP */
+ Bool HasPanelRegs; /* Current chip can connect to a FP */
+
+ /* Computed values for FPs */
+ int PanelXRes;
+ int PanelYRes;
+ int PanelHNonVis;
+ int PanelHOverPlus;
+ int PanelHSyncWidth;
+ int PanelVNonVis;
+ int PanelVOverPlus;
+ int PanelVSyncWidth;
+
R128PLLRec pll;
R128RAMPtr ram;
diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c
index f30d86aa8..ea0742a99 100644
--- a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c
+++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c
@@ -171,6 +171,8 @@ static SymTabRec R128Chipsets[] = {
{ PCI_CHIP_RAGE128RK, "ATI Rage 128 RK (PCI)" },
{ PCI_CHIP_RAGE128RL, "ATI Rage 128 RL (AGP)" },
{ PCI_CHIP_RAGE128PF, "ATI Rage 128 Pro PF (AGP)" },
+ { PCI_CHIP_RAGE128LE, "ATI Rage 128 Mobility LE (PCI)" },
+ { PCI_CHIP_RAGE128LF, "ATI Rage 128 Mobility LF (AGP)" },
{ -1, NULL }
};
@@ -180,6 +182,8 @@ static PciChipsets R128PciChipsets[] = {
{ PCI_CHIP_RAGE128RK, PCI_CHIP_RAGE128RK, RES_SHARED_VGA },
{ PCI_CHIP_RAGE128RL, PCI_CHIP_RAGE128RL, RES_SHARED_VGA },
{ PCI_CHIP_RAGE128PF, PCI_CHIP_RAGE128PF, RES_SHARED_VGA },
+ { PCI_CHIP_RAGE128LE, PCI_CHIP_RAGE128LE, RES_SHARED_VGA },
+ { PCI_CHIP_RAGE128LF, PCI_CHIP_RAGE128LF, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
@@ -201,6 +205,8 @@ typedef enum {
OPTION_VBUF_SIZE,
OPTION_USE_CCE_2D,
#endif
+ OPTION_ENABLE_FP,
+ OPTION_CRT,
OPTION_FBDEV
} R128Opts;
@@ -222,6 +228,8 @@ static OptionInfoRec R128Options[] = {
{ OPTION_VBUF_SIZE, "VBSize", OPTV_INTEGER, {0}, FALSE },
{ OPTION_USE_CCE_2D, "UseCCEfor2D", OPTV_BOOLEAN, {0}, FALSE },
#endif
+ { OPTION_ENABLE_FP, "EnableFP", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_CRT, "CRTOnly", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_FBDEV, "UseFBDev", OPTV_BOOLEAN, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
@@ -852,6 +860,9 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
int offset = 0; /* RAM Type */
MessageType from;
unsigned char *R128MMIO;
+ CARD32 fp_horz_stretch = 0, fp_vert_stretch = 0;
+ CARD32 crtc_h_total_disp = 0, crtc_v_total_disp = 0;
+ CARD32 crtc_h_sync_strt_wid = 0, crtc_v_sync_strt_wid = 0;
/* Chipset */
from = X_PROBED;
@@ -935,21 +946,46 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
"BIOS at 0x%08lx\n", info->BIOSAddr);
}
- /* RAM */
- from = X_PROBED;
+ /* Flat panel (part 1) */
+ /* FIXME: Make this an option */
+ switch (info->Chipset) {
+ case PCI_CHIP_RAGE128LE:
+ case PCI_CHIP_RAGE128LF: info->HasPanelRegs = TRUE; break;
+ case PCI_CHIP_RAGE128RE:
+ case PCI_CHIP_RAGE128RF:
+ case PCI_CHIP_RAGE128RK:
+ case PCI_CHIP_RAGE128RL:
+ case PCI_CHIP_RAGE128PF:
+ default: info->HasPanelRegs = FALSE; break;
+ }
+
+ /* Read registers used to determine options */
+ from = X_PROBED;
R128MapMMIO(pScrn);
- R128MMIO = info->MMIO;
+ R128MMIO = info->MMIO;
if (info->FBDev)
- pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024;
+ pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024;
else
- pScrn->videoRam = INREG(R128_CONFIG_MEMSIZE) / 1024;
- info->MemCntl = INREG(R128_MEM_CNTL);
- info->BusCntl = INREG(R128_BUS_CNTL);
- R128MMIO = NULL;
+ pScrn->videoRam = INREG(R128_CONFIG_MEMSIZE) / 1024;
+ info->MemCntl = INREG(R128_MEM_CNTL);
+ info->BusCntl = INREG(R128_BUS_CNTL);
+ if (info->HasPanelRegs) {
+ fp_horz_stretch = INREG(R128_FP_HORZ_STRETCH);
+ fp_vert_stretch = INREG(R128_FP_VERT_STRETCH);
+ crtc_h_total_disp = INREG(R128_CRTC_H_TOTAL_DISP);
+ crtc_v_total_disp = INREG(R128_CRTC_V_TOTAL_DISP);
+ crtc_h_sync_strt_wid = INREG(R128_CRTC_H_SYNC_STRT_WID);
+ crtc_v_sync_strt_wid = INREG(R128_CRTC_V_SYNC_STRT_WID);
+ }
+ R128MMIO = NULL;
R128UnmapMMIO(pScrn);
+
+ /* RAM */
switch (info->MemCntl & 0x3) {
case 0: /* SDR SGRAM 1:1 */
switch (info->Chipset) {
+ case PCI_CHIP_RAGE128LE:
+ case PCI_CHIP_RAGE128LF:
case PCI_CHIP_RAGE128RE:
case PCI_CHIP_RAGE128RF: offset = 0; break; /* 128-bit SDR SGRAM 1:1 */
case PCI_CHIP_RAGE128RK:
@@ -975,6 +1011,72 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, from,
"VideoRAM: %d kByte (%s)\n", pScrn->videoRam, info->ram->name);
+ /* Flat panel (part 2) */
+ if ((info->EnableFP = xf86ReturnOptValBool(R128Options,
+ OPTION_ENABLE_FP, FALSE))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Enabling use of flat panel registers\n");
+ if ((info->CRTOnly = xf86ReturnOptValBool(R128Options,
+ OPTION_CRT, FALSE))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Using external CRT instead of "
+ "flat panel for display\n");
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Using flat panel for display\n");
+ }
+ }
+
+ if (info->HasPanelRegs) {
+ int tmp;
+
+ info->PanelXRes =
+ (fp_horz_stretch & R128_HORZ_PANEL_SIZE) >> R128_HORZ_PANEL_SHIFT;
+ info->PanelXRes = (info->PanelXRes + 1) * 8;
+ info->PanelYRes =
+ (fp_vert_stretch & R128_VERT_PANEL_SIZE) >> R128_VERT_PANEL_SHIFT;
+ info->PanelYRes += 1;
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel dimensions: %dx%d\n",
+ info->PanelXRes, info->PanelYRes);
+
+ info->PanelHNonVis =
+ (crtc_h_total_disp & R128_CRTC_H_TOTAL) >> R128_CRTC_H_TOTAL_SHIFT;
+ info->PanelHNonVis += 4; /* Add 4 since we are in VGA mode */
+ tmp =
+ (crtc_h_total_disp & R128_CRTC_H_DISP) >> R128_CRTC_H_DISP_SHIFT;
+ info->PanelHNonVis -= tmp;
+ info->PanelHOverPlus =
+ (crtc_h_sync_strt_wid & R128_CRTC_H_SYNC_STRT_CHAR)
+ >> R128_CRTC_H_SYNC_STRT_CHAR_SHIFT;
+ info->PanelHOverPlus -= tmp;
+ switch (info->pixel_code) { /* Adjustments are from ATI */
+ case 8: info->PanelHOverPlus += 2; break;
+ case 15:
+ case 16: info->PanelHOverPlus += 1; break;
+ case 24:
+ case 32: info->PanelHOverPlus += 0; break;
+ }
+ info->PanelHSyncWidth =
+ (crtc_h_sync_strt_wid & R128_CRTC_H_SYNC_WID)
+ >> R128_CRTC_H_SYNC_WID_SHIFT;
+ info->PanelHSyncWidth += 14; /* ??? */
+
+ info->PanelVNonVis =
+ (crtc_v_total_disp & R128_CRTC_V_TOTAL) >> R128_CRTC_V_TOTAL_SHIFT;
+ info->PanelVNonVis += 1; /* Add 1 since we are in VGA mode */
+ tmp =
+ (crtc_v_total_disp & R128_CRTC_V_DISP) >> R128_CRTC_V_DISP_SHIFT;
+ info->PanelVNonVis -= tmp;
+ info->PanelVOverPlus =
+ (crtc_v_sync_strt_wid & R128_CRTC_V_SYNC_STRT)
+ >> R128_CRTC_V_SYNC_STRT_SHIFT;
+ info->PanelVOverPlus -= tmp + 1;
+ info->PanelVSyncWidth =
+ (crtc_v_sync_strt_wid & R128_CRTC_V_SYNC_WID)
+ >> R128_CRTC_V_SYNC_WID_SHIFT;
+ info->PanelVSyncWidth -= 2; /* ??? */
+ }
+
#ifdef XF86DRI
/* AGP/PCI */
if (xf86ReturnOptValBool(R128Options, OPTION_IS_PCI, FALSE)) {
@@ -982,8 +1084,10 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI-only mode\n");
} else {
switch (info->Chipset) {
+ case PCI_CHIP_RAGE128LE:
case PCI_CHIP_RAGE128RE:
case PCI_CHIP_RAGE128RK: info->IsPCI = TRUE; break;
+ case PCI_CHIP_RAGE128LF:
case PCI_CHIP_RAGE128RF:
case PCI_CHIP_RAGE128RL:
case PCI_CHIP_RAGE128PF:
@@ -991,6 +1095,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn)
}
}
#endif
+
return TRUE;
}
@@ -1862,6 +1967,24 @@ static void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
OUTREG(R128_CRTC_PITCH, restore->crtc_pitch);
}
+/* Write flat panel registers */
+static void R128RestoreFPRegisters(ScrnInfoPtr pScrn, R128SavePtr restore)
+{
+ R128MMIO_VARS();
+
+ OUTREG(R128_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
+ OUTREG(R128_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
+ OUTREG(R128_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
+ OUTREG(R128_FP_GEN_CNTL, restore->fp_gen_cntl);
+ OUTREG(R128_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
+ OUTREG(R128_FP_HORZ_STRETCH, restore->fp_horz_stretch);
+ OUTREG(R128_FP_PANEL_CNTL, restore->fp_panel_cntl);
+ OUTREG(R128_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
+ OUTREG(R128_FP_VERT_STRETCH, restore->fp_vert_stretch);
+ OUTREG(R128_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
+ OUTREG(R128_TMDS_CRC, restore->tmds_crc);
+}
+
static void R128PLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn)
{
while (INPLL(pScrn, R128_PPLL_REF_DIV) & R128_PPLL_ATOMIC_UPDATE_R);
@@ -1945,6 +2068,8 @@ static void R128RestoreMode(ScrnInfoPtr pScrn, R128SavePtr restore)
R128TRACE(("R128RestoreMode(%p)\n", restore));
R128RestoreCommonRegisters(pScrn, restore);
R128RestoreCrtcRegisters(pScrn, restore);
+ if (R128PTR(pScrn)->HasPanelRegs && R128PTR(pScrn)->EnableFP)
+ R128RestoreFPRegisters(pScrn, restore);
R128RestorePLLRegisters(pScrn, restore);
R128RestoreDDARegisters(pScrn, restore);
R128RestorePalette(pScrn, restore);
@@ -1987,6 +2112,24 @@ static void R128SaveCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr save)
save->crtc_pitch = INREG(R128_CRTC_PITCH);
}
+/* Read flat panel registers */
+static void R128SaveFPRegisters(ScrnInfoPtr pScrn, R128SavePtr save)
+{
+ R128MMIO_VARS();
+
+ save->crtc2_gen_cntl = INREG(R128_CRTC2_GEN_CNTL);
+ save->fp_crtc_h_total_disp = INREG(R128_FP_CRTC_H_TOTAL_DISP);
+ save->fp_crtc_v_total_disp = INREG(R128_FP_CRTC_V_TOTAL_DISP);
+ save->fp_gen_cntl = INREG(R128_FP_GEN_CNTL);
+ save->fp_h_sync_strt_wid = INREG(R128_FP_H_SYNC_STRT_WID);
+ save->fp_horz_stretch = INREG(R128_FP_HORZ_STRETCH);
+ save->fp_panel_cntl = INREG(R128_FP_PANEL_CNTL);
+ save->fp_v_sync_strt_wid = INREG(R128_FP_V_SYNC_STRT_WID);
+ save->fp_vert_stretch = INREG(R128_FP_VERT_STRETCH);
+ save->lvds_gen_cntl = INREG(R128_LVDS_GEN_CNTL);
+ save->tmds_crc = INREG(R128_TMDS_CRC);
+}
+
/* Read PLL registers. */
static void R128SavePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr save)
{
@@ -2031,6 +2174,8 @@ static void R128SaveMode(ScrnInfoPtr pScrn, R128SavePtr save)
R128SaveCommonRegisters(pScrn, save);
R128SaveCrtcRegisters(pScrn, save);
+ if (R128PTR(pScrn)->HasPanelRegs && R128PTR(pScrn)->EnableFP)
+ R128SaveFPRegisters(pScrn, save);
R128SavePLLRegisters(pScrn, save);
R128SaveDDARegisters(pScrn, save);
R128SavePalette(pScrn, save);
@@ -2205,6 +2350,127 @@ static Bool R128InitCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr save,
return TRUE;
}
+/* Define CRTC registers for requested video mode. */
+static void R128InitFPRegisters(ScrnInfoPtr pScrn, R128SavePtr orig,
+ R128SavePtr save, DisplayModePtr mode,
+ R128InfoPtr info)
+{
+ int xres = mode->CrtcHDisplay;
+ int yres = mode->CrtcVDisplay;
+ float Hratio, Vratio;
+ int disp_end;
+
+ if (info->CRTOnly) {
+ save->crtc_ext_cntl |= R128_CRTC_CRT_ON;
+ save->crtc2_gen_cntl = 0;
+ save->fp_gen_cntl = orig->fp_gen_cntl;
+ save->fp_gen_cntl &= ~(R128_FP_FPON |
+ R128_FP_CRTC_USE_SHADOW_VEND |
+ R128_FP_CRTC_HORZ_DIV2_EN |
+ R128_FP_CRTC_HOR_CRT_DIV2_DIS |
+ R128_FP_USE_SHADOW_EN);
+ save->fp_gen_cntl |= (R128_FP_SEL_CRTC2 |
+ R128_FP_CRTC_DONT_SHADOW_VPAR);
+ save->fp_panel_cntl = orig->fp_panel_cntl & ~R128_FP_DIGON;
+ save->lvds_gen_cntl = orig->lvds_gen_cntl & ~R128_LVDS_ON;
+ return;
+ }
+
+ if (xres > info->PanelXRes) xres = info->PanelXRes;
+ if (yres > info->PanelYRes) yres = info->PanelYRes;
+
+ Hratio = (float)xres/(float)info->PanelXRes;
+ Vratio = (float)yres/(float)info->PanelYRes;
+
+ save->fp_horz_stretch =
+ (((((int)(Hratio * R128_HORZ_STRETCH_RATIO_MAX))
+ & R128_HORZ_STRETCH_RATIO_MASK) << R128_HORZ_STRETCH_RATIO_SHIFT) |
+ (orig->fp_horz_stretch & (R128_HORZ_PANEL_SIZE |
+ R128_HORZ_FP_LOOP_STRETCH |
+ R128_HORZ_STRETCH_RESERVED)));
+ if (Hratio != 1.0) save->fp_horz_stretch |= (R128_HORZ_STRETCH_BLEND |
+ R128_HORZ_STRETCH_ENABLE);
+
+ save->fp_vert_stretch =
+ (((((int)(Vratio * R128_VERT_STRETCH_RATIO_MAX))
+ & R128_VERT_STRETCH_RATIO_MASK) << R128_VERT_STRETCH_RATIO_SHIFT) |
+ (orig->fp_vert_stretch & (R128_VERT_PANEL_SIZE |
+ R128_VERT_STRETCH_RESERVED |
+ R128_VERT_STRETCH_BLEND)));
+ if (Vratio == 1.0) save->fp_vert_stretch &= ~R128_VERT_STRETCH_ENABLE;
+ else save->fp_vert_stretch |= R128_VERT_STRETCH_ENABLE;
+
+ save->fp_gen_cntl = ((orig->fp_gen_cntl & ~(R128_FP_SEL_CRTC2 |
+ R128_FP_CRTC_USE_SHADOW_VEND |
+ R128_FP_CRTC_HORZ_DIV2_EN |
+ R128_FP_CRTC_HOR_CRT_DIV2_DIS |
+ R128_FP_USE_SHADOW_EN)) |
+ R128_FP_CRTC_DONT_SHADOW_VPAR |
+ R128_FP_TDMS_EN);
+ save->fp_panel_cntl = orig->fp_panel_cntl;
+ save->fp_crtc_h_total_disp = orig->fp_crtc_h_total_disp;
+ save->fp_crtc_v_total_disp = orig->fp_crtc_v_total_disp;
+ save->fp_h_sync_strt_wid = orig->fp_h_sync_strt_wid;
+ save->fp_v_sync_strt_wid = orig->fp_v_sync_strt_wid;
+ save->lvds_gen_cntl = orig->lvds_gen_cntl;
+
+ save->tmds_crc = orig->tmds_crc;
+
+ /* Disable CRT output by disabling CRT output and setting the CRT
+ DAC to use CRTC2, which we set to 0's. In the future, we will
+ want to use the dual CRTC capabilities of the R128 to allow both
+ the flat panel and external CRT to either simultaneously display
+ the same image or display two different images. */
+ save->crtc_ext_cntl &= ~R128_CRTC_CRT_ON;
+ save->dac_cntl |= R128_DAC_CRT_SEL_CRTC2;
+ save->crtc2_gen_cntl = 0;
+
+ save->fp_panel_cntl |= (R128_FP_DIGON | R128_FP_BLON);
+ save->fp_gen_cntl |= (R128_FP_FPON);
+
+ save->crtc_gen_cntl &= ~(R128_CRTC_DBL_SCAN_EN |
+ R128_CRTC_INTERLACE_EN |
+ R128_CRTC_CSYNC_EN |
+ R128_CRTC_CUR_EN |
+ R128_CRTC_CUR_MODE_MASK |
+ R128_CRTC_ICON_EN |
+ R128_CRTC_EXT_DISP_EN |
+ R128_CRTC_EN |
+ R128_CRTC_DISP_REQ_EN_B);
+ save->crtc_gen_cntl |= R128_CRTC_EXT_DISP_EN | R128_CRTC_EN;
+
+ disp_end = xres/8 - 1;
+ save->crtc_h_total_disp = ((disp_end << R128_CRTC_H_DISP_SHIFT) |
+ (disp_end + info->PanelHNonVis));
+
+ save->crtc_h_sync_strt_wid &= ~(R128_CRTC_H_SYNC_STRT_PIX |
+ R128_CRTC_H_SYNC_STRT_CHAR |
+ R128_CRTC_H_SYNC_WID);
+ save->crtc_h_sync_strt_wid |=
+ (disp_end + info->PanelHOverPlus) << R128_CRTC_H_SYNC_STRT_CHAR_SHIFT;
+ switch (info->pixel_code) { /* Adjustments are from ATI */
+ case 8: save->crtc_h_sync_strt_wid |= 2; break;
+ case 15:
+ case 16: save->crtc_h_sync_strt_wid |= 1; break;
+ case 24: save->crtc_h_sync_strt_wid |= 6; break;
+ case 32: save->crtc_h_sync_strt_wid |= 5; break;
+ }
+ save->crtc_h_sync_strt_wid |=
+ info->PanelHSyncWidth << R128_CRTC_H_SYNC_WID_SHIFT;
+ save->crtc_h_sync_strt_wid |= R128_CRTC_H_SYNC_POL;
+
+ disp_end = yres - 1;
+ save->crtc_v_total_disp = ((disp_end << R128_CRTC_V_DISP_SHIFT) |
+ (disp_end + info->PanelVNonVis));
+
+ save->crtc_v_sync_strt_wid &= ~(R128_CRTC_V_SYNC_STRT |
+ R128_CRTC_V_SYNC_WID);
+ save->crtc_v_sync_strt_wid |= (disp_end + info->PanelVOverPlus);
+ save->crtc_v_sync_strt_wid |=
+ info->PanelVSyncWidth << R128_CRTC_V_SYNC_WID_SHIFT;
+ save->crtc_v_sync_strt_wid |= R128_CRTC_V_SYNC_POL;
+}
+
/* Define PLL registers for requested video mode. */
static void R128InitPLLRegisters(ScrnInfoPtr pScrn, R128SavePtr save,
DisplayModePtr mode, R128PLLPtr pll,
@@ -2386,6 +2652,8 @@ static Bool R128Init(ScrnInfoPtr pScrn, DisplayModePtr mode, R128SavePtr save)
R128InitCommonRegisters(save, mode, info);
if (!R128InitCrtcRegisters(pScrn, save, mode, info)) return FALSE;
+ if (info->HasPanelRegs && info->EnableFP)
+ R128InitFPRegisters(pScrn, &info->SavedReg, save, mode, info);
R128InitPLLRegisters(pScrn, save, mode, &info->pll, dot_clock);
if (!R128InitDDARegisters(pScrn, save, mode, &info->pll, info))
return FALSE;
diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h
index 144fd9efe..17a539e76 100644
--- a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h
+++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h
@@ -332,6 +332,7 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l
# define R128_CRTC_HSYNC_DIS (1 << 8)
# define R128_CRTC_VSYNC_DIS (1 << 9)
# define R128_CRTC_DISPLAY_DIS (1 << 10)
+# define R128_CRTC_CRT_ON (1 << 15)
#define R128_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
# define R128_CRTC_HSYNC_DIS_BYTE (1 << 0)
# define R128_CRTC_VSYNC_DIS_BYTE (1 << 1)
@@ -339,24 +340,57 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l
#define R128_CRTC_GEN_CNTL 0x0050
# define R128_CRTC_DBL_SCAN_EN (1 << 0)
# define R128_CRTC_INTERLACE_EN (1 << 1)
+# define R128_CRTC_CSYNC_EN (1 << 4)
# define R128_CRTC_CUR_EN (1 << 16)
# define R128_CRTC_CUR_MODE_MASK (7 << 17)
+# define R128_CRTC_ICON_EN (1 << 20)
# define R128_CRTC_EXT_DISP_EN (1 << 24)
# define R128_CRTC_EN (1 << 25)
+# define R128_CRTC_DISP_REQ_EN_B (1 << 26)
#define R128_CRTC_GUI_TRIG_VLINE 0x0218
#define R128_CRTC_H_SYNC_STRT_WID 0x0204
-# define R128_CRTC_H_SYNC_POL (1 << 23)
+# define R128_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
+# define R128_CRTC_H_SYNC_STRT_CHAR (0x1ff << 3)
+# define R128_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
+# define R128_CRTC_H_SYNC_WID (0x3f << 16)
+# define R128_CRTC_H_SYNC_WID_SHIFT 16
+# define R128_CRTC_H_SYNC_POL (1 << 23)
#define R128_CRTC_H_TOTAL_DISP 0x0200
+# define R128_CRTC_H_TOTAL (0x01ff << 0)
+# define R128_CRTC_H_TOTAL_SHIFT 0
+# define R128_CRTC_H_DISP (0x00ff << 16)
+# define R128_CRTC_H_DISP_SHIFT 16
#define R128_CRTC_OFFSET 0x0224
#define R128_CRTC_OFFSET_CNTL 0x0228
#define R128_CRTC_PITCH 0x022c
#define R128_CRTC_STATUS 0x005c
# define R128_CRTC_VBLANK_SAVE (1 << 1)
#define R128_CRTC_V_SYNC_STRT_WID 0x020c
-# define R128_CRTC_V_SYNC_POL (1 << 23)
+# define R128_CRTC_V_SYNC_STRT (0x7ff << 0)
+# define R128_CRTC_V_SYNC_STRT_SHIFT 0
+# define R128_CRTC_V_SYNC_WID (0x1f << 16)
+# define R128_CRTC_V_SYNC_WID_SHIFT 16
+# define R128_CRTC_V_SYNC_POL (1 << 23)
#define R128_CRTC_V_TOTAL_DISP 0x0208
+# define R128_CRTC_V_TOTAL (0x07ff << 0)
+# define R128_CRTC_V_TOTAL_SHIFT 0
+# define R128_CRTC_V_DISP (0x07ff << 16)
+# define R128_CRTC_V_DISP_SHIFT 16
#define R128_CRTC_VLINE_CRNT_VLINE 0x0210
# define R128_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
+#define R128_CRTC2_CRNT_FRAME 0x0314
+#define R128_CRTC2_DEBUG 0x031c
+#define R128_CRTC2_GEN_CNTL 0x03f8
+#define R128_CRTC2_GUI_TRIG_VLINE 0x0318
+#define R128_CRTC2_H_SYNC_STRT_WID 0x0304
+#define R128_CRTC2_H_TOTAL_DISP 0x0300
+#define R128_CRTC2_OFFSET 0x0324
+#define R128_CRTC2_OFFSET_CNTL 0x0328
+#define R128_CRTC2_PITCH 0x032c
+#define R128_CRTC2_STATUS 0x03fc
+#define R128_CRTC2_V_SYNC_STRT_WID 0x030c
+#define R128_CRTC2_V_TOTAL_DISP 0x0308
+#define R128_CRTC2_VLINE_CRNT_VLINE 0x0310
#define R128_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
#define R128_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
#define R128_CUR_CLR0 0x026c
@@ -369,6 +403,7 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l
#define R128_DAC_CNTL 0x0058
# define R128_DAC_RANGE_CNTL (3 << 0)
# define R128_DAC_BLANKING (1 << 2)
+# define R128_DAC_CRT_SEL_CRTC2 (1 << 4)
# define R128_DAC_8BIT_EN (1 << 8)
# define R128_DAC_VGA_ADR_EN (1 << 13)
# define R128_DAC_MASK_ALL (0xff << 24)
@@ -384,11 +419,6 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l
#define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
# define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
# define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
-#define R128_FOG_3D_TABLE_START 0x1810
-#define R128_FOG_3D_TABLE_END 0x1814
-#define R128_FOG_3D_TABLE_DENSITY 0x181c
-#define R128_FOG_TABLE_INDEX 0x1a14
-#define R128_FOG_TABLE_DATA 0x1a18
#define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820
#define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824
#define R128_DEVICE_ID 0x0f02 /* PCI */
@@ -524,6 +554,49 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l
#define R128_FLUSH_5 0x1714
#define R128_FLUSH_6 0x1718
#define R128_FLUSH_7 0x171c
+#define R128_FOG_3D_TABLE_START 0x1810
+#define R128_FOG_3D_TABLE_END 0x1814
+#define R128_FOG_3D_TABLE_DENSITY 0x181c
+#define R128_FOG_TABLE_INDEX 0x1a14
+#define R128_FOG_TABLE_DATA 0x1a18
+#define R128_FP_CRTC_H_TOTAL_DISP 0x0250
+#define R128_FP_CRTC_V_TOTAL_DISP 0x0254
+#define R128_FP_GEN_CNTL 0x0284
+# define R128_FP_FPON (1 << 0)
+# define R128_FP_TDMS_EN (1 << 2)
+# define R128_FP_SEL_CRTC2 (1 << 13)
+# define R128_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
+# define R128_FP_CRTC_USE_SHADOW_VEND (1 << 18)
+# define R128_FP_CRTC_HORZ_DIV2_EN (1 << 20)
+# define R128_FP_CRTC_HOR_CRT_DIV2_DIS (1 << 21)
+# define R128_FP_USE_SHADOW_EN (1 << 24)
+#define R128_FP_H_SYNC_STRT_WID 0x02c4
+#define R128_FP_HORZ_STRETCH 0x028c
+# define R128_HORZ_STRETCH_RATIO_MASK 0xffff
+# define R128_HORZ_STRETCH_RATIO_SHIFT 0
+# define R128_HORZ_STRETCH_RATIO_MAX 4096
+# define R128_HORZ_PANEL_SIZE (0xff << 16)
+# define R128_HORZ_PANEL_SHIFT 16
+# define R128_HORZ_STRETCH_PIXREP (0 << 25)
+# define R128_HORZ_STRETCH_BLEND (1 << 25)
+# define R128_HORZ_STRETCH_ENABLE (1 << 26)
+# define R128_HORZ_FP_LOOP_STRETCH (0x7 << 27)
+# define R128_HORZ_STRETCH_RESERVED 0xc0000000
+
+#define R128_FP_PANEL_CNTL 0x0288
+# define R128_FP_DIGON (1 << 0)
+# define R128_FP_BLON (1 << 1)
+#define R128_FP_V_SYNC_STRT_WID 0x02c8
+#define R128_FP_VERT_STRETCH 0x0290
+# define R128_VERT_PANEL_SIZE (0x7ff << 0)
+# define R128_VERT_PANEL_SHIFT 0
+# define R128_VERT_STRETCH_RATIO_MASK 0x3ff
+# define R128_VERT_STRETCH_RATIO_SHIFT 11
+# define R128_VERT_STRETCH_RATIO_MAX 1024
+# define R128_VERT_STRETCH_ENABLE (1 << 24)
+# define R128_VERT_STRETCH_LINEREP (0 << 25)
+# define R128_VERT_STRETCH_BLEND (1 << 25)
+# define R128_VERT_STRETCH_RESERVED 0xf8e00000
#define R128_GEN_INT_CNTL 0x0040
#define R128_GEN_INT_STATUS 0x0044
@@ -601,6 +674,9 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l
#define R128_LEAD_BRES_INC 0x1604
#define R128_LEAD_BRES_LNTH 0x161c
#define R128_LEAD_BRES_LNTH_SUB 0x1624
+#define R128_LVDS_GEN_CNTL 0x02d0
+# define R128_LVDS_ON (1 << 0)
+# define R128_LVDS_SEL_CRTC2 (1 << 23)
#define R128_MAX_LATENCY 0x0f3f /* PCI */
#define R128_MCLK_CNTL 0x000f /* PLL */
@@ -718,11 +794,13 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l
#define R128_TEST_DEBUG_CNTL 0x0120
#define R128_TEST_DEBUG_MUX 0x0124
#define R128_TEST_DEBUG_OUT 0x012c
+#define R128_TMDS_CRC 0x02a0
#define R128_TRAIL_BRES_DEC 0x1614
#define R128_TRAIL_BRES_ERR 0x160c
#define R128_TRAIL_BRES_INC 0x1610
#define R128_TRAIL_X 0x1618
#define R128_TRAIL_X_SUB 0x1620
+
#define R128_VCLK_ECP_CNTL 0x0008 /* PLL */
#define R128_VENDOR_ID 0x0f00 /* PCI */
#define R128_VGA_DDA_CONFIG 0x02e8
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 00:03:00 +0000