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Diffstat (limited to 'xc/programs/Xserver/hw/xfree86/ramdac/TI.c')
-rw-r--r--xc/programs/Xserver/hw/xfree86/ramdac/TI.c331
1 files changed, 238 insertions, 93 deletions
diff --git a/xc/programs/Xserver/hw/xfree86/ramdac/TI.c b/xc/programs/Xserver/hw/xfree86/ramdac/TI.c
index 498df080b..c34ca1e89 100644
--- a/xc/programs/Xserver/hw/xfree86/ramdac/TI.c
+++ b/xc/programs/Xserver/hw/xfree86/ramdac/TI.c
@@ -22,9 +22,9 @@
* Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
*
* Modified from IBM.c to support TI RAMDAC routines
- * by Jens Owen, <jens@precisioninsight.com>.
+ * by Jens Owen, <jens@tungstengraphics.com>.
*/
-/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/TI.c,v 1.1 1999/06/14 07:32:08 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/ramdac/TI.c,v 1.5 2000/05/02 21:04:46 alanh Exp $ */
#include "xf86.h"
#include "xf86_OSproc.h"
@@ -71,7 +71,7 @@ TIramdacCalculateMNPForClock(
* we don't have to bother checking for this maximum limit.
*/
VCO = (double)ReqClock;
- for ( p = *rP; p < 3 && VCO < TI_MIN_VCO_FREQ; ( p )++ )
+ for ( p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; ( p )++ )
VCO *= 2.0;
/*
@@ -158,55 +158,55 @@ TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
/* only restore clocks if they were valid to begin with */
if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
- /* Reset pixel clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0, 0x3c);
+ /* Reset pixel clock */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0, 0x3c);
- /* Restore N, M & P values for pixel clocks */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
+ /* Restore N, M & P values for pixel clocks */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
ramdacReg->DacRegs[TIDAC_PIXEL_N]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
ramdacReg->DacRegs[TIDAC_PIXEL_M]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
ramdacReg->DacRegs[TIDAC_PIXEL_P]);
- /* wait for pixel clock to lock */
- i = 1000000;
- do {
- status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- } while ((!(status & 0x40)) && (--i));
- if (!(status & 0x40)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ /* wait for pixel clock to lock */
+ i = 1000000;
+ do {
+ status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
+ } while ((!(status & 0x40)) && (--i));
+ if (!(status & 0x40)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Pixel clock setup timed out\n");
- return;
- }
+ return;
+ }
}
if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
- /* Reset loop clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0, 0x70);
+ /* Reset loop clock */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0, 0x70);
- /* Restore N, M & P values for pixel clocks */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
+ /* Restore N, M & P values for pixel clocks */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
ramdacReg->DacRegs[TIDAC_LOOP_N]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
ramdacReg->DacRegs[TIDAC_LOOP_M]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
ramdacReg->DacRegs[TIDAC_LOOP_P]);
- /* wait for loop clock to lock */
- i = 1000000;
- do {
- status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- } while ((!(status & 0x40)) && (--i));
- if (!(status & 0x40)) {
+ /* wait for loop clock to lock */
+ i = 1000000;
+ do {
+ status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
+ } while ((!(status & 0x40)) && (--i));
+ if (!(status & 0x40)) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Loop clock setup timed out\n");
return;
- }
+ }
}
/* restore palette */
@@ -228,38 +228,32 @@ TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
RamDacRegRecPtr ramdacReg)
{
int i;
- unsigned long status;
(*ramdacPtr->ReadAddress)(pScrn, 0);
for (i=0;i<768;i++)
ramdacReg->DAC[i] = (*ramdacPtr->ReadData)(pScrn);
- if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
- /* Read back N,M and P values for pixel clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- ramdacReg->DacRegs[TIDAC_PIXEL_N] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
- ramdacReg->DacRegs[TIDAC_PIXEL_M] =
+ /* Read back N,M and P values for pixel clock */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
+ ramdacReg->DacRegs[TIDAC_PIXEL_N] =
+ (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
+ ramdacReg->DacRegs[TIDAC_PIXEL_M] =
+ (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
+ ramdacReg->DacRegs[TIDAC_PIXEL_P] =
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- ramdacReg->DacRegs[TIDAC_PIXEL_P] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x33);
- }
- if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
- /* Read back N,M and P values for loop clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- ramdacReg->DacRegs[TIDAC_LOOP_N] =
+
+ /* Read back N,M and P values for loop clock */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
+ ramdacReg->DacRegs[TIDAC_LOOP_N] =
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
- ramdacReg->DacRegs[TIDAC_LOOP_M] =
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
+ ramdacReg->DacRegs[TIDAC_LOOP_M] =
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- ramdacReg->DacRegs[TIDAC_LOOP_P] =
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
+ ramdacReg->DacRegs[TIDAC_LOOP_P] =
(*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x33);
- }
/* Order is important */
TISAVE(TIDAC_latch_ctrl);
@@ -285,7 +279,7 @@ TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
}
RamDacHelperRecPtr
-TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs/* , RamDacRecPtr ramdacPtr*/)
+TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs)
{
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
RamDacHelperRecPtr ramdacHelperPtr = NULL;
@@ -309,6 +303,10 @@ TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs/* , RamDacRec
if (id == id2 && rev == rev2) /* check for READ ONLY */
TIramdac_ID = TI3030_RAMDAC;
break;
+ case TIDAC_TVP_3026_ID:
+ if (id == id2 && rev == rev2) /* check for READ ONLY */
+ TIramdac_ID = TI3026_RAMDAC;
+ break;
}
(*ramdacPtr->WriteDAC)(pScrn, rev, 0, TIDAC_rev);
@@ -338,7 +336,11 @@ TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs/* , RamDacRec
switch (TIramdac_ID) {
case TI3030_RAMDAC:
ramdacHelperPtr->SetBpp = TIramdac3030SetBpp;
- ramdacHelperPtr->HWCursorInit = TIramdac3030HWCursorInit;
+ ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
+ break;
+ case TI3026_RAMDAC:
+ ramdacHelperPtr->SetBpp = TIramdac3026SetBpp;
+ ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
break;
}
ramdacPtr->RamDacType = TIramdac_ID;
@@ -350,14 +352,14 @@ TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs/* , RamDacRec
}
void
-TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
+TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
{
switch (pScrn->bitsPerPixel) {
case 32:
/* order is important */
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
@@ -373,7 +375,7 @@ TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- if (ramdacReg->Overlay) {
+ if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
@@ -404,7 +406,7 @@ TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
break;
case 16:
/* order is important */
-#ifdef NOT_DONE
+#if 0
/* Matrox driver uses this */
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
#else
@@ -415,20 +417,19 @@ TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
} else {
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
}
-#ifdef NOT_DONE
+#if 0
/* Matrox driver uses this */
ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
#else
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
#endif
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
/* 0x2A & 0x2B are reserved */
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
@@ -446,21 +447,106 @@ TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
/* order is important */
ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
-#ifdef NOT_DONE
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x48;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ }
+}
+
+void
+TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
+{
+ switch (pScrn->bitsPerPixel) {
+ case 32:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
+ }
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 24:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 16:
+ /* order is important */
+#if 0
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
#else
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
#endif
+ if (pScrn->depth == 16) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
+ } else {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
+ }
+#if 0
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
-#ifdef NOT_DONE
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x0C;
#else
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
#endif
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
/* 0x2A & 0x2B are reserved */
ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
@@ -470,6 +556,28 @@ TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 8:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
@@ -478,25 +586,25 @@ TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
}
void
-TIramdac3030ShowCursor(ScrnInfoPtr pScrn)
+TIramdacShowCursor(ScrnInfoPtr pScrn)
{
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
/* Enable cursor - X11 mode */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0x6c, 0x13);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x03);
}
void
-TIramdac3030HideCursor(ScrnInfoPtr pScrn)
+TIramdacHideCursor(ScrnInfoPtr pScrn)
{
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
/* Disable cursor - X11 mode */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0xfc, 0x00);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
}
void
-TIramdac3030SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
+TIramdacSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
{
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
@@ -510,7 +618,7 @@ TIramdac3030SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
}
void
-TIramdac3030SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
+TIramdacSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
{
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
@@ -528,17 +636,16 @@ TIramdac3030SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
}
void
-TIramdac3030LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
+TIramdacLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
{
RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
int i = 1024;
-int j = 16;
/* reset A9,A8 */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0xf3, 0x00);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
/* reset cursor RAM load address A7..A0 */
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_INDEX, 0x00, 0x00);
-
+
while(i--) {
/* NOT_DONE: might need a delay here */
(*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++));
@@ -546,23 +653,61 @@ int j = 16;
}
static Bool
-TIramdac3030UseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
+TIramdacUseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
{
return TRUE;
}
void
-TIramdac3030HWCursorInit(xf86CursorInfoPtr infoPtr)
+TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr)
{
infoPtr->MaxWidth = 64;
infoPtr->MaxHeight = 64;
infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
- infoPtr->SetCursorColors = TIramdac3030SetCursorColors;
- infoPtr->SetCursorPosition = TIramdac3030SetCursorPosition;
- infoPtr->LoadCursorImage = TIramdac3030LoadCursorImage;
- infoPtr->HideCursor = TIramdac3030HideCursor;
- infoPtr->ShowCursor = TIramdac3030ShowCursor;
- infoPtr->UseHWCursor = TIramdac3030UseHWCursor;
+ infoPtr->SetCursorColors = TIramdacSetCursorColors;
+ infoPtr->SetCursorPosition = TIramdacSetCursorPosition;
+ infoPtr->LoadCursorImage = TIramdacLoadCursorImage;
+ infoPtr->HideCursor = TIramdacHideCursor;
+ infoPtr->ShowCursor = TIramdacShowCursor;
+ infoPtr->UseHWCursor = TIramdacUseHWCursor;
+}
+
+void TIramdacLoadPalette(
+ ScrnInfoPtr pScrn,
+ int numColors,
+ int *indices,
+ LOCO *colors,
+ VisualPtr pVisual
+){
+ RamDacRecPtr hwp = RAMDACSCRPTR(pScrn);
+ int i, index, shift;
+
+ if (pScrn->depth == 16) {
+ for(i = 0; i < numColors; i++) {
+ index = indices[i];
+ (*hwp->WriteAddress)(pScrn, index << 2);
+ (*hwp->WriteData)(pScrn, colors[index >> 1].red);
+ (*hwp->WriteData)(pScrn, colors[index].green);
+ (*hwp->WriteData)(pScrn, colors[index >> 1].blue);
+
+ if(index <= 31) {
+ (*hwp->WriteAddress)(pScrn, index << 3);
+ (*hwp->WriteData)(pScrn, colors[index].red);
+ (*hwp->WriteData)(pScrn, colors[(index << 1) + 1].green);
+ (*hwp->WriteData)(pScrn, colors[index].blue);
+ }
+ }
+} else {
+ shift = (pScrn->depth == 15) ? 3 : 0;
+
+ for(i = 0; i < numColors; i++) {
+ index = indices[i];
+ (*hwp->WriteAddress)(pScrn, index << shift);
+ (*hwp->WriteData)(pScrn, colors[index].red);
+ (*hwp->WriteData)(pScrn, colors[index].green);
+ (*hwp->WriteData)(pScrn, colors[index].blue);
+ }
+}
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-25 15:12:58 +0000