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path: root/xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c
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Diffstat (limited to 'xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c')
-rw-r--r--xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c106
1 files changed, 86 insertions, 20 deletions
diff --git a/xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c b/xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c
index c2cc94452..eaab5bb5b 100644
--- a/xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c
+++ b/xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c
@@ -27,7 +27,7 @@
* this work is sponsored by S.u.S.E. GmbH, Fuerth, Elsa GmbH, Aachen and
* Siemens Nixdorf Informationssysteme
*/
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c,v 1.8 1999/03/28 15:32:39 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/tx_dac.c,v 1.10 2000/05/10 18:55:30 alanh Exp $ */
#include "xf86.h"
#include "xf86_OSproc.h"
@@ -37,6 +37,7 @@
#include "xf86Pci.h"
#include "IBM.h"
+#include "TI.h"
#include "glint_regs.h"
#include "glint.h"
@@ -46,7 +47,8 @@ Shiftbpp(ScrnInfoPtr pScrn, int value)
GLINTPtr pGlint = GLINTPTR(pScrn);
int logbytesperaccess;
- if (pGlint->RamDac->RamDacType == (IBM640_RAMDAC))
+ if ( (pGlint->RamDac->RamDacType == (IBM640_RAMDAC)) ||
+ (pGlint->RamDac->RamDacType == (TI3030_RAMDAC)) )
logbytesperaccess = 4;
else
logbytesperaccess = 3;
@@ -91,11 +93,14 @@ TXInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
pReg->glintRegs[Aperture1 >> 3] = 0;
if (pGlint->UsePCIRetry) {
- pReg->glintRegs[DFIFODis >> 3] = 1;
- pReg->glintRegs[FIFODis >> 3] = 3;
+ pReg->glintRegs[DFIFODis >> 3] = GLINT_READ_REG(DFIFODis) | 0x01;
+ if (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_GAMMA)
+ pReg->glintRegs[FIFODis >> 3] = GLINT_READ_REG(FIFODis) | 0x01;
+ else
+ pReg->glintRegs[FIFODis >> 3] = GLINT_READ_REG(FIFODis) | 0x03;
} else {
- pReg->glintRegs[DFIFODis >> 3] = 0;
- pReg->glintRegs[FIFODis >> 3] = 1;
+ pReg->glintRegs[DFIFODis >> 3] = GLINT_READ_REG(DFIFODis) & 0xFFFFFFFE;
+ pReg->glintRegs[FIFODis >> 3] = GLINT_READ_REG(FIFODis) | 0x01;
}
temp1 = mode->CrtcHSyncStart - mode->CrtcHDisplay;
@@ -124,7 +129,7 @@ TXInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
* tell DAC to use the ICD chip clock 0 as ref clock
* and set up some more video timining generator registers
*/
- pReg->glintRegs[VTGSerialClk >> 3] = 0x05;
+ pReg->glintRegs[VTGSerialClk >> 3] = 0x05;
/* This is ugly */
if (pGlint->UseFireGL3000) {
@@ -141,6 +146,21 @@ TXInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
pReg->glintRegs[VTGModeCtl >> 3] = 0x44;
}
+ /* Override FBModeSel for 300SX chip */
+ if (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_300SX) {
+ switch (pScrn->bitsPerPixel) {
+ case 8:
+ pReg->glintRegs[FBModeSel >> 3] = 0x905;
+ break;
+ case 16:
+ pReg->glintRegs[FBModeSel >> 3] = 0x903;
+ break;
+ case 32:
+ pReg->glintRegs[FBModeSel >> 3] = 0x901;
+ break;
+ }
+ }
+
switch (pGlint->RamDac->RamDacType) {
case IBM526DB_RAMDAC:
case IBM526_RAMDAC:
@@ -208,6 +228,49 @@ TXInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
ramdacReg->DacRegs[RGB640_VRAM_MASK2] = 0x0F;
pReg->glintRegs[VTGModeCtl >> 3] = 0x04;
+ break;
+
+ case TI3026_RAMDAC:
+ case TI3030_RAMDAC:
+ {
+ /* Get the programmable clock values */
+ unsigned long m=0,n=0,p=0;
+ unsigned long clock;
+ int count;
+ unsigned long q, status, VCO;
+
+ clock = TIramdacCalculateMNPForClock(pGlint->RefClock,
+ mode->Clock, 1, pGlint->MinClock, pGlint->MaxClock, &m, &n, &p);
+
+ ramdacReg->DacRegs[TIDAC_PIXEL_N] = ((n & 0x3f) | 0xC0);
+ ramdacReg->DacRegs[TIDAC_PIXEL_M] = (m & 0x3f) ;
+ ramdacReg->DacRegs[TIDAC_PIXEL_P] = ((p & 0x03) | 0xbc);
+ ramdacReg->DacRegs[TIDAC_PIXEL_VALID] = TRUE;
+
+ if (pGlint->RamDac->RamDacType == (TI3026_RAMDAC))
+ n = 65 - ((64 << 2) / pScrn->bitsPerPixel);
+ else
+ n = 65 - ((128 << 2) / pScrn->bitsPerPixel);
+ m = 61;
+ p = 0;
+ for (q = 0; q < 8; q++) {
+ if (q > 0) p = 3;
+ for ( ; p < 4; p++) {
+ VCO = ((clock * (q + 1) * (65 - m)) / (65 - n)) << (p + 1);
+ if (VCO >= 110000) { break; }
+ }
+ if (VCO >= 110000) { break; }
+ }
+ ramdacReg->DacRegs[TIDAC_clock_ctrl] = (q | 0x38);
+
+ ramdacReg->DacRegs[TIDAC_LOOP_N] = ((n & 0x3f) | 0xC0);
+ ramdacReg->DacRegs[TIDAC_LOOP_M] = (m & 0x3f) ;
+ ramdacReg->DacRegs[TIDAC_LOOP_P] = ((p & 0x03) | 0xF0);
+ ramdacReg->DacRegs[TIDAC_LOOP_VALID] = TRUE;
+ }
+ if (pGlint->RamDac->RamDacType == (TI3030_RAMDAC))
+ pReg->glintRegs[VTGModeCtl >> 3] = 0x04;
+ break;
}
/* Now use helper routines to setup bpp for this driver */
@@ -224,8 +287,14 @@ TXSave(ScrnInfoPtr pScrn, GLINTRegPtr glintReg)
glintReg->glintRegs[Aperture0 >> 3] = GLINT_READ_REG(Aperture0);
glintReg->glintRegs[Aperture1 >> 3] = GLINT_READ_REG(Aperture1);
- glintReg->glintRegs[DFIFODis >> 3] = GLINT_READ_REG(DFIFODis);
- glintReg->glintRegs[FIFODis >> 3] = GLINT_READ_REG(FIFODis);
+ if ((pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_DELTA) ||
+ (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_GAMMA))
+ glintReg->glintRegs[DFIFODis >> 3] = GLINT_READ_REG(DFIFODis);
+
+ if (pGlint->Chipset != PCI_VENDOR_3DLABS_CHIP_300SX) {
+ glintReg->glintRegs[FIFODis >> 3] = GLINT_READ_REG(FIFODis);
+ glintReg->glintRegs[VTGModeCtl >> 3] = GLINT_READ_REG(VTGModeCtl);
+ }
glintReg->glintRegs[VClkCtl >> 3] = GLINT_READ_REG(VClkCtl);
glintReg->glintRegs[VTGPolarity >> 3] = GLINT_READ_REG(VTGPolarity);
@@ -241,7 +310,6 @@ TXSave(ScrnInfoPtr pScrn, GLINTRegPtr glintReg)
glintReg->glintRegs[VTGVGateEnd >> 3] = GLINT_READ_REG(VTGVGateEnd);
glintReg->glintRegs[VTGSerialClk >> 3] = GLINT_READ_REG(VTGSerialClk);
glintReg->glintRegs[FBModeSel >> 3] = GLINT_READ_REG(FBModeSel);
- glintReg->glintRegs[VTGModeCtl >> 3] = GLINT_READ_REG(VTGModeCtl);
glintReg->glintRegs[VTGHGateStart >> 3] = GLINT_READ_REG(VTGHGateStart);
glintReg->glintRegs[VTGHGateEnd >> 3] = GLINT_READ_REG(VTGHGateEnd);
}
@@ -251,23 +319,21 @@ TXRestore(ScrnInfoPtr pScrn, GLINTRegPtr glintReg)
{
GLINTPtr pGlint = GLINTPTR(pScrn);
-#if 1
- GLINT_SLOW_WRITE_REG(0, ResetStatus);
- while(GLINT_READ_REG(ResetStatus) != 0) {
- xf86MsgVerb(X_INFO, 2, "Resetting Engine - Please Wait.\n");
- };
-#endif
-
GLINT_SLOW_WRITE_REG(glintReg->glintRegs[Aperture0 >> 3], Aperture0);
GLINT_SLOW_WRITE_REG(glintReg->glintRegs[Aperture1 >> 3], Aperture1);
- GLINT_SLOW_WRITE_REG(glintReg->glintRegs[DFIFODis >> 3], DFIFODis);
- GLINT_SLOW_WRITE_REG(glintReg->glintRegs[FIFODis >> 3], FIFODis);
+ if ((pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_DELTA) ||
+ (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_GAMMA))
+ GLINT_SLOW_WRITE_REG(glintReg->glintRegs[DFIFODis >> 3], DFIFODis);
+
+ if (pGlint->Chipset != PCI_VENDOR_3DLABS_CHIP_300SX) {
+ GLINT_SLOW_WRITE_REG(glintReg->glintRegs[FIFODis >> 3], FIFODis);
+ GLINT_SLOW_WRITE_REG(glintReg->glintRegs[VTGModeCtl >> 3], VTGModeCtl);
+ }
GLINT_SLOW_WRITE_REG(glintReg->glintRegs[VTGPolarity >> 3], VTGPolarity);
GLINT_SLOW_WRITE_REG(glintReg->glintRegs[VClkCtl >> 3], VClkCtl);
GLINT_SLOW_WRITE_REG(glintReg->glintRegs[VTGSerialClk >> 3], VTGSerialClk);
- GLINT_SLOW_WRITE_REG(glintReg->glintRegs[VTGModeCtl >> 3], VTGModeCtl);
GLINT_SLOW_WRITE_REG(glintReg->glintRegs[VTGHLimit >> 3], VTGHLimit);
GLINT_SLOW_WRITE_REG(glintReg->glintRegs[VTGHSyncStart >> 3],VTGHSyncStart);
GLINT_SLOW_WRITE_REG(glintReg->glintRegs[VTGHSyncEnd >> 3], VTGHSyncEnd);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 09:07:45 +0000