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Diffstat (limited to 'xc/lib/GL/mesa/src/drv/r128/r128_screen.h')
-rw-r--r--xc/lib/GL/mesa/src/drv/r128/r128_screen.h79
1 files changed, 55 insertions, 24 deletions
diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_screen.h b/xc/lib/GL/mesa/src/drv/r128/r128_screen.h
index bfbf4bc5f..07670331e 100644
--- a/xc/lib/GL/mesa/src/drv/r128/r128_screen.h
+++ b/xc/lib/GL/mesa/src/drv/r128/r128_screen.h
@@ -38,54 +38,85 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifdef GLX_DIRECT_RENDERING
typedef struct {
- drmHandle handle;
- drmSize size;
+ drmHandle handle; /* Handle to the DRM region */
+ drmSize size; /* Size of the DRM region */
} r128RegionRec, *r128RegionPtr;
typedef struct {
+ /* FIXME: There needs to be two register regions. One to allow
+ read-only access to the block of non-FIFO'd GUI registers
+ (0x0000-0x0FFC), and one to allow read/write acces to the block
+ of FIFO'd GUI registers (0x1000-0x1FFC) */
+
+ /* MMIO register data */
r128RegionRec mmioRgn;
unsigned char *mmio;
+ /* AGP data */
r128RegionRec agpRgn;
unsigned char *agp;
- int deviceID;
-
- int width;
- int height;
- int depth;
- int bpp;
-
+ /* Frame buffer data */
unsigned char *fb;
unsigned long fbOffset;
int fbStride;
int fbSize;
- int fbX;
+ int CCEMode; /* CCE mode that server/clients use */
+ int CCEFifoSize; /* Size of the CCE command FIFO */
+
+ /* CCE ring buffer data */
+ unsigned long ringStart;
+ int ringSize;
+ /* FIXME: These should be in the
+ SAREA so that they can be
+ shared with other clients. */
+ int *ringWritePtr; /* Pointer to current write addr */
+ int *ringReadPtr; /* Pointer to current read addr */
+
+ /* CCE vertex buffer data */
+ unsigned long vbStart;
+ int vbSize;
+
+ /* CCE indirect buffer data */
+ unsigned long indStart;
+ int indSize;
+
+ /* CCE AGP Texture data */
+ unsigned long agpTexStart;
+ int agpTexSize;
+ int log2AGPTexGran;
+
+ /* DRI screen private data */
+ int deviceID; /* PCI device ID */
+ int width; /* Width in pixels of display */
+ int height; /* Height in scanlines of display */
+ int depth; /* Depth of display (8, 15, 16, 24) */
+ int bpp; /* Bit depth of disp (8, 16, 24, 32) */
+
+ int fbX; /* Start of frame buffer */
int fbY;
- int backX;
+ int backX; /* Start of shared back buffer */
int backY;
- int depthX;
+ int depthX; /* Start of shared depth buffer */
int depthY;
- int textureX;
+ int textureX; /* Start of textures in frame buffer */
int textureY;
int textureSize;
+ int log2TexGran;
- int CCEMode;
- int CCEFifoSize;
+ int MMIOFifoSlots; /* Free slots in the FIFO (64 max) */
+ int CCEFifoSlots; /* Free slots in the CCE FIFO */
- unsigned long ringStart;
- int ringSize;
- int *ringWritePtr;
- int *ringReadPtr;
-
- int MMIOFifoSlots;
- int CCEFifoSlots;
-
- int CCEFifoAddr;
+ int CCEFifoAddr; /* MMIO offset to write next CCE
+ value (only used when CCE is
+ in PIO mode). */
__DRIscreenPrivate *driScreen;
} r128ScreenRec, *r128ScreenPtr;
+r128ScreenPtr r128CreateScreen(__DRIscreenPrivate *sPriv);
+void r128DestroyScreen(__DRIscreenPrivate *sPriv);
+
#endif
#endif /* _R128_SCREEN_H_ */