- Fix subpixel precision errors.

- Fix software alpha buffer initialization.
- Clean up depth clears, fixes SoF and H2 bugs.

15 files changed, 136 insertions, 127 deletions

diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h b/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h
index fb1fbbb4b..502c088eb 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h
@@ -81,15 +81,6 @@ typedef struct radeon_context *radeonContextPtr;
 #define RADEON_FALLBACK_MULTIDRAW	0x0020
 #define RADEON_FALLBACK_LOGICOP		0x0040
 
-/* Subpixel offsets for window coordinates: */
-#if 1
-#define SUBPIXEL_X		(-0.125F)
-#define SUBPIXEL_Y		( 0.375F)
-#else
-#define SUBPIXEL_X		(0.0F)
-#define SUBPIXEL_Y		(0.0F)
-#endif
-
 typedef void (*radeon_interp_func)( GLfloat t,
 				    GLfloat *result,
 				    const GLfloat *in,
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_dd.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_dd.c
index 6141fd88e..313d00b8f 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_dd.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_dd.c
@@ -46,7 +46,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "X86/common_x86_asm.h"
 #endif
 
-#define RADEON_DATE	"20010103"
+#define RADEON_DATE	"20010105"
 
 
 /* Return the width and height of the current color buffer.
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_eltpath.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_eltpath.c
index 0909c4b82..2957083e2 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_eltpath.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_eltpath.c
@@ -360,9 +360,9 @@ static void refresh_projection_matrix( GLcontext *ctx )
    m[MAT_SX] =  mat->m[MAT_SX];
    m[MAT_TX] =  mat->m[MAT_TX];
    m[MAT_SY] = -mat->m[MAT_SY];
-   m[MAT_TY] = -mat->m[MAT_TY] + rmesa->driDrawable->h;
-   m[MAT_SZ] =  mat->m[MAT_SZ] * rmesa->depth_scale;
-   m[MAT_TZ] =  mat->m[MAT_TZ] * rmesa->depth_scale;
+   m[MAT_TY] = -mat->m[MAT_TY];
+   m[MAT_SZ] =  mat->m[MAT_SZ];
+   m[MAT_TZ] =  mat->m[MAT_TZ];
 }
 
 #define CLIP_UBYTE_R 0
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_fastpath.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_fastpath.c
index af1a0e434..7c32a0f15 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_fastpath.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_fastpath.c
@@ -418,6 +418,10 @@ static void radeon_render_elements_direct( struct vertex_buffer *VB )
 	     ctx->Driver.MultipassFunc( VB, ++p ) );
 }
 
+/* GH: These should go away altogether on the Radeon.  We should disable
+ * the viewport mapping entirely in Mesa and let the hardware do it in
+ * all cases.
+ */
 static void radeon_project_vertices( struct vertex_buffer *VB )
 {
    GLcontext *ctx = VB->ctx;
@@ -429,9 +433,9 @@ static void radeon_project_vertices( struct vertex_buffer *VB )
    m[MAT_SX] =  mat->m[MAT_SX];
    m[MAT_TX] =  mat->m[MAT_TX];
    m[MAT_SY] = -mat->m[MAT_SY];
-   m[MAT_TY] = -mat->m[MAT_TY] + rmesa->driDrawable->h;
-   m[MAT_SZ] =  mat->m[MAT_SZ] * rmesa->depth_scale;
-   m[MAT_TZ] =  mat->m[MAT_TZ] * rmesa->depth_scale;
+   m[MAT_TY] = -mat->m[MAT_TY];
+   m[MAT_SZ] =  mat->m[MAT_SZ];
+   m[MAT_TZ] =  mat->m[MAT_TZ];
 
    gl_project_v16( rvb->verts[VB->CopyStart].f,
 		   rvb->verts[rvb->last_vert].f,
@@ -450,9 +454,9 @@ static void radeon_project_clipped_vertices( struct vertex_buffer *VB )
    m[MAT_SX] =  mat->m[MAT_SX];
    m[MAT_TX] =  mat->m[MAT_TX];
    m[MAT_SY] = -mat->m[MAT_SY];
-   m[MAT_TY] = -mat->m[MAT_TY] + rmesa->driDrawable->h;
-   m[MAT_SZ] =  mat->m[MAT_SZ] * rmesa->depth_scale;
-   m[MAT_TZ] =  mat->m[MAT_TZ] * rmesa->depth_scale;
+   m[MAT_TY] = -mat->m[MAT_TY];
+   m[MAT_SZ] =  mat->m[MAT_SZ];
+   m[MAT_TZ] =  mat->m[MAT_TZ];
 
    gl_project_clipped_v16( rvb->verts[VB->CopyStart].f,
 			   rvb->verts[rvb->last_vert].f,
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
index d909e574e..22ad27962 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
@@ -542,7 +542,8 @@ static GLbitfield radeonDDClear( GLcontext *ctx, GLbitfield mask,
    GLint ret, i;
 
    if ( RADEON_DEBUG & DEBUG_VERBOSE_API ) {
-      fprintf( stderr, "%s:\n", __FUNCTION__ );
+      fprintf( stderr, "%s:  all=%d cx=%d cy=%d cw=%d ch=%d\n",
+	       __FUNCTION__, all, cx, cy, cw, ch );
    }
 
    FLUSH_BATCH( rmesa );
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_span.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_span.c
index 9b154f7f5..69fc1870a 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_span.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_span.c
@@ -88,7 +88,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
       _n1 = _n;								\
       _x1 = _x;								\
       if (_x1 < minx) _i += (minx - _x1), _x1 = minx;			\
-      if (_x1 + _n1 >= maxx) n1 -= (_x1 + n1 - maxx) + 1;		\
+      if (_x1 + _n1 >= maxx) n1 -= (_x1 + n1 - maxx);			\
    }
 
 #define Y_FLIP( _y )		(height - _y - 1)
@@ -234,7 +234,7 @@ static __inline GLuint radeon_mba_z32( radeonContextPtr rmesa,
    *(GLushort *)(buf + radeon_mba_z16( rmesa, _x, _y )) = d;
 
 #define READ_DEPTH( d, _x, _y )						\
-   d = *(GLushort *)(buf + radeon_mba_z16( rmesa, _x, _y ) )
+   d = *(GLushort *)(buf + radeon_mba_z16( rmesa, _x, _y ));
 
 #define TAG(x) radeon##x##_16
 #include "depthtmp.h"
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c
index b66845433..4c87ed7aa 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c
@@ -562,19 +562,23 @@ static void radeonDDShadeModel( GLcontext *ctx, GLenum mode )
 void radeonUpdateWindow( GLcontext *ctx )
 {
    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-   CARD32 m = rmesa->setup.re_misc;
-   GLfloat x = (GLfloat) rmesa->driDrawable->x;
-   GLfloat y = (GLfloat) rmesa->driDrawable->y;
+   __DRIdrawablePrivate *dPriv = rmesa->driDrawable;
+   GLfloat xoffset = (GLfloat)dPriv->x;
+   GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
    const GLfloat one = 1.0;
+#if 0
+   CARD32 m = rmesa->setup.re_misc;
    CARD32 sx, sy;
+#endif
 
    rmesa->setup.se_vport_xscale  = *(GLuint *)&one;
-   rmesa->setup.se_vport_xoffset = *(GLuint *)&x;
+   rmesa->setup.se_vport_xoffset = *(GLuint *)&xoffset;
    rmesa->setup.se_vport_yscale  = *(GLuint *)&one;
-   rmesa->setup.se_vport_yoffset = *(GLuint *)&y;
-   rmesa->setup.se_vport_zscale  = *(GLuint *)&one;
+   rmesa->setup.se_vport_yoffset = *(GLuint *)&yoffset;
+   rmesa->setup.se_vport_zscale  = *(GLuint *)&rmesa->depth_scale;
    rmesa->setup.se_vport_zoffset = 0x00000000;
 
+#if 0
    /* FIXME: This appears to be broken...
     */
    m &= ~(RADEON_STIPPLE_X_OFFSET_MASK |
@@ -586,11 +590,12 @@ void radeonUpdateWindow( GLcontext *ctx )
    m |= ((sx << RADEON_STIPPLE_X_OFFSET_SHIFT) |
 	 (sy << RADEON_STIPPLE_Y_OFFSET_SHIFT));
 
-   rmesa->dirty |= RADEON_UPLOAD_VIEWPORT;
    if ( rmesa->setup.re_misc != m ) {
       rmesa->setup.re_misc = m;
       rmesa->dirty |= RADEON_UPLOAD_MISC;
    }
+#endif
+   rmesa->dirty |= RADEON_UPLOAD_VIEWPORT;
 }
 
 
@@ -889,6 +894,9 @@ void radeonEmitHwStateLocked( radeonContextPtr rmesa )
       memcpy( &sarea->ContextState, regs, sizeof(sarea->ContextState) );
    }
 
+   /* Assemble the texture state, combining the texture object and
+    * texture environment state into the hardware texture unit state.
+    */
    if ( (rmesa->dirty & RADEON_UPLOAD_TEX0) && t0 ) {
       radeon_texture_regs_t *tex = &sarea->TexState[0];
 
@@ -1181,6 +1189,7 @@ void radeonDDInitState( radeonContextPtr rmesa )
 			   RADEON_SPECULAR_SHADE_GOURAUD |
 			   RADEON_FOG_SHADE_GOURAUD |
 			   RADEON_VPORT_XY_XFORM_ENABLE |
+			   RADEON_VPORT_Z_XFORM_ENABLE |
 			   RADEON_VTX_PIX_CENTER_OGL |
 			   RADEON_ROUND_MODE_TRUNC |
 			   RADEON_ROUND_PREC_8TH_PIX);
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c
index fe0bd6543..47dd1a547 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c
@@ -143,7 +143,9 @@ static radeonTexObjPtr radeonCreateTexObj( radeonContextPtr rmesa,
 
    switch ( image->Format ) {
    case GL_RGBA:
-      if ( rmesa->radeonScreen->cpp == 4 ) {
+      if ( image->IntFormat != GL_RGBA4 &&
+	   ( image->IntFormat == GL_RGBA8 ||
+	     rmesa->radeonScreen->cpp == 4 ) ) {
 	 t->texelBytes = 4;
 	 txformat = RADEON_TXF_32BPP_ARGB8888;
       } else {
@@ -154,7 +156,9 @@ static radeonTexObjPtr radeonCreateTexObj( radeonContextPtr rmesa,
       break;
 
    case GL_RGB:
-      if ( rmesa->radeonScreen->cpp == 4 ) {
+      if ( image->IntFormat != GL_RGB5 &&
+	   ( image->IntFormat == GL_RGB8 ||
+	     rmesa->radeonScreen->cpp == 4 ) ) {
 	 t->texelBytes = 4;
 	 txformat = RADEON_TXF_32BPP_ARGB8888;
       } else {
@@ -906,9 +910,6 @@ static void radeonUploadSubImage( radeonContextPtr rmesa,
 
    rmesa->new_state |= RADEON_NEW_CONTEXT;
    rmesa->dirty |= RADEON_UPLOAD_CONTEXT | RADEON_UPLOAD_MASKS;
-
-
-   radeonWaitForIdleLocked( rmesa );
 }
 
 /* Upload the texture images associated with texture `t'.  This might
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_tris.h b/xc/lib/GL/mesa/src/drv/radeon/radeon_tris.h
index 5ddd0923a..8a77de803 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_tris.h
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_tris.h
@@ -163,7 +163,7 @@ static __inline void radeon_draw_quad( radeonContextPtr rmesa,
 static __inline void radeon_draw_line( radeonContextPtr rmesa,
 				       radeonVertexPtr tmp0,
 				       radeonVertexPtr tmp1,
-				       float width )
+				       GLfloat width )
 {
 #if 1
    GLuint vertsize = rmesa->vertsize;
@@ -248,7 +248,7 @@ static __inline void radeon_draw_line( radeonContextPtr rmesa,
 }
 
 static __inline void radeon_draw_point( radeonContextPtr rmesa,
-					radeonVertexPtr tmp, float sz )
+					radeonVertexPtr tmp, GLfloat sz )
 {
 #if 1
    GLuint vertsize = rmesa->vertsize;
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c
index 52780ec9d..c3421c5d9 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c
@@ -107,9 +107,9 @@ do {									\
 #define COORD								\
 do {									\
    GLfloat *win = VB->Win.data[i];					\
-   v->v.x =               win[0] + xoffset;				\
-   v->v.y =             - win[1] + yoffset;				\
-   v->v.z = depth_scale * win[2];					\
+   v->v.x =               win[0];					\
+   v->v.y =             - win[1];					\
+   v->v.z =               win[2];					\
    v->v.rhw = v->v.rhw2 = win[3];					\
 } while (0)
 
@@ -120,10 +120,10 @@ do {									\
 #define COORD								\
 do {									\
    GLfloat *win = VB->Win.data[i];					\
-   v->v.x =               win[0] + xoffset;				\
-   v->v.y =             - win[1] + yoffset;				\
-   v->v.z = depth_scale * win[2];					\
-   v->v.rhw =             win[3];					\
+   v->v.x =   win[0];							\
+   v->v.y = - win[1];							\
+   v->v.z =   win[2];							\
+   v->v.rhw = win[3];							\
 } while (0)								\
 
 #endif /* USE_RHW2 */
@@ -135,17 +135,11 @@ do {									\
 static void name( struct vertex_buffer *VB, GLuint start, GLuint end )	\
 {									\
    radeonContextPtr rmesa = RADEON_CONTEXT(VB->ctx);			\
-   __DRIdrawablePrivate *dPriv = rmesa->driDrawable;			\
    radeonVertexPtr v;							\
    GLfloat (*tc0)[4];							\
    GLfloat (*tc1)[4];							\
-   const GLfloat depth_scale = rmesa->depth_scale;			\
-   const GLfloat xoffset = SUBPIXEL_X;					\
-   const GLfloat yoffset = dPriv->h + SUBPIXEL_Y;			\
    GLint i;								\
 									\
-   (void) xoffset; (void) yoffset; (void) depth_scale;			\
-									\
    gl_import_client_data( VB, VB->ctx->RenderFlags,			\
 			  (VB->ClipOrMask				\
 			   ? VEC_WRITABLE | VEC_GOOD_STRIDE		\
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_xmesa.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_xmesa.c
index 51aeae630..4d79f770c 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_xmesa.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_xmesa.c
@@ -126,10 +126,10 @@ GLframebuffer *XMesaCreateWindowBuffer( Display *dpy,
 					GLvisual *mesaVis )
 {
    return gl_create_framebuffer( mesaVis,
-				 GL_FALSE,  /* software depth buffer? */
+				 GL_FALSE, /* software depth buffer? */
 				 mesaVis->StencilBits > 0,
 				 mesaVis->AccumRedBits > 0,
-				 mesaVis->AlphaBits > 0 );
+				 GL_FALSE  /* software alpha buffer? */ );
 }
 
 /* Create and initialize the Mesa and driver specific pixmap buffer
diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_cp.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_cp.c
index 0df883c67..5d662bc08 100644
--- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_cp.c
+++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_cp.c
@@ -667,13 +667,29 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 		return -EINVAL;
 	}
 
-	dev_priv->fb_bpp	= init->fb_bpp;
+	switch ( init->fb_bpp ) {
+	case 16:
+		dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
+		break;
+	case 32:
+	default:
+		dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
+		break;
+	}
 	dev_priv->front_offset	= init->front_offset;
 	dev_priv->front_pitch	= init->front_pitch;
 	dev_priv->back_offset	= init->back_offset;
 	dev_priv->back_pitch	= init->back_pitch;
 
-	dev_priv->depth_bpp	= init->depth_bpp;
+	switch ( init->depth_bpp ) {
+	case 16:
+		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
+		break;
+	case 32:
+	default:
+		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
+		break;
+	}
 	dev_priv->depth_offset	= init->depth_offset;
 	dev_priv->depth_pitch	= init->depth_pitch;
 
@@ -684,6 +700,38 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
 					(dev_priv->depth_offset >> 10));
 
+	/* Hardware state for depth clears.  Remove this if/when we no
+	 * longer clear the depth buffer with a 3D rectangle.  Hard-code
+	 * all values to prevent unwanted 3D state from slipping through
+	 * and screwing with the clear operation.
+	 */
+	dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
+					   RADEON_Z_ENABLE |
+					   (dev_priv->color_fmt << 10) |
+					   RADEON_ZBLOCK16);
+
+	dev_priv->depth_clear.rb3d_zstencilcntl = (dev_priv->depth_fmt |
+						   RADEON_Z_TEST_ALWAYS |
+						   RADEON_STENCIL_TEST_ALWAYS |
+						   RADEON_STENCIL_S_FAIL_KEEP |
+						   RADEON_STENCIL_ZPASS_KEEP |
+						   RADEON_STENCIL_ZFAIL_KEEP |
+						   RADEON_Z_WRITE_ENABLE);
+
+	dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
+					 RADEON_BFACE_SOLID |
+					 RADEON_FFACE_SOLID |
+					 RADEON_FLAT_SHADE_VTX_LAST |
+
+					 RADEON_DIFFUSE_SHADE_FLAT |
+					 RADEON_ALPHA_SHADE_FLAT |
+					 RADEON_SPECULAR_SHADE_FLAT |
+					 RADEON_FOG_SHADE_FLAT |
+
+					 RADEON_VTX_PIX_CENTER_OGL |
+					 RADEON_ROUND_MODE_TRUNC |
+					 RADEON_ROUND_PREC_8TH_PIX);
+
 	/* FIXME: We want multiple shared areas, including one shared
 	 * only by the X Server and kernel module.
 	 */
diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.c
index c9bb3eeaf..0113ed97c 100644
--- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.c
+++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.c
@@ -34,7 +34,7 @@
 
 #define RADEON_NAME		"radeon"
 #define RADEON_DESC		"ATI Radeon"
-#define RADEON_DATE		"20010103"
+#define RADEON_DATE		"20010105"
 #define RADEON_MAJOR		1
 #define RADEON_MINOR		0
 #define RADEON_PATCHLEVEL	0
diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.h
index 985ebc7ed..06b541991 100644
--- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.h
+++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.h
@@ -52,6 +52,12 @@ typedef struct drm_radeon_ring_buffer {
 	int space;
 } drm_radeon_ring_buffer_t;
 
+typedef struct drm_radeon_depth_clear_t {
+	u32 rb3d_cntl;
+	u32 rb3d_zstencilcntl;
+	u32 se_cntl;
+} drm_radeon_depth_clear_t;
+
 typedef struct drm_radeon_private {
 	drm_radeon_ring_buffer_t ring;
 	drm_radeon_sarea_t *sarea_priv;
@@ -85,13 +91,13 @@ typedef struct drm_radeon_private {
 	u32 crtc_offset;
 	u32 crtc_offset_cntl;
 
-	unsigned int fb_bpp;
+	unsigned int color_fmt;
 	unsigned int front_offset;
 	unsigned int front_pitch;
 	unsigned int back_offset;
 	unsigned int back_pitch;
 
-	unsigned int depth_bpp;
+	unsigned int depth_fmt;
 	unsigned int depth_offset;
 	unsigned int depth_pitch;
 
@@ -99,6 +105,8 @@ typedef struct drm_radeon_private {
 	u32 back_pitch_offset;
 	u32 depth_pitch_offset;
 
+	drm_radeon_depth_clear_t depth_clear;
+
 	drm_map_t *sarea;
 	drm_map_t *fb;
 	drm_map_t *mmio;
@@ -353,9 +361,13 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #	define RADEON_BFACE_SOLID		(3 << 1)
 #	define RADEON_FFACE_SOLID		(3 << 3)
 #	define RADEON_FLAT_SHADE_VTX_LAST	(3 << 6)
+#	define RADEON_DIFFUSE_SHADE_FLAT	(1 << 8)
 #	define RADEON_DIFFUSE_SHADE_GOURAUD	(2 << 8)
+#	define RADEON_ALPHA_SHADE_FLAT		(1 << 10)
 #	define RADEON_ALPHA_SHADE_GOURAUD	(2 << 10)
+#	define RADEON_SPECULAR_SHADE_FLAT	(1 << 12)
 #	define RADEON_SPECULAR_SHADE_GOURAUD	(2 << 12)
+#	define RADEON_FOG_SHADE_FLAT		(1 << 14)
 #	define RADEON_FOG_SHADE_GOURAUD		(2 << 14)
 #	define RADEON_VPORT_XY_XFORM_ENABLE	(1 << 24)
 #	define RADEON_VPORT_Z_XFORM_ENABLE	(1 << 25)
diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_state.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_state.c
index a7bbaf074..12bd6c796 100644
--- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_state.c
+++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_state.c
@@ -411,19 +411,17 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
 			      int r, int g, int b )
 {
 	u32 pitch, offset;
-	u32 fb_bpp, color;
+	u32 color;
 	RING_LOCALS;
 
-	switch ( dev_priv->fb_bpp ) {
-	case 16:
-		fb_bpp = RADEON_GMC_DST_16BPP;
+	switch ( dev_priv->color_fmt ) {
+	case RADEON_COLOR_FORMAT_RGB565:
 		color = (((r & 0xf8) << 8) |
 			 ((g & 0xfc) << 3) |
 			 ((b & 0xf8) >> 3));
 		break;
-	case 32:
+	case RADEON_COLOR_FORMAT_ARGB8888:
 	default:
-		fb_bpp = RADEON_GMC_DST_32BPP;
 		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
 		break;
 	}
@@ -436,7 +434,7 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
 	OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 	OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 		  RADEON_GMC_BRUSH_SOLID_COLOR |
-		  fb_bpp |
+		  (dev_priv->color_fmt << 8) |
 		  RADEON_GMC_SRC_DATATYPE_COLOR |
 		  RADEON_ROP3_P |
 		  RADEON_GMC_CLR_CMP_CNTL_DIS );
@@ -495,33 +493,12 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 	int nbox = sarea_priv->nbox;
 	drm_clip_rect_t *pbox = sarea_priv->boxes;
 	unsigned int flags = clear->flags;
-	u32 fb_bpp, depth_bpp;
 	int i;
 	RING_LOCALS;
 	DRM_DEBUG( "%s\n", __FUNCTION__ );
 
 	radeon_update_ring_snapshot( dev_priv );
 
-	switch ( dev_priv->fb_bpp ) {
-	case 16:
-		fb_bpp = RADEON_GMC_DST_16BPP;
-		break;
-	case 32:
-	default:
-		fb_bpp = RADEON_GMC_DST_32BPP;
-		break;
-	}
-	switch ( dev_priv->depth_bpp ) {
-	case 16:
-		depth_bpp = RADEON_GMC_DST_16BPP;
-		break;
-	case 32:
-		depth_bpp = RADEON_GMC_DST_32BPP;
-		break;
-	default:
-		return;
-	}
-
 	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
 		unsigned int tmp = flags;
 
@@ -537,8 +514,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 		int h = pbox[i].y2 - y;
 
 		DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
-			   pbox[i].x1, pbox[i].y1, pbox[i].x2,
-			   pbox[i].y2, flags );
+			   x, y, w, h, flags );
 
 		if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
 			BEGIN_RING( 4 );
@@ -565,7 +541,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 			OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 			OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 				  RADEON_GMC_BRUSH_SOLID_COLOR |
-				  fb_bpp |
+				  (dev_priv->color_fmt << 8) |
 				  RADEON_GMC_SRC_DATATYPE_COLOR |
 				  RADEON_ROP3_P |
 				  RADEON_GMC_CLR_CMP_CNTL_DIS );
@@ -585,7 +561,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 			OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 			OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 				  RADEON_GMC_BRUSH_SOLID_COLOR |
-				  fb_bpp |
+				  (dev_priv->color_fmt << 8) |
 				  RADEON_GMC_SRC_DATATYPE_COLOR |
 				  RADEON_ROP3_P |
 				  RADEON_GMC_CLR_CMP_CNTL_DIS );
@@ -597,49 +573,33 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 			OUT_RING( (w << 16) | h );
 
 			ADVANCE_RING();
+
 		}
 
 		if ( flags & RADEON_DEPTH ) {
-			drm_radeon_context_regs_t *ctx =
-			   &sarea_priv->context_state;
-			u32 rb3d_cntl = ctx->rb3d_cntl;
-			u32 rb3d_zstencilcntl = ctx->rb3d_zstencilcntl;
-			u32 se_cntl = ctx->se_cntl;
+			drm_radeon_depth_clear_t *depth_clear =
+			   &dev_priv->depth_clear;
 
 			if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
 				radeon_emit_state( dev_priv );
 			}
 
-			/* FIXME: Do re really need to do this?  Why
-			 * not just precalculate all the values?
-			 */
-			rb3d_cntl |= (RADEON_PLANE_MASK_ENABLE |
-				      RADEON_Z_ENABLE);
-
-			rb3d_zstencilcntl |= (RADEON_Z_TEST_ALWAYS |
-					      RADEON_Z_WRITE_ENABLE);
-
-			se_cntl &= ~(RADEON_VPORT_XY_XFORM_ENABLE |
-				     RADEON_VPORT_Z_XFORM_ENABLE);
-			se_cntl |= (RADEON_FFACE_SOLID |
-				    RADEON_BFACE_SOLID);
-
 			/* FIXME: Render a rectangle to clear the depth
 			 * buffer.  So much for those "fast Z clears"...
 			 */
-			BEGIN_RING( 22 );
+			BEGIN_RING( 23 );
 
 			RADEON_WAIT_UNTIL_2D_IDLE();
 
 			OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
 			OUT_RING( 0x00000000 );
-			OUT_RING( rb3d_cntl );
+			OUT_RING( depth_clear->rb3d_cntl );
 			OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) );
-			OUT_RING( rb3d_zstencilcntl );
+			OUT_RING( depth_clear->rb3d_zstencilcntl );
 			OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) );
 			OUT_RING( 0x00000000 );
 			OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
-			OUT_RING( se_cntl );
+			OUT_RING( depth_clear->se_cntl );
 
 			OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) );
 			OUT_RING( RADEON_VTX_Z_PRESENT );
@@ -691,7 +651,6 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	int nbox = sarea_priv->nbox;
 	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	u32 fb_bpp;
 	int i;
 	RING_LOCALS;
 	DRM_DEBUG( "%s\n", __FUNCTION__ );
@@ -704,19 +663,6 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
 	radeon_cp_performance_boxes( dev_priv );
 #endif
 
-	switch ( dev_priv->fb_bpp ) {
-	case 16:
-		fb_bpp = RADEON_GMC_DST_16BPP;
-		break;
-	case 24:
-		fb_bpp = RADEON_GMC_DST_24BPP;
-		break;
-	case 32:
-	default:
-		fb_bpp = RADEON_GMC_DST_32BPP;
-		break;
-	}
-
 	/* Wait for the 3D stream to idle before dispatching the bitblt.
 	 * This will prevent data corruption between the two streams.
 	 */
@@ -732,13 +678,16 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
 		int w = pbox[i].x2 - x;
 		int h = pbox[i].y2 - y;
 
+		DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
+			   x, y, w, h );
+
 		BEGIN_RING( 7 );
 
 		OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
 		OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 			  RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 			  RADEON_GMC_BRUSH_NONE |
-			  fb_bpp |
+			  (dev_priv->color_fmt << 8) |
 			  RADEON_GMC_SRC_DATATYPE_COLOR |
 			  RADEON_ROP3_S |
 			  RADEON_DP_SRC_SOURCE_MEMORY |
@@ -1139,7 +1088,7 @@ static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	int i;
 	RING_LOCALS;
-	DRM_INFO( "%s\n", __FUNCTION__ );
+	DRM_DEBUG( "%s\n", __FUNCTION__ );
 
 	radeon_update_ring_snapshot( dev_priv );