hacksdisplayport

3 files changed, 28 insertions, 10 deletions

diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 2efc5bd8..9f903f65 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -365,8 +365,12 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
     RADEONComputePLL(&info->pll, adj_pixel_clock, &temp, &fb_div, &frac_fb_div, &ref_div, &post_div, pll_flags);
     sclock = temp;
     
+    fb_div = 0xa0;
+    post_div = 2;
+    ref_div = 8;
+    //    sclock = adj_pixel_clock / 10;
     sclock = mode->Clock / 10;
-
+    //    mode->Clock = adj_pixel_clock;
     xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
 	       "crtc(%d) Clock: mode %d, PLL %lu, adj %d\n",
 	       radeon_crtc->crtc_id, mode->Clock, (long unsigned int)sclock * 10, adj_pixel_clock);
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 5c140bbb..84a24ec7 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -709,10 +709,11 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action)
     } else {
 	disp_data.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 
-	if (radeon_output->MonType == MT_DP)
-	    disp_data.v1.usPixelClock =
+	if (radeon_output->MonType == MT_DP) {
+	  disp_data.v2.acConfig.fDPConnector = 1;
+	  disp_data.v1.usPixelClock =
 		cpu_to_le16(dp_link_clock_for_mode_clock(clock));
-	else
+        } else
 	    disp_data.v1.usPixelClock = cpu_to_le16((clock) / 10);
 
 	switch (radeon_encoder->encoder_id) {
@@ -742,7 +743,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action)
 			disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 		}
 	    } else {
-		if (clock > 165000)
+		if (clock > 165000 && radeon_output->MonType != MT_DP)
 		    disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
 					      ATOM_TRANSMITTER_CONFIG_LINKA_B |
 					      ATOM_TRANSMITTER_CONFIG_LANE_0_7);
@@ -771,6 +772,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action)
 	    break;
 	}
 
+	disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 	if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) {
 	    if (radeon_output->coherent_mode &&
 		radeon_output->MonType != MT_DP) {
@@ -792,7 +794,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action)
 	if (IS_DCE32_VARIANT)
 	    ErrorF("Output UNIPHY%d transmitter setup success\n", num);
 	else
-	   ErrorF("Output DIG%d transmitter setup success\n", num);
+	  ErrorF("Output DIG%d transmitter action %d setup success\n", num, action);
 	return ATOM_SUCCESS;
     }
 
@@ -1868,7 +1870,8 @@ RADEONDPEncoderService(xf86OutputPtr output, int action, uint8_t ucconfig, uint8
 
     memset(&args, 0, sizeof(args));
     
-    args.ucLinkClock = 0;
+    /* lies uc is actually usLinkClock */
+    args.ucLinkClock = radeon_output->dp_clock/10;
     args.ucConfig = ucconfig;
     args.ucAction = action;
     args.ucLaneNum = lane_num;
@@ -1964,6 +1967,10 @@ int RADEON_DP_DigTransmitterSetup_VSEMPH(xf86OutputPtr output, uint8_t lane_num,
 	    if (info->IsIGP) {
 	    } else {
 		
+	      if (radeon_output->linkb)
+		disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+	      else
+		disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 	    }
 	}
     }
@@ -2522,8 +2529,10 @@ static void dp_update_dpvs_emph(xf86OutputPtr output, uint8_t train_set[4])
 {
     RADEONOutputPrivatePtr radeon_output = output->driver_private;
     int i;
-    for (i = 0; i < radeon_output->dp_lane_count; i++)
-	RADEON_DP_DigTransmitterSetup_VSEMPH(output, i, train_set[i]);
+    
+    //for (i = 0; i < radeon_output->dp_lane_count; i++)
+    /* hw only has one ? */
+    RADEON_DP_DigTransmitterSetup_VSEMPH(output, 0, train_set[0]);
 
     atom_dp_aux_native_write(output, DP_TRAINING_LANE0_SET, radeon_output->dp_lane_count, train_set);
 }
@@ -2567,6 +2576,10 @@ static void do_displayport_dance(xf86OutputPtr output, DisplayModePtr mode, Disp
     atom_dp_aux_native_write(output, 0x100, 2,
 			     radeon_output->dp_link_configuration);
 
+    {
+      unsigned char zero = 0;
+      atom_dp_aux_native_write(output, 0x107, 1, &zero);
+    }
     /* start local training start */
     RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_START, enc_id, 0);
 
@@ -2581,6 +2594,7 @@ static void do_displayport_dance(xf86OutputPtr output, DisplayModePtr mode, Disp
     tries = 0;
     voltage = 0xff;
     for (;;) {
+
       	usleep(100);
 	if (!atom_dp_get_link_status(output, link_status))
 	    break;
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index b80c5d0b..14bc2809 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -2594,7 +2594,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data)
     CAILFUNC(CAIL);
 
     OUTREG(idx << 2,data);
-    /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data));*/
+    DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data));
 }
 
 UINT32