1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
|
#ifndef __ddr2_defs_asm_h
#define __ddr2_defs_asm_h
/*
* This file is autogenerated from
* file: ddr2.r
*
* by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_cfg, scope ddr2, type rw */
#define reg_ddr2_rw_cfg___col_width___lsb 0
#define reg_ddr2_rw_cfg___col_width___width 4
#define reg_ddr2_rw_cfg___nr_banks___lsb 4
#define reg_ddr2_rw_cfg___nr_banks___width 1
#define reg_ddr2_rw_cfg___nr_banks___bit 4
#define reg_ddr2_rw_cfg___bw___lsb 5
#define reg_ddr2_rw_cfg___bw___width 1
#define reg_ddr2_rw_cfg___bw___bit 5
#define reg_ddr2_rw_cfg___nr_ref___lsb 6
#define reg_ddr2_rw_cfg___nr_ref___width 4
#define reg_ddr2_rw_cfg___ref_interval___lsb 10
#define reg_ddr2_rw_cfg___ref_interval___width 11
#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21
#define reg_ddr2_rw_cfg___odt_ctrl___width 2
#define reg_ddr2_rw_cfg___odt_mem___lsb 23
#define reg_ddr2_rw_cfg___odt_mem___width 1
#define reg_ddr2_rw_cfg___odt_mem___bit 23
#define reg_ddr2_rw_cfg___imp_strength___lsb 24
#define reg_ddr2_rw_cfg___imp_strength___width 1
#define reg_ddr2_rw_cfg___imp_strength___bit 24
#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25
#define reg_ddr2_rw_cfg___auto_imp_cal___width 1
#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25
#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26
#define reg_ddr2_rw_cfg___imp_cal_override___width 1
#define reg_ddr2_rw_cfg___imp_cal_override___bit 26
#define reg_ddr2_rw_cfg___dll_override___lsb 27
#define reg_ddr2_rw_cfg___dll_override___width 1
#define reg_ddr2_rw_cfg___dll_override___bit 27
#define reg_ddr2_rw_cfg_offset 0
/* Register rw_timing, scope ddr2, type rw */
#define reg_ddr2_rw_timing___wr___lsb 0
#define reg_ddr2_rw_timing___wr___width 3
#define reg_ddr2_rw_timing___rcd___lsb 3
#define reg_ddr2_rw_timing___rcd___width 3
#define reg_ddr2_rw_timing___rp___lsb 6
#define reg_ddr2_rw_timing___rp___width 3
#define reg_ddr2_rw_timing___ras___lsb 9
#define reg_ddr2_rw_timing___ras___width 4
#define reg_ddr2_rw_timing___rfc___lsb 13
#define reg_ddr2_rw_timing___rfc___width 7
#define reg_ddr2_rw_timing___rc___lsb 20
#define reg_ddr2_rw_timing___rc___width 5
#define reg_ddr2_rw_timing___rtp___lsb 25
#define reg_ddr2_rw_timing___rtp___width 2
#define reg_ddr2_rw_timing___rtw___lsb 27
#define reg_ddr2_rw_timing___rtw___width 3
#define reg_ddr2_rw_timing___wtr___lsb 30
#define reg_ddr2_rw_timing___wtr___width 2
#define reg_ddr2_rw_timing_offset 4
/* Register rw_latency, scope ddr2, type rw */
#define reg_ddr2_rw_latency___cas___lsb 0
#define reg_ddr2_rw_latency___cas___width 3
#define reg_ddr2_rw_latency___additive___lsb 3
#define reg_ddr2_rw_latency___additive___width 3
#define reg_ddr2_rw_latency_offset 8
/* Register rw_phy_cfg, scope ddr2, type rw */
#define reg_ddr2_rw_phy_cfg___en___lsb 0
#define reg_ddr2_rw_phy_cfg___en___width 1
#define reg_ddr2_rw_phy_cfg___en___bit 0
#define reg_ddr2_rw_phy_cfg_offset 12
/* Register rw_phy_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_phy_ctrl___rst___lsb 0
#define reg_ddr2_rw_phy_ctrl___rst___width 1
#define reg_ddr2_rw_phy_ctrl___rst___bit 0
#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1
#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1
#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1
#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2
#define reg_ddr2_rw_phy_ctrl___cal_start___width 1
#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2
#define reg_ddr2_rw_phy_ctrl_offset 16
/* Register rw_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_ctrl___mrs_data___lsb 0
#define reg_ddr2_rw_ctrl___mrs_data___width 16
#define reg_ddr2_rw_ctrl___cmd___lsb 16
#define reg_ddr2_rw_ctrl___cmd___width 8
#define reg_ddr2_rw_ctrl_offset 20
/* Register rw_pwr_down, scope ddr2, type rw */
#define reg_ddr2_rw_pwr_down___self_ref___lsb 0
#define reg_ddr2_rw_pwr_down___self_ref___width 2
#define reg_ddr2_rw_pwr_down___phy_en___lsb 2
#define reg_ddr2_rw_pwr_down___phy_en___width 1
#define reg_ddr2_rw_pwr_down___phy_en___bit 2
#define reg_ddr2_rw_pwr_down_offset 24
/* Register r_stat, scope ddr2, type r */
#define reg_ddr2_r_stat___dll_lock___lsb 0
#define reg_ddr2_r_stat___dll_lock___width 1
#define reg_ddr2_r_stat___dll_lock___bit 0
#define reg_ddr2_r_stat___dll_delay_code___lsb 1
#define reg_ddr2_r_stat___dll_delay_code___width 7
#define reg_ddr2_r_stat___imp_cal_done___lsb 8
#define reg_ddr2_r_stat___imp_cal_done___width 1
#define reg_ddr2_r_stat___imp_cal_done___bit 8
#define reg_ddr2_r_stat___imp_cal_fault___lsb 9
#define reg_ddr2_r_stat___imp_cal_fault___width 1
#define reg_ddr2_r_stat___imp_cal_fault___bit 9
#define reg_ddr2_r_stat___cal_imp_pu___lsb 10
#define reg_ddr2_r_stat___cal_imp_pu___width 4
#define reg_ddr2_r_stat___cal_imp_pd___lsb 14
#define reg_ddr2_r_stat___cal_imp_pd___width 4
#define reg_ddr2_r_stat_offset 28
/* Register rw_imp_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0
#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4
#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4
#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4
#define reg_ddr2_rw_imp_ctrl_offset 32
#define STRIDE_ddr2_rw_dll_ctrl 4
/* Register rw_dll_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_dll_ctrl___mode___lsb 0
#define reg_ddr2_rw_dll_ctrl___mode___width 1
#define reg_ddr2_rw_dll_ctrl___mode___bit 0
#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1
#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7
#define reg_ddr2_rw_dll_ctrl_offset 36
#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0
#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14
#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21
#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7
#define reg_ddr2_rw_dqs_dll_ctrl_offset 52
/* Constants */
#define regk_ddr2_al0 0x00000000
#define regk_ddr2_al1 0x00000008
#define regk_ddr2_al2 0x00000010
#define regk_ddr2_al3 0x00000018
#define regk_ddr2_al4 0x00000020
#define regk_ddr2_auto 0x00000003
#define regk_ddr2_bank4 0x00000000
#define regk_ddr2_bank8 0x00000001
#define regk_ddr2_bl4 0x00000002
#define regk_ddr2_bl8 0x00000003
#define regk_ddr2_bt_il 0x00000008
#define regk_ddr2_bt_seq 0x00000000
#define regk_ddr2_bw16 0x00000001
#define regk_ddr2_bw32 0x00000000
#define regk_ddr2_cas2 0x00000020
#define regk_ddr2_cas3 0x00000030
#define regk_ddr2_cas4 0x00000040
#define regk_ddr2_cas5 0x00000050
#define regk_ddr2_deselect 0x000000c0
#define regk_ddr2_dic_weak 0x00000002
#define regk_ddr2_direct 0x00000001
#define regk_ddr2_dis 0x00000000
#define regk_ddr2_dll_dis 0x00000001
#define regk_ddr2_dll_en 0x00000000
#define regk_ddr2_dll_rst 0x00000100
#define regk_ddr2_emrs 0x00000081
#define regk_ddr2_emrs2 0x00000082
#define regk_ddr2_emrs3 0x00000083
#define regk_ddr2_full 0x00000001
#define regk_ddr2_hi_ref_rate 0x00000080
#define regk_ddr2_mrs 0x00000080
#define regk_ddr2_no 0x00000000
#define regk_ddr2_nop 0x000000b8
#define regk_ddr2_ocd_adj 0x00000200
#define regk_ddr2_ocd_default 0x00000380
#define regk_ddr2_ocd_drive0 0x00000100
#define regk_ddr2_ocd_drive1 0x00000080
#define regk_ddr2_ocd_exit 0x00000000
#define regk_ddr2_odt_dis 0x00000000
#define regk_ddr2_offs 0x00000000
#define regk_ddr2_pre 0x00000090
#define regk_ddr2_pre_all 0x00000400
#define regk_ddr2_pwr_down_fast 0x00000000
#define regk_ddr2_pwr_down_slow 0x00001000
#define regk_ddr2_ref 0x00000088
#define regk_ddr2_rtt150 0x00000040
#define regk_ddr2_rtt50 0x00000044
#define regk_ddr2_rtt75 0x00000004
#define regk_ddr2_rw_cfg_default 0x00186000
#define regk_ddr2_rw_dll_ctrl_default 0x00000000
#define regk_ddr2_rw_dll_ctrl_size 0x00000004
#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000
#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004
#define regk_ddr2_rw_latency_default 0x00000000
#define regk_ddr2_rw_phy_cfg_default 0x00000000
#define regk_ddr2_rw_pwr_down_default 0x00000000
#define regk_ddr2_rw_timing_default 0x00000000
#define regk_ddr2_s1Gb 0x0000001a
#define regk_ddr2_s256Mb 0x0000000f
#define regk_ddr2_s2Gb 0x00000027
#define regk_ddr2_s4Gb 0x00000042
#define regk_ddr2_s512Mb 0x00000015
#define regk_ddr2_temp0_85 0x00000618
#define regk_ddr2_temp85_95 0x0000030c
#define regk_ddr2_term150 0x00000002
#define regk_ddr2_term50 0x00000003
#define regk_ddr2_term75 0x00000001
#define regk_ddr2_test 0x00000080
#define regk_ddr2_weak 0x00000000
#define regk_ddr2_wr2 0x00000200
#define regk_ddr2_wr3 0x00000400
#define regk_ddr2_yes 0x00000001
#endif /* __ddr2_defs_asm_h */
|
