diff options
Diffstat (limited to 'sound/soc/codecs')
26 files changed, 5152 insertions, 781 deletions
diff --git a/sound/soc/codecs/ak4642.c b/sound/soc/codecs/ak4642.c index 1f0cdab03294..2d0378709702 100644 --- a/sound/soc/codecs/ak4642.c +++ b/sound/soc/codecs/ak4642.c @@ -26,6 +26,7 @@ #include <linux/delay.h> #include <linux/i2c.h> #include <linux/slab.h> +#include <linux/of_device.h> #include <linux/module.h> #include <sound/soc.h> #include <sound/initval.h> @@ -513,12 +514,31 @@ static struct snd_soc_codec_driver soc_codec_dev_ak4648 = { }; #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) +static struct of_device_id ak4642_of_match[]; static int ak4642_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { + struct device_node *np = i2c->dev.of_node; + const struct snd_soc_codec_driver *driver; + + driver = NULL; + if (np) { + const struct of_device_id *of_id; + + of_id = of_match_device(ak4642_of_match, &i2c->dev); + if (of_id) + driver = of_id->data; + } else { + driver = (struct snd_soc_codec_driver *)id->driver_data; + } + + if (!driver) { + dev_err(&i2c->dev, "no driver\n"); + return -EINVAL; + } + return snd_soc_register_codec(&i2c->dev, - (struct snd_soc_codec_driver *)id->driver_data, - &ak4642_dai, 1); + driver, &ak4642_dai, 1); } static int ak4642_i2c_remove(struct i2c_client *client) @@ -527,6 +547,14 @@ static int ak4642_i2c_remove(struct i2c_client *client) return 0; } +static struct of_device_id ak4642_of_match[] = { + { .compatible = "asahi-kasei,ak4642", .data = &soc_codec_dev_ak4642}, + { .compatible = "asahi-kasei,ak4643", .data = &soc_codec_dev_ak4642}, + { .compatible = "asahi-kasei,ak4648", .data = &soc_codec_dev_ak4648}, + {}, +}; +MODULE_DEVICE_TABLE(of, ak4642_of_match); + static const struct i2c_device_id ak4642_i2c_id[] = { { "ak4642", (kernel_ulong_t)&soc_codec_dev_ak4642 }, { "ak4643", (kernel_ulong_t)&soc_codec_dev_ak4642 }, @@ -539,6 +567,7 @@ static struct i2c_driver ak4642_i2c_driver = { .driver = { .name = "ak4642-codec", .owner = THIS_MODULE, + .of_match_table = ak4642_of_match, }, .probe = ak4642_i2c_probe, .remove = ak4642_i2c_remove, diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c index ef62c435848e..d824c984c8a4 100644 --- a/sound/soc/codecs/arizona.c +++ b/sound/soc/codecs/arizona.c @@ -56,14 +56,14 @@ #define arizona_fll_warn(_fll, fmt, ...) \ dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) #define arizona_fll_dbg(_fll, fmt, ...) \ - dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) + dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) #define arizona_aif_err(_dai, fmt, ...) \ dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) #define arizona_aif_warn(_dai, fmt, ...) \ dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) #define arizona_aif_dbg(_dai, fmt, ...) \ - dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) + dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { "None", @@ -141,6 +141,30 @@ const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { "ASRC1R", "ASRC2L", "ASRC2R", + "ISRC1INT1", + "ISRC1INT2", + "ISRC1INT3", + "ISRC1INT4", + "ISRC1DEC1", + "ISRC1DEC2", + "ISRC1DEC3", + "ISRC1DEC4", + "ISRC2INT1", + "ISRC2INT2", + "ISRC2INT3", + "ISRC2INT4", + "ISRC2DEC1", + "ISRC2DEC2", + "ISRC2DEC3", + "ISRC2DEC4", + "ISRC3INT1", + "ISRC3INT2", + "ISRC3INT3", + "ISRC3INT4", + "ISRC3DEC1", + "ISRC3DEC2", + "ISRC3DEC3", + "ISRC3DEC4", }; EXPORT_SYMBOL_GPL(arizona_mixer_texts); @@ -220,6 +244,30 @@ int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = { 0x91, 0x92, 0x93, + 0xa0, /* ISRC1INT1 */ + 0xa1, + 0xa2, + 0xa3, + 0xa4, /* ISRC1DEC1 */ + 0xa5, + 0xa6, + 0xa7, + 0xa8, /* ISRC2DEC1 */ + 0xa9, + 0xaa, + 0xab, + 0xac, /* ISRC2INT1 */ + 0xad, + 0xae, + 0xaf, + 0xb0, /* ISRC3DEC1 */ + 0xb1, + 0xb2, + 0xb3, + 0xb4, /* ISRC3INT1 */ + 0xb5, + 0xb6, + 0xb7, }; EXPORT_SYMBOL_GPL(arizona_mixer_values); @@ -275,6 +323,15 @@ const struct soc_enum arizona_lhpf4_mode = arizona_lhpf_mode_text); EXPORT_SYMBOL_GPL(arizona_lhpf4_mode); +static const char *arizona_ng_hold_text[] = { + "30ms", "120ms", "250ms", "500ms", +}; + +const struct soc_enum arizona_ng_hold = + SOC_ENUM_SINGLE(ARIZONA_NOISE_GATE_CONTROL, ARIZONA_NGATE_HOLD_SHIFT, + 4, arizona_ng_hold_text); +EXPORT_SYMBOL_GPL(arizona_ng_hold); + int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -417,6 +474,10 @@ int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id, case 147456000: val |= 6 << ARIZONA_SYSCLK_FREQ_SHIFT; break; + case 0: + dev_dbg(arizona->dev, "%s cleared\n", name); + *clk = freq; + return 0; default: return -EINVAL; } @@ -635,6 +696,9 @@ static int arizona_startup(struct snd_pcm_substream *substream, return 0; } + if (base_rate == 0) + return 0; + if (base_rate % 8000) constraint = &arizona_44k1_constraint; else @@ -645,25 +709,81 @@ static int arizona_startup(struct snd_pcm_substream *substream, constraint); } +static int arizona_hw_params_rate(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1]; + int base = dai->driver->base; + int i, sr_val; + + /* + * We will need to be more flexible than this in future, + * currently we use a single sample rate for SYSCLK. + */ + for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++) + if (arizona_sr_vals[i] == params_rate(params)) + break; + if (i == ARRAY_SIZE(arizona_sr_vals)) { + arizona_aif_err(dai, "Unsupported sample rate %dHz\n", + params_rate(params)); + return -EINVAL; + } + sr_val = i; + + switch (dai_priv->clk) { + case ARIZONA_CLK_SYSCLK: + snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1, + ARIZONA_SAMPLE_RATE_1_MASK, sr_val); + if (base) + snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, + ARIZONA_AIF1_RATE_MASK, 0); + break; + case ARIZONA_CLK_ASYNCCLK: + snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1, + ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val); + if (base) + snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, + ARIZONA_AIF1_RATE_MASK, + 8 << ARIZONA_AIF1_RATE_SHIFT); + break; + default: + arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk); + return -EINVAL; + } + + return 0; +} + static int arizona_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); - struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1]; + struct arizona *arizona = priv->arizona; int base = dai->driver->base; const int *rates; - int i; - int bclk, lrclk, wl, frame, sr_val; + int i, ret; + int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1]; + int bclk, lrclk, wl, frame, bclk_target; if (params_rate(params) % 8000) rates = &arizona_44k1_bclk_rates[0]; else rates = &arizona_48k_bclk_rates[0]; + bclk_target = snd_soc_params_to_bclk(params); + if (chan_limit && chan_limit < params_channels(params)) { + arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit); + bclk_target /= params_channels(params); + bclk_target *= chan_limit; + } + for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) { - if (rates[i] >= snd_soc_params_to_bclk(params) && + if (rates[i] >= bclk_target && rates[i] % params_rate(params) == 0) { bclk = i; break; @@ -675,16 +795,6 @@ static int arizona_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } - for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++) - if (arizona_sr_vals[i] == params_rate(params)) - break; - if (i == ARRAY_SIZE(arizona_sr_vals)) { - arizona_aif_err(dai, "Unsupported sample rate %dHz\n", - params_rate(params)); - return -EINVAL; - } - sr_val = i; - lrclk = rates[bclk] / params_rate(params); arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n", @@ -693,28 +803,9 @@ static int arizona_hw_params(struct snd_pcm_substream *substream, wl = snd_pcm_format_width(params_format(params)); frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl; - /* - * We will need to be more flexible than this in future, - * currently we use a single sample rate for SYSCLK. - */ - switch (dai_priv->clk) { - case ARIZONA_CLK_SYSCLK: - snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1, - ARIZONA_SAMPLE_RATE_1_MASK, sr_val); - snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, - ARIZONA_AIF1_RATE_MASK, 0); - break; - case ARIZONA_CLK_ASYNCCLK: - snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1, - ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val); - snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, - ARIZONA_AIF1_RATE_MASK, - 8 << ARIZONA_AIF1_RATE_SHIFT); - break; - default: - arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk); - return -EINVAL; - } + ret = arizona_hw_params_rate(substream, params, dai); + if (ret != 0) + return ret; snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL, ARIZONA_AIF1_BCLK_FREQ_MASK, bclk); @@ -789,11 +880,27 @@ static int arizona_dai_set_sysclk(struct snd_soc_dai *dai, return snd_soc_dapm_sync(&codec->dapm); } +static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate) +{ + struct snd_soc_codec *codec = dai->codec; + int base = dai->driver->base; + unsigned int reg; + + if (tristate) + reg = ARIZONA_AIF1_TRI; + else + reg = 0; + + return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, + ARIZONA_AIF1_TRI, reg); +} + const struct snd_soc_dai_ops arizona_dai_ops = { .startup = arizona_startup, .set_fmt = arizona_set_fmt, .hw_params = arizona_hw_params, .set_sysclk = arizona_dai_set_sysclk, + .set_tristate = arizona_set_tristate, }; EXPORT_SYMBOL_GPL(arizona_dai_ops); @@ -807,17 +914,6 @@ int arizona_init_dai(struct arizona_priv *priv, int id) } EXPORT_SYMBOL_GPL(arizona_init_dai); -static irqreturn_t arizona_fll_lock(int irq, void *data) -{ - struct arizona_fll *fll = data; - - arizona_fll_dbg(fll, "Lock status changed\n"); - - complete(&fll->lock); - - return IRQ_HANDLED; -} - static irqreturn_t arizona_fll_clock_ok(int irq, void *data) { struct arizona_fll *fll = data; @@ -910,7 +1006,7 @@ static int arizona_calc_fll(struct arizona_fll *fll, cfg->n = target / (ratio * Fref); - if (target % Fref) { + if (target % (ratio * Fref)) { gcd_fll = gcd(target, ratio * Fref); arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll); @@ -922,6 +1018,15 @@ static int arizona_calc_fll(struct arizona_fll *fll, cfg->lambda = 0; } + /* Round down to 16bit range with cost of accuracy lost. + * Denominator must be bigger than numerator so we only + * take care of it. + */ + while (cfg->lambda >= (1 << 16)) { + cfg->theta >>= 1; + cfg->lambda >>= 1; + } + arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n", cfg->n, cfg->theta, cfg->lambda); arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n", @@ -1057,7 +1162,6 @@ int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq, { int ret; - init_completion(&fll->lock); init_completion(&fll->ok); fll->id = id; @@ -1068,13 +1172,6 @@ int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq, snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name), "FLL%d clock OK", id); - ret = arizona_request_irq(arizona, lock_irq, fll->lock_name, - arizona_fll_lock, fll); - if (ret != 0) { - dev_err(arizona->dev, "Failed to get FLL%d lock IRQ: %d\n", - id, ret); - } - ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name, arizona_fll_clock_ok, fll); if (ret != 0) { @@ -1089,6 +1186,40 @@ int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq, } EXPORT_SYMBOL_GPL(arizona_init_fll); +/** + * arizona_set_output_mode - Set the mode of the specified output + * + * @codec: Device to configure + * @output: Output number + * @diff: True to set the output to differential mode + * + * Some systems use external analogue switches to connect more + * analogue devices to the CODEC than are supported by the device. In + * some systems this requires changing the switched output from single + * ended to differential mode dynamically at runtime, an operation + * supported using this function. + * + * Most systems have a single static configuration and should use + * platform data instead. + */ +int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff) +{ + unsigned int reg, val; + + if (output < 1 || output > 6) + return -EINVAL; + + reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8; + + if (diff) + val = ARIZONA_OUT1_MONO; + else + val = 0; + + return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val); +} +EXPORT_SYMBOL_GPL(arizona_set_output_mode); + MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support"); MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/arizona.h b/sound/soc/codecs/arizona.h index 4deebeb07177..116372c91f5d 100644 --- a/sound/soc/codecs/arizona.h +++ b/sound/soc/codecs/arizona.h @@ -66,7 +66,7 @@ struct arizona_priv { struct arizona_dai_priv dai[ARIZONA_MAX_DAI]; }; -#define ARIZONA_NUM_MIXER_INPUTS 75 +#define ARIZONA_NUM_MIXER_INPUTS 99 extern const unsigned int arizona_mixer_tlv[]; extern const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS]; @@ -176,6 +176,8 @@ extern const struct soc_enum arizona_lhpf2_mode; extern const struct soc_enum arizona_lhpf3_mode; extern const struct soc_enum arizona_lhpf4_mode; +extern const struct soc_enum arizona_ng_hold; + extern int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); @@ -195,7 +197,6 @@ struct arizona_fll { int id; unsigned int base; unsigned int vco_mult; - struct completion lock; struct completion ok; unsigned int fref; unsigned int fout; @@ -211,4 +212,7 @@ extern int arizona_set_fll(struct arizona_fll *fll, int source, extern int arizona_init_dai(struct arizona_priv *priv, int dai); +int arizona_set_output_mode(struct snd_soc_codec *codec, int output, + bool diff); + #endif diff --git a/sound/soc/codecs/cs4271.c b/sound/soc/codecs/cs4271.c index ac8742a1f25a..2415a4118dbd 100644 --- a/sound/soc/codecs/cs4271.c +++ b/sound/soc/codecs/cs4271.c @@ -167,6 +167,8 @@ struct cs4271_private { int gpio_nreset; /* GPIO that disable serial bus, if any */ int gpio_disable; + /* enable soft reset workaround */ + bool enable_soft_reset; }; /* @@ -325,6 +327,33 @@ static int cs4271_hw_params(struct snd_pcm_substream *substream, int i, ret; unsigned int ratio, val; + if (cs4271->enable_soft_reset) { + /* + * Put the codec in soft reset and back again in case it's not + * currently streaming data. This way of bringing the codec in + * sync to the current clocks is not explicitly documented in + * the data sheet, but it seems to work fine, and in contrast + * to a read hardware reset, we don't have to sync back all + * registers every time. + */ + + if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK && + !dai->capture_active) || + (substream->stream == SNDRV_PCM_STREAM_CAPTURE && + !dai->playback_active)) { + ret = snd_soc_update_bits(codec, CS4271_MODE2, + CS4271_MODE2_PDN, + CS4271_MODE2_PDN); + if (ret < 0) + return ret; + + ret = snd_soc_update_bits(codec, CS4271_MODE2, + CS4271_MODE2_PDN, 0); + if (ret < 0) + return ret; + } + } + cs4271->rate = params_rate(params); /* Configure DAC */ @@ -484,6 +513,10 @@ static int cs4271_probe(struct snd_soc_codec *codec) if (of_get_property(codec->dev->of_node, "cirrus,amutec-eq-bmutec", NULL)) amutec_eq_bmutec = true; + + if (of_get_property(codec->dev->of_node, + "cirrus,enable-soft-reset", NULL)) + cs4271->enable_soft_reset = true; } #endif @@ -492,6 +525,7 @@ static int cs4271_probe(struct snd_soc_codec *codec) gpio_nreset = cs4271plat->gpio_nreset; amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec; + cs4271->enable_soft_reset = cs4271plat->enable_soft_reset; } if (gpio_nreset >= 0) diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c index 9811a5478c87..0f6f481cec09 100644 --- a/sound/soc/codecs/cs42l52.c +++ b/sound/soc/codecs/cs42l52.c @@ -1038,7 +1038,7 @@ static void cs42l52_init_beep(struct snd_soc_codec *codec) struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec); int ret; - cs42l52->beep = input_allocate_device(); + cs42l52->beep = devm_input_allocate_device(codec->dev); if (!cs42l52->beep) { dev_err(codec->dev, "Failed to allocate beep device\n"); return; @@ -1059,7 +1059,6 @@ static void cs42l52_init_beep(struct snd_soc_codec *codec) ret = input_register_device(cs42l52->beep); if (ret != 0) { - input_free_device(cs42l52->beep); cs42l52->beep = NULL; dev_err(codec->dev, "Failed to register beep device\n"); } @@ -1076,7 +1075,6 @@ static void cs42l52_free_beep(struct snd_soc_codec *codec) struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec); device_remove_file(codec->dev, &dev_attr_beep); - input_unregister_device(cs42l52->beep); cancel_work_sync(&cs42l52->beep_work); cs42l52->beep = NULL; diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c index c9772ca3da4f..fc176044994d 100644..100755 --- a/sound/soc/codecs/max98090.c +++ b/sound/soc/codecs/max98090.c @@ -1,562 +1,2381 @@ /* * max98090.c -- MAX98090 ALSA SoC Audio driver - * based on Rev0p8 datasheet * - * Copyright (C) 2012 Renesas Solutions Corp. - * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * Based on - * - * max98095.c - * Copyright 2011 Maxim Integrated Products - * - * https://github.com/hardkernel/linux/commit/\ - * 3417d7166b17113b3b33b0a337c74d1c7cc313df#sound/soc/codecs/max98090.c - * Copyright 2011 Maxim Integrated Products + * Copyright 2011-2012 Maxim Integrated Products * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <linux/delay.h> #include <linux/i2c.h> #include <linux/module.h> +#include <linux/pm.h> +#include <linux/pm_runtime.h> #include <linux/regmap.h> +#include <linux/slab.h> +#include <sound/jack.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/tlv.h> +#include <sound/max98090.h> +#include "max98090.h" + +#include <linux/version.h> + +#define DEBUG +#define EXTMIC_METHOD +#define EXTMIC_METHOD_TEST + +/* Allows for sparsely populated register maps */ +static struct reg_default max98090_reg[] = { + { 0x00, 0x00 }, /* 00 Software Reset */ + { 0x03, 0x04 }, /* 03 Interrupt Masks */ + { 0x04, 0x00 }, /* 04 System Clock Quick */ + { 0x05, 0x00 }, /* 05 Sample Rate Quick */ + { 0x06, 0x00 }, /* 06 DAI Interface Quick */ + { 0x07, 0x00 }, /* 07 DAC Path Quick */ + { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ + { 0x09, 0x00 }, /* 09 Line to ADC Quick */ + { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ + { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ + { 0x0C, 0x00 }, /* 0C Reserved */ + { 0x0D, 0x00 }, /* 0D Input Config */ + { 0x0E, 0x1B }, /* 0E Line Input Level */ + { 0x0F, 0x00 }, /* 0F Line Config */ + + { 0x10, 0x14 }, /* 10 Mic1 Input Level */ + { 0x11, 0x14 }, /* 11 Mic2 Input Level */ + { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ + { 0x13, 0x00 }, /* 13 Digital Mic Config */ + { 0x14, 0x00 }, /* 14 Digital Mic Mode */ + { 0x15, 0x00 }, /* 15 Left ADC Mixer */ + { 0x16, 0x00 }, /* 16 Right ADC Mixer */ + { 0x17, 0x03 }, /* 17 Left ADC Level */ + { 0x18, 0x03 }, /* 18 Right ADC Level */ + { 0x19, 0x00 }, /* 19 ADC Biquad Level */ + { 0x1A, 0x00 }, /* 1A ADC Sidetone */ + { 0x1B, 0x00 }, /* 1B System Clock */ + { 0x1C, 0x00 }, /* 1C Clock Mode */ + { 0x1D, 0x00 }, /* 1D Any Clock 1 */ + { 0x1E, 0x00 }, /* 1E Any Clock 2 */ + { 0x1F, 0x00 }, /* 1F Any Clock 3 */ + + { 0x20, 0x00 }, /* 20 Any Clock 4 */ + { 0x21, 0x00 }, /* 21 Master Mode */ + { 0x22, 0x00 }, /* 22 Interface Format */ + { 0x23, 0x00 }, /* 23 TDM Format 1*/ + { 0x24, 0x00 }, /* 24 TDM Format 2*/ + { 0x25, 0x00 }, /* 25 I/O Configuration */ + { 0x26, 0x80 }, /* 26 Filter Config */ + { 0x27, 0x00 }, /* 27 DAI Playback Level */ + { 0x28, 0x00 }, /* 28 EQ Playback Level */ + { 0x29, 0x00 }, /* 29 Left HP Mixer */ + { 0x2A, 0x00 }, /* 2A Right HP Mixer */ + { 0x2B, 0x00 }, /* 2B HP Control */ + { 0x2C, 0x1A }, /* 2C Left HP Volume */ + { 0x2D, 0x1A }, /* 2D Right HP Volume */ + { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ + { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ + + { 0x30, 0x00 }, /* 30 Spk Control */ + { 0x31, 0x2C }, /* 31 Left Spk Volume */ + { 0x32, 0x2C }, /* 32 Right Spk Volume */ + { 0x33, 0x00 }, /* 33 ALC Timing */ + { 0x34, 0x00 }, /* 34 ALC Compressor */ + { 0x35, 0x00 }, /* 35 ALC Expander */ + { 0x36, 0x00 }, /* 36 ALC Gain */ + { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ + { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ + { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ + { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ + { 0x3B, 0x00 }, /* 3B Line OutR Control */ + { 0x3C, 0x15 }, /* 3C Line OutR Volume */ + { 0x3D, 0x00 }, /* 3D Jack Detect */ + { 0x3E, 0x00 }, /* 3E Input Enable */ + { 0x3F, 0x00 }, /* 3F Output Enable */ + + { 0x40, 0x00 }, /* 40 Level Control */ + { 0x41, 0x00 }, /* 41 DSP Filter Enable */ + { 0x42, 0x00 }, /* 42 Bias Control */ + { 0x43, 0x00 }, /* 43 DAC Control */ + { 0x44, 0x06 }, /* 44 ADC Control */ + { 0x45, 0x00 }, /* 45 Device Shutdown */ + { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ + { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ + { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ + { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ + { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ + { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ + { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ + { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ + { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ + { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ + + { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ + { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ + { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ + { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ + { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ + { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ + { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ + { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ + { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ + { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ + { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ + { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ + { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ + { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ + { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ + { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ + + { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ + { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ + { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ + { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ + { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ + { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ + { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ + { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ + { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ + { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ + { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ + { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ + { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ + { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ + { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ + { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ + + { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ + { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ + { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ + { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ + { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ + { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ + { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ + { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ + { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ + { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ + { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ + { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ + { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ + { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ + { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ + { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ + + { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ + { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ + { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ + { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ + { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ + { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ + { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ + { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ + { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ + { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ + { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ + { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ + { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ + { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ + { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ + { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ + + { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ + { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ + { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ + { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ + { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ + { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ + { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ + { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ + { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ + { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ + { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ + { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ + { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ + { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ + { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ + { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ + + { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ + { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ + { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ + { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ + { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ + { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ + { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ + { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ + { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ + { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ + { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ + { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ + { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ + { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ + { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ + { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ + + { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ + { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ + { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ + { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ + { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ + { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ + { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ + { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ + { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ + { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ + { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ + { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ + { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ + { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ + { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ + { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ + + { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ + { 0xC1, 0x00 }, /* C1 Record TDM Slot */ + { 0xC2, 0x00 }, /* C2 Sample Rate */ + { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ + { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ + { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ + { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ + { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ + { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ + { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ + { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ + { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ + { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ + { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ + { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ + { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ + + { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ + { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ +}; -/* - * - * MAX98090 Registers Definition - * - */ +static bool max98090_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case M98090_REG_DEVICE_STATUS: + case M98090_REG_JACK_STATUS: + case M98090_REG_REVISION_ID: + return true; + default: + return false; + } +} -/* RESET / STATUS / INTERRUPT REGISTERS */ -#define MAX98090_0x00_SW_RESET 0x00 -#define MAX98090_0x01_INT_STS 0x01 -#define MAX98090_0x02_JACK_STS 0x02 -#define MAX98090_0x03_INT_MASK 0x03 - -/* QUICK SETUP REGISTERS */ -#define MAX98090_0x04_SYS_CLK 0x04 -#define MAX98090_0x05_SAMPLE_RATE 0x05 -#define MAX98090_0x06_DAI_IF 0x06 -#define MAX98090_0x07_DAC_PATH 0x07 -#define MAX98090_0x08_MIC_TO_ADC 0x08 -#define MAX98090_0x09_LINE_TO_ADC 0x09 -#define MAX98090_0x0A_ANALOG_MIC_LOOP 0x0A -#define MAX98090_0x0B_ANALOG_LINE_LOOP 0x0B - -/* ANALOG INPUT CONFIGURATION REGISTERS */ -#define MAX98090_0x0D_INPUT_CONFIG 0x0D -#define MAX98090_0x0E_LINE_IN_LVL 0x0E -#define MAX98090_0x0F_LINI_IN_CFG 0x0F -#define MAX98090_0x10_MIC1_IN_LVL 0x10 -#define MAX98090_0x11_MIC2_IN_LVL 0x11 - -/* MICROPHONE CONFIGURATION REGISTERS */ -#define MAX98090_0x12_MIC_BIAS_VOL 0x12 -#define MAX98090_0x13_DIGITAL_MIC_CFG 0x13 -#define MAX98090_0x14_DIGITAL_MIC_MODE 0x14 - -/* ADC PATH AND CONFIGURATION REGISTERS */ -#define MAX98090_0x15_L_ADC_MIX 0x15 -#define MAX98090_0x16_R_ADC_MIX 0x16 -#define MAX98090_0x17_L_ADC_LVL 0x17 -#define MAX98090_0x18_R_ADC_LVL 0x18 -#define MAX98090_0x19_ADC_BIQUAD_LVL 0x19 -#define MAX98090_0x1A_ADC_SIDETONE 0x1A - -/* CLOCK CONFIGURATION REGISTERS */ -#define MAX98090_0x1B_SYS_CLK 0x1B -#define MAX98090_0x1C_CLK_MODE 0x1C -#define MAX98090_0x1D_ANY_CLK1 0x1D -#define MAX98090_0x1E_ANY_CLK2 0x1E -#define MAX98090_0x1F_ANY_CLK3 0x1F -#define MAX98090_0x20_ANY_CLK4 0x20 -#define MAX98090_0x21_MASTER_MODE 0x21 - -/* INTERFACE CONTROL REGISTERS */ -#define MAX98090_0x22_DAI_IF_FMT 0x22 -#define MAX98090_0x23_DAI_TDM_FMT1 0x23 -#define MAX98090_0x24_DAI_TDM_FMT2 0x24 -#define MAX98090_0x25_DAI_IO_CFG 0x25 -#define MAX98090_0x26_FILTER_CFG 0x26 -#define MAX98090_0x27_DAI_PLAYBACK_LVL 0x27 -#define MAX98090_0x28_EQ_PLAYBACK_LVL 0x28 - -/* HEADPHONE CONTROL REGISTERS */ -#define MAX98090_0x29_L_HP_MIX 0x29 -#define MAX98090_0x2A_R_HP_MIX 0x2A -#define MAX98090_0x2B_HP_CTR 0x2B -#define MAX98090_0x2C_L_HP_VOL 0x2C -#define MAX98090_0x2D_R_HP_VOL 0x2D - -/* SPEAKER CONFIGURATION REGISTERS */ -#define MAX98090_0x2E_L_SPK_MIX 0x2E -#define MAX98090_0x2F_R_SPK_MIX 0x2F -#define MAX98090_0x30_SPK_CTR 0x30 -#define MAX98090_0x31_L_SPK_VOL 0x31 -#define MAX98090_0x32_R_SPK_VOL 0x32 - -/* ALC CONFIGURATION REGISTERS */ -#define MAX98090_0x33_ALC_TIMING 0x33 -#define MAX98090_0x34_ALC_COMPRESSOR 0x34 -#define MAX98090_0x35_ALC_EXPANDER 0x35 -#define MAX98090_0x36_ALC_GAIN 0x36 - -/* RECEIVER AND LINE_OUTPUT REGISTERS */ -#define MAX98090_0x37_RCV_LOUT_L_MIX 0x37 -#define MAX98090_0x38_RCV_LOUT_L_CNTL 0x38 -#define MAX98090_0x39_RCV_LOUT_L_VOL 0x39 -#define MAX98090_0x3A_LOUT_R_MIX 0x3A -#define MAX98090_0x3B_LOUT_R_CNTL 0x3B -#define MAX98090_0x3C_LOUT_R_VOL 0x3C - -/* JACK DETECT AND ENABLE REGISTERS */ -#define MAX98090_0x3D_JACK_DETECT 0x3D -#define MAX98090_0x3E_IN_ENABLE 0x3E -#define MAX98090_0x3F_OUT_ENABLE 0x3F -#define MAX98090_0x40_LVL_CTR 0x40 -#define MAX98090_0x41_DSP_FILTER_ENABLE 0x41 - -/* BIAS AND POWER MODE CONFIGURATION REGISTERS */ -#define MAX98090_0x42_BIAS_CTR 0x42 -#define MAX98090_0x43_DAC_CTR 0x43 -#define MAX98090_0x44_ADC_CTR 0x44 -#define MAX98090_0x45_DEV_SHUTDOWN 0x45 - -/* REVISION ID REGISTER */ -#define MAX98090_0xFF_REV_ID 0xFF - -#define MAX98090_REG_MAX_CACHED 0x45 -#define MAX98090_REG_END 0xFF +static bool max98090_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case M98090_REG_DEVICE_STATUS: + case M98090_REG_JACK_STATUS: + case M98090_REG_INTERRUPT_S: + case M98090_REG_RESERVED: + case M98090_REG_LINE_INPUT_CONFIG: + case M98090_REG_LINE_INPUT_LEVEL: + case M98090_REG_INPUT_MODE: + case M98090_REG_MIC1_INPUT_LEVEL: + case M98090_REG_MIC2_INPUT_LEVEL: + case M98090_REG_MIC_BIAS_VOLTAGE: + case M98090_REG_DIGITAL_MIC_ENABLE: + case M98090_REG_DIGITAL_MIC_CONFIG: + case M98090_REG_LEFT_ADC_MIXER: + case M98090_REG_RIGHT_ADC_MIXER: + case M98090_REG_LEFT_ADC_LEVEL: + case M98090_REG_RIGHT_ADC_LEVEL: + case M98090_REG_ADC_BIQUAD_LEVEL: + case M98090_REG_ADC_SIDETONE: + case M98090_REG_SYSTEM_CLOCK: + case M98090_REG_CLOCK_MODE: + case M98090_REG_CLOCK_RATIO_NI_MSB: + case M98090_REG_CLOCK_RATIO_NI_LSB: + case M98090_REG_CLOCK_RATIO_MI_MSB: + case M98090_REG_CLOCK_RATIO_MI_LSB: + case M98090_REG_MASTER_MODE: + case M98090_REG_INTERFACE_FORMAT: + case M98090_REG_TDM_CONTROL: + case M98090_REG_TDM_FORMAT: + case M98090_REG_IO_CONFIGURATION: + case M98090_REG_FILTER_CONFIG: + case M98090_REG_DAI_PLAYBACK_LEVEL: + case M98090_REG_DAI_PLAYBACK_LEVEL_EQ: + case M98090_REG_LEFT_HP_MIXER: + case M98090_REG_RIGHT_HP_MIXER: + case M98090_REG_HP_CONTROL: + case M98090_REG_LEFT_HP_VOLUME: + case M98090_REG_RIGHT_HP_VOLUME: + case M98090_REG_LEFT_SPK_MIXER: + case M98090_REG_RIGHT_SPK_MIXER: + case M98090_REG_SPK_CONTROL: + case M98090_REG_LEFT_SPK_VOLUME: + case M98090_REG_RIGHT_SPK_VOLUME: + case M98090_REG_DRC_TIMING: + case M98090_REG_DRC_COMPRESSOR: + case M98090_REG_DRC_EXPANDER: + case M98090_REG_DRC_GAIN: + case M98090_REG_RCV_LOUTL_MIXER: + case M98090_REG_RCV_LOUTL_CONTROL: + case M98090_REG_RCV_LOUTL_VOLUME: + case M98090_REG_LOUTR_MIXER: + case M98090_REG_LOUTR_CONTROL: + case M98090_REG_LOUTR_VOLUME: + case M98090_REG_JACK_DETECT: + case M98090_REG_INPUT_ENABLE: + case M98090_REG_OUTPUT_ENABLE: + case M98090_REG_LEVEL_CONTROL: + case M98090_REG_DSP_FILTER_ENABLE: + case M98090_REG_BIAS_CONTROL: + case M98090_REG_DAC_CONTROL: + case M98090_REG_ADC_CONTROL: + case M98090_REG_DEVICE_SHUTDOWN: + case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68: + case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E: + case M98090_REG_DMIC3_VOLUME: + case M98090_REG_DMIC4_VOLUME: + case M98090_REG_DMIC34_BQ_PREATTEN: + case M98090_REG_RECORD_TDM_SLOT: + case M98090_REG_SAMPLE_RATE: + case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E: + return true; + default: + return false; + } +} -/* - * - * MAX98090 Registers Bit Fields - * - */ +static int max98090_reset(struct max98090_priv *max98090) +{ + int ret; -/* MAX98090_0x06_DAI_IF */ -#define MAX98090_DAI_IF_MASK 0x3F -#define MAX98090_RJ_M (1 << 5) -#define MAX98090_RJ_S (1 << 4) -#define MAX98090_LJ_M (1 << 3) -#define MAX98090_LJ_S (1 << 2) -#define MAX98090_I2S_M (1 << 1) -#define MAX98090_I2S_S (1 << 0) - -/* MAX98090_0x45_DEV_SHUTDOWN */ -#define MAX98090_SHDNRUN (1 << 7) - -/* codec private data */ -struct max98090_priv { - struct regmap *regmap; -}; - -static const struct reg_default max98090_reg_defaults[] = { - /* RESET / STATUS / INTERRUPT REGISTERS */ - {MAX98090_0x00_SW_RESET, 0x00}, - {MAX98090_0x01_INT_STS, 0x00}, - {MAX98090_0x02_JACK_STS, 0x00}, - {MAX98090_0x03_INT_MASK, 0x04}, - - /* QUICK SETUP REGISTERS */ - {MAX98090_0x04_SYS_CLK, 0x00}, - {MAX98090_0x05_SAMPLE_RATE, 0x00}, - {MAX98090_0x06_DAI_IF, 0x00}, - {MAX98090_0x07_DAC_PATH, 0x00}, - {MAX98090_0x08_MIC_TO_ADC, 0x00}, - {MAX98090_0x09_LINE_TO_ADC, 0x00}, - {MAX98090_0x0A_ANALOG_MIC_LOOP, 0x00}, - {MAX98090_0x0B_ANALOG_LINE_LOOP, 0x00}, - - /* ANALOG INPUT CONFIGURATION REGISTERS */ - {MAX98090_0x0D_INPUT_CONFIG, 0x00}, - {MAX98090_0x0E_LINE_IN_LVL, 0x1B}, - {MAX98090_0x0F_LINI_IN_CFG, 0x00}, - {MAX98090_0x10_MIC1_IN_LVL, 0x11}, - {MAX98090_0x11_MIC2_IN_LVL, 0x11}, - - /* MICROPHONE CONFIGURATION REGISTERS */ - {MAX98090_0x12_MIC_BIAS_VOL, 0x00}, - {MAX98090_0x13_DIGITAL_MIC_CFG, 0x00}, - {MAX98090_0x14_DIGITAL_MIC_MODE, 0x00}, - - /* ADC PATH AND CONFIGURATION REGISTERS */ - {MAX98090_0x15_L_ADC_MIX, 0x00}, - {MAX98090_0x16_R_ADC_MIX, 0x00}, - {MAX98090_0x17_L_ADC_LVL, 0x03}, - {MAX98090_0x18_R_ADC_LVL, 0x03}, - {MAX98090_0x19_ADC_BIQUAD_LVL, 0x00}, - {MAX98090_0x1A_ADC_SIDETONE, 0x00}, - - /* CLOCK CONFIGURATION REGISTERS */ - {MAX98090_0x1B_SYS_CLK, 0x00}, - {MAX98090_0x1C_CLK_MODE, 0x00}, - {MAX98090_0x1D_ANY_CLK1, 0x00}, - {MAX98090_0x1E_ANY_CLK2, 0x00}, - {MAX98090_0x1F_ANY_CLK3, 0x00}, - {MAX98090_0x20_ANY_CLK4, 0x00}, - {MAX98090_0x21_MASTER_MODE, 0x00}, - - /* INTERFACE CONTROL REGISTERS */ - {MAX98090_0x22_DAI_IF_FMT, 0x00}, - {MAX98090_0x23_DAI_TDM_FMT1, 0x00}, - {MAX98090_0x24_DAI_TDM_FMT2, 0x00}, - {MAX98090_0x25_DAI_IO_CFG, 0x00}, - {MAX98090_0x26_FILTER_CFG, 0x80}, - {MAX98090_0x27_DAI_PLAYBACK_LVL, 0x00}, - {MAX98090_0x28_EQ_PLAYBACK_LVL, 0x00}, - - /* HEADPHONE CONTROL REGISTERS */ - {MAX98090_0x29_L_HP_MIX, 0x00}, - {MAX98090_0x2A_R_HP_MIX, 0x00}, - {MAX98090_0x2B_HP_CTR, 0x00}, - {MAX98090_0x2C_L_HP_VOL, 0x1A}, - {MAX98090_0x2D_R_HP_VOL, 0x1A}, - - /* SPEAKER CONFIGURATION REGISTERS */ - {MAX98090_0x2E_L_SPK_MIX, 0x00}, - {MAX98090_0x2F_R_SPK_MIX, 0x00}, - {MAX98090_0x30_SPK_CTR, 0x00}, - {MAX98090_0x31_L_SPK_VOL, 0x2C}, - {MAX98090_0x32_R_SPK_VOL, 0x2C}, - - /* ALC CONFIGURATION REGISTERS */ - {MAX98090_0x33_ALC_TIMING, 0x00}, - {MAX98090_0x34_ALC_COMPRESSOR, 0x00}, - {MAX98090_0x35_ALC_EXPANDER, 0x00}, - {MAX98090_0x36_ALC_GAIN, 0x00}, - - /* RECEIVER AND LINE_OUTPUT REGISTERS */ - {MAX98090_0x37_RCV_LOUT_L_MIX, 0x00}, - {MAX98090_0x38_RCV_LOUT_L_CNTL, 0x00}, - {MAX98090_0x39_RCV_LOUT_L_VOL, 0x15}, - {MAX98090_0x3A_LOUT_R_MIX, 0x00}, - {MAX98090_0x3B_LOUT_R_CNTL, 0x00}, - {MAX98090_0x3C_LOUT_R_VOL, 0x15}, - - /* JACK DETECT AND ENABLE REGISTERS */ - {MAX98090_0x3D_JACK_DETECT, 0x00}, - {MAX98090_0x3E_IN_ENABLE, 0x00}, - {MAX98090_0x3F_OUT_ENABLE, 0x00}, - {MAX98090_0x40_LVL_CTR, 0x00}, - {MAX98090_0x41_DSP_FILTER_ENABLE, 0x00}, - - /* BIAS AND POWER MODE CONFIGURATION REGISTERS */ - {MAX98090_0x42_BIAS_CTR, 0x00}, - {MAX98090_0x43_DAC_CTR, 0x00}, - {MAX98090_0x44_ADC_CTR, 0x06}, - {MAX98090_0x45_DEV_SHUTDOWN, 0x00}, + /* Reset the codec by writing to this write-only reset register */ + ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, + M98090_SWRESET_MASK); + if (ret < 0) { + dev_err(max98090->codec->dev, + "Failed to reset codec: %d\n", ret); + return ret; + } + + msleep(20); + return ret; +} + +static const unsigned int max98090_micboost_tlv[] = { + TLV_DB_RANGE_HEAD(2), + 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), + 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), +}; + +static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); + +static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, + -600, 600, 0); + +static const unsigned int max98090_line_tlv[] = { + TLV_DB_RANGE_HEAD(2), + 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), + 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), +}; + +static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); +static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); + +static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); +static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); + +static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0); + +static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0); +static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); +static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); +static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); + +static const unsigned int max98090_mixout_tlv[] = { + TLV_DB_RANGE_HEAD(2), + 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), + 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), }; static const unsigned int max98090_hp_tlv[] = { TLV_DB_RANGE_HEAD(5), - 0x0, 0x6, TLV_DB_SCALE_ITEM(-6700, 400, 0), - 0x7, 0xE, TLV_DB_SCALE_ITEM(-4000, 300, 0), - 0xF, 0x15, TLV_DB_SCALE_ITEM(-1700, 200, 0), - 0x16, 0x1B, TLV_DB_SCALE_ITEM(-400, 100, 0), - 0x1C, 0x1F, TLV_DB_SCALE_ITEM(150, 50, 0), + 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), + 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), + 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), + 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), + 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), }; -static struct snd_kcontrol_new max98090_snd_controls[] = { - SOC_DOUBLE_R_TLV("Headphone Volume", MAX98090_0x2C_L_HP_VOL, - MAX98090_0x2D_R_HP_VOL, 0, 31, 0, max98090_hp_tlv), +static const unsigned int max98090_spk_tlv[] = { + TLV_DB_RANGE_HEAD(5), + 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), + 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), + 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), + 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), + 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0), }; -/* Left HeadPhone Mixer Switch */ -static struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { - SOC_DAPM_SINGLE("DACR Switch", MAX98090_0x29_L_HP_MIX, 1, 1, 0), - SOC_DAPM_SINGLE("DACL Switch", MAX98090_0x29_L_HP_MIX, 0, 1, 0), +static const unsigned int max98090_rcv_lout_tlv[] = { + TLV_DB_RANGE_HEAD(5), + 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), + 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), + 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), + 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), + 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), }; -/* Right HeadPhone Mixer Switch */ -static struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { - SOC_DAPM_SINGLE("DACR Switch", MAX98090_0x2A_R_HP_MIX, 1, 1, 0), - SOC_DAPM_SINGLE("DACL Switch", MAX98090_0x2A_R_HP_MIX, 0, 1, 0), +static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int mask = (1 << fls(mc->max)) - 1; + unsigned int val = snd_soc_read(codec, mc->reg); + unsigned int *select; + + switch (mc->reg) { + case M98090_REG_MIC1_INPUT_LEVEL: + select = &(max98090->pa1en); + break; + case M98090_REG_MIC2_INPUT_LEVEL: + select = &(max98090->pa2en); + break; + case M98090_REG_ADC_SIDETONE: + select = &(max98090->sidetone); + break; + default: + return -EINVAL; + } + + val = (val >> mc->shift) & mask; + + if (val >= 1) { + /* If on, return the volume */ + val = val - 1; + *select = val; + } else { + /* If off, return last stored value */ + val = *select; + } + + ucontrol->value.integer.value[0] = val; + return 0; +} + +static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int mask = (1 << fls(mc->max)) - 1; + unsigned int sel = ucontrol->value.integer.value[0]; + unsigned int val = snd_soc_read(codec, mc->reg); + unsigned int *select; + + switch (mc->reg) { + case M98090_REG_MIC1_INPUT_LEVEL: + select = &(max98090->pa1en); + break; + case M98090_REG_MIC2_INPUT_LEVEL: + select = &(max98090->pa2en); + break; + case M98090_REG_ADC_SIDETONE: + select = &(max98090->sidetone); + break; + default: + return -EINVAL; + } + + val = (val >> mc->shift) & mask; + + *select = sel; + + /* Setting a volume is only valid if it is already On */ + if (val >= 1) { + sel = sel + 1; + } else { + /* Write what was already there */ + sel = val; + } + + snd_soc_update_bits(codec, mc->reg, + mask << mc->shift, + sel << mc->shift); + + return 0; +} + +static const char * max98090_perf_pwr_text[] = + { "High Performance", "Low Power" }; +static const char * max98090_pwr_perf_text[] = + { "Low Power", "High Performance" }; + +static const struct soc_enum max98090_vcmbandgap_enum = + SOC_ENUM_SINGLE(M98090_REG_BIAS_CONTROL, M98090_VCM_MODE_SHIFT, + ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text); + +static const char * max98090_osr128_text[] = { "64*fs", "128*fs" }; + +static const struct soc_enum max98090_osr128_enum = + SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_OSR128_SHIFT, + ARRAY_SIZE(max98090_osr128_text), max98090_osr128_text); + +static const char *max98090_mode_text[] = { "Voice", "Music" }; + +static const struct soc_enum max98090_mode_enum = + SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, M98090_MODE_SHIFT, + ARRAY_SIZE(max98090_mode_text), max98090_mode_text); + +static const struct soc_enum max98090_filter_dmic34mode_enum = + SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, + M98090_FLT_DMIC34MODE_SHIFT, + ARRAY_SIZE(max98090_mode_text), max98090_mode_text); + +static const char * max98090_drcatk_text[] = + { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; + +static const struct soc_enum max98090_drcatk_enum = + SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCATK_SHIFT, + ARRAY_SIZE(max98090_drcatk_text), max98090_drcatk_text); + +static const char * max98090_drcrls_text[] = + { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; + +static const struct soc_enum max98090_drcrls_enum = + SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCRLS_SHIFT, + ARRAY_SIZE(max98090_drcrls_text), max98090_drcrls_text); + +static const char * max98090_alccmp_text[] = + { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; + +static const struct soc_enum max98090_alccmp_enum = + SOC_ENUM_SINGLE(M98090_REG_DRC_COMPRESSOR, M98090_DRCCMP_SHIFT, + ARRAY_SIZE(max98090_alccmp_text), max98090_alccmp_text); + +static const char * max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; + +static const struct soc_enum max98090_drcexp_enum = + SOC_ENUM_SINGLE(M98090_REG_DRC_EXPANDER, M98090_DRCEXP_SHIFT, + ARRAY_SIZE(max98090_drcexp_text), max98090_drcexp_text); + +static const struct soc_enum max98090_dac_perfmode_enum = + SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_PERFMODE_SHIFT, + ARRAY_SIZE(max98090_perf_pwr_text), max98090_perf_pwr_text); + +static const struct soc_enum max98090_dachp_enum = + SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_DACHP_SHIFT, + ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text); + +static const struct soc_enum max98090_adchp_enum = + SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_ADCHP_SHIFT, + ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text); + +static const struct snd_kcontrol_new max98090_snd_controls[] = { + SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), + + SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, + M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), + + SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", + M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, + M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, + max98090_put_enab_tlv, max98090_micboost_tlv), + + SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", + M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, + M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, + max98090_put_enab_tlv, max98090_micboost_tlv), + + SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, + M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, + max98090_mic_tlv), + + SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, + M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, + max98090_mic_tlv), + + SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", + M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, + M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), + + SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", + M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, + M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), + + SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, + M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, + max98090_line_tlv), + + SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, + M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, + max98090_line_tlv), + + SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, + M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), + SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, + M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), + + SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, + M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, + max98090_avg_tlv), + SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, + M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, + max98090_avg_tlv), + + SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, + M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, + max98090_av_tlv), + SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, + M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, + max98090_av_tlv), + + SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), + SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, + M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), + SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), + + SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, + M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), + SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, + M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), + SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, + M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), + SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, + M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), + SOC_ENUM("Filter Mode", max98090_mode_enum), + SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, + M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), + SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, + M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), + SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, + M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), + SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", + M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, + M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, + max98090_put_enab_tlv, max98090_micboost_tlv), + SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, + M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, + max98090_dvg_tlv), + SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, + M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, + max98090_dv_tlv), + SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), + SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, + M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), + SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, + M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), + SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, + M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), + SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, + M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, + 1), + SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, + M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, + max98090_dv_tlv), + + SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, + M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), + SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), + SOC_ENUM("ALC Release Time", max98090_drcrls_enum), + SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, + M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, + max98090_alcmakeup_tlv), + SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), + SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), + SOC_SINGLE_TLV("ALC Compression Threshold Volume", + M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, + M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), + SOC_SINGLE_TLV("ALC Expansion Threshold Volume", + M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, + M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), + + SOC_ENUM("DAC HP Playback Performance Mode", + max98090_dac_perfmode_enum), + SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), + + SOC_SINGLE_TLV("Headphone Left Mixer Volume", + M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, + M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), + SOC_SINGLE_TLV("Headphone Right Mixer Volume", + M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, + M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), + + SOC_SINGLE_TLV("Speaker Left Mixer Volume", + M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, + M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), + SOC_SINGLE_TLV("Speaker Right Mixer Volume", + M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, + M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), + + SOC_SINGLE_TLV("Receiver Left Mixer Volume", + M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, + M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), + SOC_SINGLE_TLV("Receiver Right Mixer Volume", + M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, + M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), + + SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, + M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, + M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), + + SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", + M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, + M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, + 0, max98090_spk_tlv), + + SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, + M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, + M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), + + SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, + M98090_HPLM_SHIFT, 1, 1), + SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, + M98090_HPRM_SHIFT, 1, 1), + + SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, + M98090_SPLM_SHIFT, 1, 1), + SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, + M98090_SPRM_SHIFT, 1, 1), + + SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, + M98090_RCVLM_SHIFT, 1, 1), + SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, + M98090_RCVRM_SHIFT, 1, 1), + + SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, + M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), + SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, + M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), + SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, + M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), + + SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), + SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, + M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), }; -static struct snd_soc_dapm_widget max98090_dapm_widgets[] = { - /* Output */ +static const struct snd_kcontrol_new max98091_snd_controls[] = { + + SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, + M98090_DMIC34_ZEROPAD_SHIFT, + M98090_DMIC34_ZEROPAD_NUM - 1, 0), + + SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), + SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, + M98090_FLT_DMIC34HPF_SHIFT, + M98090_FLT_DMIC34HPF_NUM - 1, 0), + + SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, + M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, + max98090_avg_tlv), + SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, + M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, + max98090_avg_tlv), + + SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, + M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, + max98090_av_tlv), + SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, + M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, + max98090_av_tlv), + + SND_SOC_BYTES("DMIC34 Biquad Coefficients", + M98090_REG_DMIC34_BIQUAD_BASE, 15), + SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, + M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), + + SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", + M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, + M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), +}; + +static int max98090_micinput_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + + unsigned int val = snd_soc_read(codec, w->reg); + + if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) + val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; + else + val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; + + + if (val >= 1) { + if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { + max98090->pa1en = val - 1; /* Update for volatile */ + } else { + max98090->pa2en = val - 1; /* Update for volatile */ + } + } + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + /* If turning on, set to most recently selected volume */ + if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) + val = max98090->pa1en + 1; + else + val = max98090->pa2en + 1; + break; + case SND_SOC_DAPM_POST_PMD: + /* If turning off, turn off */ + val = 0; + break; + default: + return -EINVAL; + } + + if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) + snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK, + val << M98090_MIC_PA1EN_SHIFT); + else + snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK, + val << M98090_MIC_PA2EN_SHIFT); + + return 0; +} + +static const char *mic1_mux_text[] = { "IN12", "IN56" }; + +static const struct soc_enum mic1_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC1_SHIFT, + ARRAY_SIZE(mic1_mux_text), mic1_mux_text); + +static const struct snd_kcontrol_new max98090_mic1_mux = + SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); + +static const char *mic2_mux_text[] = { "IN34", "IN56" }; + +static const struct soc_enum mic2_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC2_SHIFT, + ARRAY_SIZE(mic2_mux_text), mic2_mux_text); + +static const struct snd_kcontrol_new max98090_mic2_mux = + SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); + +static const char * max98090_micpre_text[] = { "Off", "On" }; + +static const struct soc_enum max98090_pa1en_enum = + SOC_ENUM_SINGLE(M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, + ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text); + +static const struct soc_enum max98090_pa2en_enum = + SOC_ENUM_SINGLE(M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, + ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text); + +/* LINEA mixer switch */ +static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { + SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, + M98090_IN1SEEN_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, + M98090_IN3SEEN_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, + M98090_IN5SEEN_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, + M98090_IN34DIFF_SHIFT, 1, 0), +}; + +/* LINEB mixer switch */ +static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { + SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, + M98090_IN2SEEN_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, + M98090_IN4SEEN_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, + M98090_IN6SEEN_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, + M98090_IN56DIFF_SHIFT, 1, 0), +}; + +/* Left ADC mixer switch */ +static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { + SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, + M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, + M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, + M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, + M98090_MIXADL_LINEA_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, + M98090_MIXADL_LINEB_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, + M98090_MIXADL_MIC1_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, + M98090_MIXADL_MIC2_SHIFT, 1, 0), +}; + +/* Right ADC mixer switch */ +static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { + SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, + M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, + M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), + SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, + M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, + M98090_MIXADR_LINEA_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, + M98090_MIXADR_LINEB_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, + M98090_MIXADR_MIC1_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, + M98090_MIXADR_MIC2_SHIFT, 1, 0), +}; + +static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; + +static const struct soc_enum ltenl_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT, + ARRAY_SIZE(lten_mux_text), lten_mux_text); + +static const struct soc_enum ltenr_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT, + ARRAY_SIZE(lten_mux_text), lten_mux_text); + +static const struct snd_kcontrol_new max98090_ltenl_mux = + SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); + +static const struct snd_kcontrol_new max98090_ltenr_mux = + SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); + +static const char *lben_mux_text[] = { "Normal", "Loopback" }; + +static const struct soc_enum lbenl_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT, + ARRAY_SIZE(lben_mux_text), lben_mux_text); + +static const struct soc_enum lbenr_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT, + ARRAY_SIZE(lben_mux_text), lben_mux_text); + +static const struct snd_kcontrol_new max98090_lbenl_mux = + SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); + +static const struct snd_kcontrol_new max98090_lbenr_mux = + SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); + +static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; + +static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; + +static const struct soc_enum stenl_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSL_SHIFT, + ARRAY_SIZE(stenl_mux_text), stenl_mux_text); + +static const struct soc_enum stenr_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSR_SHIFT, + ARRAY_SIZE(stenr_mux_text), stenr_mux_text); + +static const struct snd_kcontrol_new max98090_stenl_mux = + SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); + +static const struct snd_kcontrol_new max98090_stenr_mux = + SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); + +/* Left speaker mixer switch */ +static const struct + snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, + M98090_MIXSPL_DACL_SHIFT, 1, 0), + SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, + M98090_MIXSPL_DACR_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, + M98090_MIXSPL_LINEA_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, + M98090_MIXSPL_LINEB_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, + M98090_MIXSPL_MIC1_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, + M98090_MIXSPL_MIC2_SHIFT, 1, 0), +}; + +/* Right speaker mixer switch */ +static const struct + snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, + M98090_MIXSPR_DACL_SHIFT, 1, 0), + SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, + M98090_MIXSPR_DACR_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, + M98090_MIXSPR_LINEA_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, + M98090_MIXSPR_LINEB_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, + M98090_MIXSPR_MIC1_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, + M98090_MIXSPR_MIC2_SHIFT, 1, 0), +}; + +/* Left headphone mixer switch */ +static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, + M98090_MIXHPL_DACL_SHIFT, 1, 0), + SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, + M98090_MIXHPL_DACR_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, + M98090_MIXHPL_LINEA_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, + M98090_MIXHPL_LINEB_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, + M98090_MIXHPL_MIC1_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, + M98090_MIXHPL_MIC2_SHIFT, 1, 0), +}; + +/* Right headphone mixer switch */ +static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, + M98090_MIXHPR_DACL_SHIFT, 1, 0), + SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, + M98090_MIXHPR_DACR_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, + M98090_MIXHPR_LINEA_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, + M98090_MIXHPR_LINEB_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, + M98090_MIXHPR_MIC1_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, + M98090_MIXHPR_MIC2_SHIFT, 1, 0), +}; + +/* Left receiver mixer switch */ +static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, + M98090_MIXRCVL_DACL_SHIFT, 1, 0), + SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, + M98090_MIXRCVL_DACR_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, + M98090_MIXRCVL_LINEA_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, + M98090_MIXRCVL_LINEB_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, + M98090_MIXRCVL_MIC1_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, + M98090_MIXRCVL_MIC2_SHIFT, 1, 0), +}; + +/* Right receiver mixer switch */ +static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { + SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, + M98090_MIXRCVR_DACL_SHIFT, 1, 0), + SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, + M98090_MIXRCVR_DACR_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, + M98090_MIXRCVR_LINEA_SHIFT, 1, 0), + SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, + M98090_MIXRCVR_LINEB_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, + M98090_MIXRCVR_MIC1_SHIFT, 1, 0), + SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, + M98090_MIXRCVR_MIC2_SHIFT, 1, 0), +}; + +static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; + +static const struct soc_enum linmod_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_LOUTR_MIXER, M98090_LINMOD_SHIFT, + ARRAY_SIZE(linmod_mux_text), linmod_mux_text); + +static const struct snd_kcontrol_new max98090_linmod_mux = + SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); + +static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; + +/* + * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable + */ +static const struct soc_enum mixhplsel_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPLSEL_SHIFT, + ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text); + +static const struct snd_kcontrol_new max98090_mixhplsel_mux = + SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); + +static const struct soc_enum mixhprsel_mux_enum = + SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPRSEL_SHIFT, + ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text); + +static const struct snd_kcontrol_new max98090_mixhprsel_mux = + SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); + +static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { + + SND_SOC_DAPM_INPUT("MIC1"), + SND_SOC_DAPM_INPUT("MIC2"), + SND_SOC_DAPM_INPUT("DMICL"), + SND_SOC_DAPM_INPUT("DMICR"), + SND_SOC_DAPM_INPUT("IN1"), + SND_SOC_DAPM_INPUT("IN2"), + SND_SOC_DAPM_INPUT("IN3"), + SND_SOC_DAPM_INPUT("IN4"), + SND_SOC_DAPM_INPUT("IN5"), + SND_SOC_DAPM_INPUT("IN6"), + SND_SOC_DAPM_INPUT("IN12"), + SND_SOC_DAPM_INPUT("IN34"), + SND_SOC_DAPM_INPUT("IN56"), + + SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, + M98090_MBEN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, + M98090_SHDNN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, + M98090_SDIEN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, + M98090_SDOEN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, + M98090_DIGMICL_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, + M98090_DIGMICR_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, + M98090_AHPF_SHIFT, 0, NULL, 0), + +/* + * Note: Sysclk and misc power supplies are taken care of by SHDN + */ + + SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, + 0, 0, &max98090_mic1_mux), + + SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, + 0, 0, &max98090_mic2_mux), + + SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, + M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, + M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, + &max98090_linea_mixer_controls[0], + ARRAY_SIZE(max98090_linea_mixer_controls)), + + SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, + &max98090_lineb_mixer_controls[0], + ARRAY_SIZE(max98090_lineb_mixer_controls)), + + SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, + M98090_LINEAEN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, + M98090_LINEBEN_SHIFT, 0, NULL, 0), + + SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, + &max98090_left_adc_mixer_controls[0], + ARRAY_SIZE(max98090_left_adc_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, + &max98090_right_adc_mixer_controls[0], + ARRAY_SIZE(max98090_right_adc_mixer_controls)), + + SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE, + M98090_ADLEN_SHIFT, 0), + SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE, + M98090_ADREN_SHIFT, 0), + + SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, + SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, + SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, + 0, 0, &max98090_lbenl_mux), + + SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, + 0, 0, &max98090_lbenr_mux), + + SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, + 0, 0, &max98090_ltenl_mux), + + SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, + 0, 0, &max98090_ltenr_mux), + + SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, + 0, 0, &max98090_stenl_mux), + + SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, + 0, 0, &max98090_stenr_mux), + + SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, + M98090_DALEN_SHIFT, 0), + SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, + M98090_DAREN_SHIFT, 0), + + SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, + &max98090_left_hp_mixer_controls[0], + ARRAY_SIZE(max98090_left_hp_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, + &max98090_right_hp_mixer_controls[0], + ARRAY_SIZE(max98090_right_hp_mixer_controls)), + + SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, + &max98090_left_speaker_mixer_controls[0], + ARRAY_SIZE(max98090_left_speaker_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, + &max98090_right_speaker_mixer_controls[0], + ARRAY_SIZE(max98090_right_speaker_mixer_controls)), + + SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, + &max98090_left_rcv_mixer_controls[0], + ARRAY_SIZE(max98090_left_rcv_mixer_controls)), + + SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, + &max98090_right_rcv_mixer_controls[0], + ARRAY_SIZE(max98090_right_rcv_mixer_controls)), + + SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER, + M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux), + + SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL, + M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux), + + SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL, + M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux), + + SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, + M98090_HPLEN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, + M98090_HPREN_SHIFT, 0, NULL, 0), + + SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, + M98090_SPLEN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, + M98090_SPREN_SHIFT, 0, NULL, 0), + + SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, + M98090_RCVLEN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, + M98090_RCVREN_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_OUTPUT("HPL"), SND_SOC_DAPM_OUTPUT("HPR"), + SND_SOC_DAPM_OUTPUT("SPKL"), + SND_SOC_DAPM_OUTPUT("SPKR"), + SND_SOC_DAPM_OUTPUT("RCVL"), + SND_SOC_DAPM_OUTPUT("RCVR"), +}; + +static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { - /* PGA */ - SND_SOC_DAPM_PGA("HPL Out", MAX98090_0x3F_OUT_ENABLE, 7, 0, NULL, 0), - SND_SOC_DAPM_PGA("HPR Out", MAX98090_0x3F_OUT_ENABLE, 6, 0, NULL, 0), + SND_SOC_DAPM_INPUT("DMIC3"), + SND_SOC_DAPM_INPUT("DMIC4"), - /* Mixer */ - SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0, - max98090_left_hp_mixer_controls, - ARRAY_SIZE(max98090_left_hp_mixer_controls)), + SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, + M98090_DIGMIC3_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, + M98090_DIGMIC4_SHIFT, 0, NULL, 0), +}; - SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0, - max98090_right_hp_mixer_controls, - ARRAY_SIZE(max98090_right_hp_mixer_controls)), +static const struct snd_soc_dapm_route max98090_dapm_routes[] = { + + {"MIC1 Input", NULL, "MIC1"}, + {"MIC2 Input", NULL, "MIC2"}, + + {"DMICL", NULL, "DMICL_ENA"}, + {"DMICR", NULL, "DMICR_ENA"}, + {"DMICL", NULL, "AHPF"}, + {"DMICR", NULL, "AHPF"}, + + /* MIC1 input mux */ + {"MIC1 Mux", "IN12", "IN12"}, + {"MIC1 Mux", "IN56", "IN56"}, + + /* MIC2 input mux */ + {"MIC2 Mux", "IN34", "IN34"}, + {"MIC2 Mux", "IN56", "IN56"}, + + {"MIC1 Input", NULL, "MIC1 Mux"}, + {"MIC2 Input", NULL, "MIC2 Mux"}, + + /* Left ADC input mixer */ + {"Left ADC Mixer", "IN12 Switch", "IN12"}, + {"Left ADC Mixer", "IN34 Switch", "IN34"}, + {"Left ADC Mixer", "IN56 Switch", "IN56"}, + {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, + {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, + {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, + {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, + + /* Right ADC input mixer */ + {"Right ADC Mixer", "IN12 Switch", "IN12"}, + {"Right ADC Mixer", "IN34 Switch", "IN34"}, + {"Right ADC Mixer", "IN56 Switch", "IN56"}, + {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, + {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, + {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, + {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, + + /* Line A input mixer */ + {"LINEA Mixer", "IN1 Switch", "IN1"}, + {"LINEA Mixer", "IN3 Switch", "IN3"}, + {"LINEA Mixer", "IN5 Switch", "IN5"}, + {"LINEA Mixer", "IN34 Switch", "IN34"}, + + /* Line B input mixer */ + {"LINEB Mixer", "IN2 Switch", "IN2"}, + {"LINEB Mixer", "IN4 Switch", "IN4"}, + {"LINEB Mixer", "IN6 Switch", "IN6"}, + {"LINEB Mixer", "IN56 Switch", "IN56"}, + + {"LINEA Input", NULL, "LINEA Mixer"}, + {"LINEB Input", NULL, "LINEB Mixer"}, + + /* Inputs */ + {"ADCL", NULL, "Left ADC Mixer"}, + {"ADCR", NULL, "Right ADC Mixer"}, + {"ADCL", NULL, "SHDN"}, + {"ADCR", NULL, "SHDN"}, + + {"LBENL Mux", "Normal", "ADCL"}, + {"LBENL Mux", "Normal", "DMICL"}, + {"LBENL Mux", "Loopback", "LTENL Mux"}, + {"LBENR Mux", "Normal", "ADCR"}, + {"LBENR Mux", "Normal", "DMICR"}, + {"LBENR Mux", "Loopback", "LTENR Mux"}, + + {"AIFOUTL", NULL, "LBENL Mux"}, + {"AIFOUTR", NULL, "LBENR Mux"}, + {"AIFOUTL", NULL, "SHDN"}, + {"AIFOUTR", NULL, "SHDN"}, + {"AIFOUTL", NULL, "SDOEN"}, + {"AIFOUTR", NULL, "SDOEN"}, + + {"LTENL Mux", "Normal", "AIFINL"}, + {"LTENL Mux", "Loopthrough", "LBENL Mux"}, + {"LTENR Mux", "Normal", "AIFINR"}, + {"LTENR Mux", "Loopthrough", "LBENR Mux"}, + + {"DACL", NULL, "LTENL Mux"}, + {"DACR", NULL, "LTENR Mux"}, + + {"STENL Mux", "Sidetone Left", "ADCL"}, + {"STENL Mux", "Sidetone Left", "DMICL"}, + {"STENR Mux", "Sidetone Right", "ADCR"}, + {"STENR Mux", "Sidetone Right", "DMICR"}, + {"DACL", "NULL", "STENL Mux"}, + {"DACR", "NULL", "STENL Mux"}, + + {"AIFINL", NULL, "SHDN"}, + {"AIFINR", NULL, "SHDN"}, + {"AIFINL", NULL, "SDIEN"}, + {"AIFINR", NULL, "SDIEN"}, + {"DACL", NULL, "SHDN"}, + {"DACR", NULL, "SHDN"}, + + /* Left headphone output mixer */ + {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, + {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, + {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, + {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, + {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, + {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, + + /* Right headphone output mixer */ + {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, + {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, + {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, + {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, + {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, + {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, + + /* Left speaker output mixer */ + {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, + {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, + {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, + {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, + {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, + {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, + + /* Right speaker output mixer */ + {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, + {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, + {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, + {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, + {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, + {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, + + /* Left Receiver output mixer */ + {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, + {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, + {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, + {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, + {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, + {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, + + /* Right Receiver output mixer */ + {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, + {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, + {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, + {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, + {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, + {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, + + {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, + + /* + * Disable this for lowest power if bypassing + * the DAC with an analog signal + */ + {"HP Left Out", NULL, "DACL"}, + {"HP Left Out", NULL, "MIXHPLSEL Mux"}, + + {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, + + /* + * Disable this for lowest power if bypassing + * the DAC with an analog signal + */ + {"HP Right Out", NULL, "DACR"}, + {"HP Right Out", NULL, "MIXHPRSEL Mux"}, + + {"SPK Left Out", NULL, "Left Speaker Mixer"}, + {"SPK Right Out", NULL, "Right Speaker Mixer"}, + {"RCV Left Out", NULL, "Left Receiver Mixer"}, + + {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, + {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, + {"RCV Right Out", NULL, "LINMOD Mux"}, + + {"HPL", NULL, "HP Left Out"}, + {"HPR", NULL, "HP Right Out"}, + {"SPKL", NULL, "SPK Left Out"}, + {"SPKR", NULL, "SPK Right Out"}, + {"RCVL", NULL, "RCV Left Out"}, + {"RCVR", NULL, "RCV Right Out"}, - /* DAC */ - SND_SOC_DAPM_DAC("DACL", "Hifi Playback", MAX98090_0x3F_OUT_ENABLE, 0, 0), - SND_SOC_DAPM_DAC("DACR", "Hifi Playback", MAX98090_0x3F_OUT_ENABLE, 1, 0), }; -static struct snd_soc_dapm_route max98090_audio_map[] = { - /* Output */ - {"HPL", NULL, "HPL Out"}, - {"HPR", NULL, "HPR Out"}, +static const struct snd_soc_dapm_route max98091_dapm_routes[] = { + + /* DMIC inputs */ + {"DMIC3", NULL, "DMIC3_ENA"}, + {"DMIC4", NULL, "DMIC4_ENA"}, + {"DMIC3", NULL, "AHPF"}, + {"DMIC4", NULL, "AHPF"}, + +}; + +static int max98090_add_widgets(struct snd_soc_codec *codec) +{ + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = &codec->dapm; + + snd_soc_add_codec_controls(codec, max98090_snd_controls, + ARRAY_SIZE(max98090_snd_controls)); - /* PGA */ - {"HPL Out", NULL, "HPL Mixer"}, - {"HPR Out", NULL, "HPR Mixer"}, + if (max98090->devtype == MAX98091) { + snd_soc_add_codec_controls(codec, max98091_snd_controls, + ARRAY_SIZE(max98091_snd_controls)); + } + + snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, + ARRAY_SIZE(max98090_dapm_widgets)); + + snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, + ARRAY_SIZE(max98090_dapm_routes)); + + if (max98090->devtype == MAX98091) { + snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, + ARRAY_SIZE(max98091_dapm_widgets)); + + snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, + ARRAY_SIZE(max98091_dapm_routes)); + + } - /* Mixer*/ - {"HPL Mixer", "DACR Switch", "DACR"}, - {"HPL Mixer", "DACL Switch", "DACL"}, + return 0; +} + +static const int pclk_rates[] = { + 12000000, 12000000, 13000000, 13000000, + 16000000, 16000000, 19200000, 19200000 +}; + +static const int lrclk_rates[] = { + 8000, 16000, 8000, 16000, + 8000, 16000, 8000, 16000 +}; - {"HPR Mixer", "DACR Switch", "DACR"}, - {"HPR Mixer", "DACL Switch", "DACL"}, +static const int user_pclk_rates[] = { + 13000000, 13000000 }; -static bool max98090_volatile(struct device *dev, unsigned int reg) +static const int user_lrclk_rates[] = { + 44100, 48000 +}; + +static const unsigned long long ni_value[] = { + 3528, 768 +}; + +static const unsigned long long mi_value[] = { + 8125, 1625 +}; + +static void max98090_configure_bclk(struct snd_soc_codec *codec) { - if ((reg == MAX98090_0x01_INT_STS) || - (reg == MAX98090_0x02_JACK_STS) || - (reg > MAX98090_REG_MAX_CACHED)) - return true; + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + unsigned long long ni; + int i; + + if (!max98090->sysclk) { + dev_err(codec->dev, "No SYSCLK configured\n"); + return; + } + + if (!max98090->bclk || !max98090->lrclk) { + dev_err(codec->dev, "No audio clocks configured\n"); + return; + } + + /* Skip configuration when operating as slave */ + if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) & + M98090_MAS_MASK)) { + return; + } - return false; + /* Check for supported PCLK to LRCLK ratios */ + for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { + if ((pclk_rates[i] == max98090->sysclk) && + (lrclk_rates[i] == max98090->lrclk)) { + dev_dbg(codec->dev, + "Found supported PCLK to LRCLK rates 0x%x\n", + i + 0x8); + + snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, + M98090_FREQ_MASK, + (i + 0x8) << M98090_FREQ_SHIFT); + snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, + M98090_USE_M1_MASK, 0); + return; + } + } + + /* Check for user calculated MI and NI ratios */ + for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { + if ((user_pclk_rates[i] == max98090->sysclk) && + (user_lrclk_rates[i] == max98090->lrclk)) { + dev_dbg(codec->dev, + "Found user supported PCLK to LRCLK rates\n"); + dev_dbg(codec->dev, "i %d ni %lld mi %lld\n", + i, ni_value[i], mi_value[i]); + + snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, + M98090_FREQ_MASK, 0); + snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, + M98090_USE_M1_MASK, + 1 << M98090_USE_M1_SHIFT); + + snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, + (ni_value[i] >> 8) & 0x7F); + snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, + ni_value[i] & 0xFF); + snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB, + (mi_value[i] >> 8) & 0x7F); + snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB, + mi_value[i] & 0xFF); + + return; + } + } + + /* + * Calculate based on MI = 65536 (not as good as either method above) + */ + snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, + M98090_FREQ_MASK, 0); + snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, + M98090_USE_M1_MASK, 0); + + /* + * Configure NI when operating as master + * Note: There is a small, but significant audio quality improvement + * by calculating ni and mi. + */ + ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) + * (unsigned long long int)max98090->lrclk; + do_div(ni, (unsigned long long int)max98090->sysclk); + dev_info(codec->dev, "No better method found\n"); + dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni); + snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, + (ni >> 8) & 0x7F); + snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); } -static int max98090_dai_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) +static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) { - struct snd_soc_codec *codec = dai->codec; - unsigned int val; + struct snd_soc_codec *codec = codec_dai->codec; + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + struct max98090_cdata *cdata; + u8 regval; + + max98090->dai_fmt = fmt; + cdata = &max98090->dai[0]; + + if (fmt != cdata->fmt) { + cdata->fmt = fmt; + + regval = 0; + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* Set to slave mode PLL - MAS mode off */ + snd_soc_write(codec, + M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); + snd_soc_write(codec, + M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); + snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, + M98090_USE_M1_MASK, 0); + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* Set to master mode */ + if (max98090->tdm_slots == 4) { + /* TDM */ + regval |= M98090_MAS_MASK | + M98090_BSEL_64; + } else if (max98090->tdm_slots == 3) { + /* TDM */ + regval |= M98090_MAS_MASK | + M98090_BSEL_48; + } else { + /* Few TDM slots, or No TDM */ + regval |= M98090_MAS_MASK | + M98090_BSEL_32; + } + break; + case SND_SOC_DAIFMT_CBS_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + default: + dev_err(codec->dev, "DAI clock mode unsupported"); + return -EINVAL; + } + snd_soc_write(codec, M98090_REG_MASTER_MODE, regval); + + regval = 0; + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + regval |= M98090_DLY_MASK; + break; + case SND_SOC_DAIFMT_LEFT_J: + break; + case SND_SOC_DAIFMT_RIGHT_J: + regval |= M98090_RJ_MASK; + break; + case SND_SOC_DAIFMT_DSP_A: + /* Not supported mode */ + default: + dev_err(codec->dev, "DAI format unsupported"); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_NB_IF: + regval |= M98090_WCI_MASK; + break; + case SND_SOC_DAIFMT_IB_NF: + regval |= M98090_BCI_MASK; + break; + case SND_SOC_DAIFMT_IB_IF: + regval |= M98090_BCI_MASK|M98090_WCI_MASK; + break; + default: + dev_err(codec->dev, "DAI invert mode unsupported"); + return -EINVAL; + } + + /* + * This accommodates an inverted logic in the MAX98090 chip + * for Bit Clock Invert (BCI). The inverted logic is only + * seen for the case of TDM mode. The remaining cases have + * normal logic. + */ + if (max98090->tdm_slots > 1) { + regval ^= M98090_BCI_MASK; + } + + snd_soc_write(codec, + M98090_REG_INTERFACE_FORMAT, regval); + } - switch (params_rate(params)) { - case 96000: - val = 1 << 5; - break; - case 32000: - val = 1 << 4; - break; - case 48000: - val = 1 << 3; + return 0; +} + +static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, + unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + struct max98090_cdata *cdata; + cdata = &max98090->dai[0]; + + if (slots < 0 || slots > 4) + return -EINVAL; + + max98090->tdm_slots = slots; + max98090->tdm_width = slot_width; + + if (max98090->tdm_slots > 1) { + /* SLOTL SLOTR SLOTDLY */ + snd_soc_write(codec, M98090_REG_TDM_FORMAT, + 0 << M98090_TDM_SLOTL_SHIFT | + 1 << M98090_TDM_SLOTR_SHIFT | + 0 << M98090_TDM_SLOTDLY_SHIFT); + + /* FSW TDM */ + snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL, + M98090_TDM_MASK, + M98090_TDM_MASK); + } + + /* + * Normally advisable to set TDM first, but this permits either order + */ + cdata->fmt = 0; + max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); + + return 0; +} + +static int max98090_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + int ret; + + switch (level) { + case SND_SOC_BIAS_ON: + if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { + ret = regcache_sync(max98090->regmap); + + if (ret != 0) { + dev_err(codec->dev, + "Failed to sync cache: %d\n", ret); + return ret; + } + } + + if (max98090->jack_state == M98090_JACK_STATE_HEADSET) { + /* + * Set to normal bias level. + */ + snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE, + M98090_MBVSEL_MASK, M98090_MBVSEL_2V8); + } break; - case 44100: - val = 1 << 2; + + case SND_SOC_BIAS_PREPARE: break; - case 16000: - val = 1 << 1; + + case SND_SOC_BIAS_STANDBY: + case SND_SOC_BIAS_OFF: + /* Set internal pull-up to lowest power mode */ + snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, + M98090_JDWK_MASK, M98090_JDWK_MASK); + regcache_mark_dirty(max98090->regmap); break; - case 8000: - val = 1 << 0; + } + codec->dapm.bias_level = level; + return 0; +} + +static const int comp_pclk_rates[] = { + 11289600, 12288000, 12000000, 13000000, 19200000 +}; + +static const int dmic_micclk[] = { + 2, 2, 2, 2, 4, 2 +}; + +static const int comp_lrclk_rates[] = { + 8000, 16000, 32000, 44100, 48000, 96000 +}; + +static const int dmic_comp[6][6] = { + {7, 8, 3, 3, 3, 3}, + {7, 8, 3, 3, 3, 3}, + {7, 8, 3, 3, 3, 3}, + {7, 8, 3, 1, 1, 1}, + {7, 8, 3, 1, 2, 2}, + {7, 8, 3, 3, 3, 3} +}; + +static int max98090_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + struct max98090_cdata *cdata; + int i, j; + + cdata = &max98090->dai[0]; + max98090->bclk = snd_soc_params_to_bclk(params); + if (params_channels(params) == 1) + max98090->bclk *= 2; + + max98090->lrclk = params_rate(params); + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT, + M98090_WS_MASK, 0); break; default: - dev_err(codec->dev, "unsupported rate\n"); return -EINVAL; } - snd_soc_update_bits(codec, MAX98090_0x05_SAMPLE_RATE, 0x03F, val); + + max98090_configure_bclk(codec); + + cdata->rate = max98090->lrclk; + + /* Update filter mode */ + if (max98090->lrclk < 24000) + snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, + M98090_MODE_MASK, 0); + else + snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, + M98090_MODE_MASK, M98090_MODE_MASK); + + /* Update sample rate mode */ + if (max98090->lrclk < 50000) + snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, + M98090_DHF_MASK, 0); + else + snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, + M98090_DHF_MASK, M98090_DHF_MASK); + + /* Check for supported PCLK to LRCLK ratios */ + for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) { + if (comp_pclk_rates[j] == max98090->sysclk) { + break; + } + } + + for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { + if (max98090->lrclk <= (comp_lrclk_rates[i] + + comp_lrclk_rates[i + 1]) / 2) { + break; + } + } + + snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE, + M98090_MICCLK_MASK, + dmic_micclk[j] << M98090_MICCLK_SHIFT); + + snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG, + M98090_DMIC_COMP_MASK, + dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT); return 0; } +/* + * PLL / Sysclk + */ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, - int clk_id, unsigned int freq, int dir) + int clk_id, unsigned int freq, int dir) { struct snd_soc_codec *codec = dai->codec; - unsigned int val; - - snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, - MAX98090_SHDNRUN, 0); - - switch (freq) { - case 26000000: - val = 1 << 7; - break; - case 19200000: - val = 1 << 6; - break; - case 13000000: - val = 1 << 5; - break; - case 12288000: - val = 1 << 4; - break; - case 12000000: - val = 1 << 3; - break; - case 11289600: - val = 1 << 2; - break; - default: + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + + /* Requested clock frequency is already setup */ + if (freq == max98090->sysclk) + return 0; + + /* Setup clocks for slave mode, and using the PLL + * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) + * 0x02 (when master clk is 20MHz to 40MHz).. + * 0x03 (when master clk is 40MHz to 60MHz).. + */ + if ((freq >= 10000000) && (freq < 20000000)) { + snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, + M98090_PSCLK_DIV1); + } else if ((freq >= 20000000) && (freq < 40000000)) { + snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, + M98090_PSCLK_DIV2); + } else if ((freq >= 40000000) && (freq < 60000000)) { + snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, + M98090_PSCLK_DIV4); + } else { dev_err(codec->dev, "Invalid master clock frequency\n"); return -EINVAL; } - snd_soc_update_bits(codec, MAX98090_0x04_SYS_CLK, 0xFD, val); - snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, - MAX98090_SHDNRUN, MAX98090_SHDNRUN); + max98090->sysclk = freq; - dev_dbg(dai->dev, "sysclk is %uHz\n", freq); + max98090_configure_bclk(codec); return 0; } -static int max98090_dai_set_fmt(struct snd_soc_dai *dai, - unsigned int fmt) +static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute) { - struct snd_soc_codec *codec = dai->codec; - int is_master; - u8 val; + struct snd_soc_codec *codec = codec_dai->codec; + int regval; - /* master/slave mode */ - switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_CBM_CFM: - is_master = 1; - break; - case SND_SOC_DAIFMT_CBS_CFS: - is_master = 0; - break; - default: - dev_err(codec->dev, "unsupported clock\n"); - return -EINVAL; + regval = mute ? M98090_DVM_MASK : 0; + snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL, + M98090_DVM_MASK, regval); + + return 0; +} + +static void max98090_jack_work(struct work_struct *work) +{ + struct max98090_priv *max98090 = container_of(work, + struct max98090_priv, + jack_work.work); + struct snd_soc_codec *codec = max98090->codec; + struct snd_soc_dapm_context *dapm = &codec->dapm; + int status = 0; + int reg; + + /* Read a second time */ + if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { + + /* Strong pull up allows mic detection */ + snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, + M98090_JDWK_MASK, 0); + + msleep(50); + + reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); + + /* Weak pull up allows only insertion detection */ + snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, + M98090_JDWK_MASK, M98090_JDWK_MASK); + } else { + reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); } - /* format */ - switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_I2S: - val = (is_master) ? MAX98090_I2S_M : MAX98090_I2S_S; - break; - case SND_SOC_DAIFMT_RIGHT_J: - val = (is_master) ? MAX98090_RJ_M : MAX98090_RJ_S; - break; - case SND_SOC_DAIFMT_LEFT_J: - val = (is_master) ? MAX98090_LJ_M : MAX98090_LJ_S; - break; - default: - dev_err(codec->dev, "unsupported format\n"); - return -EINVAL; + reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); + + switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { + case M98090_LSNS_MASK | M98090_JKSNS_MASK: + dev_dbg(codec->dev, "No Headset Detected\n"); + + max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; + + status |= 0; + + break; + + case 0: + if (max98090->jack_state == + M98090_JACK_STATE_HEADSET) { + + dev_dbg(codec->dev, + "Headset Button Down Detected\n"); + + /* + * max98090_headset_button_event(codec) + * could be defined, then called here. + */ + + status |= SND_JACK_HEADSET; + status |= SND_JACK_BTN_0; + + break; + } + + /* Line is reported as Headphone */ + /* Nokia Headset is reported as Headphone */ + /* Mono Headphone is reported as Headphone */ + dev_dbg(codec->dev, "Headphone Detected\n"); + + max98090->jack_state = M98090_JACK_STATE_HEADPHONE; + + status |= SND_JACK_HEADPHONE; + + break; + + case M98090_JKSNS_MASK: + dev_dbg(codec->dev, "Headset Detected\n"); + + max98090->jack_state = M98090_JACK_STATE_HEADSET; + + status |= SND_JACK_HEADSET; + + break; + + default: + dev_dbg(codec->dev, "Unrecognized Jack Status\n"); + break; + } + + snd_soc_jack_report(max98090->jack, status, + SND_JACK_HEADSET | SND_JACK_BTN_0); + + snd_soc_dapm_sync(dapm); +} + +static irqreturn_t max98090_interrupt(int irq, void *data) +{ + struct snd_soc_codec *codec = data; + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + int ret; + unsigned int mask; + unsigned int active; + + dev_dbg(codec->dev, "***** max98090_interrupt *****\n"); + + ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); + + if (ret != 0) { + dev_err(codec->dev, + "failed to read M98090_REG_INTERRUPT_S: %d\n", + ret); + return IRQ_NONE; + } + + ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); + + if (ret != 0) { + dev_err(codec->dev, + "failed to read M98090_REG_DEVICE_STATUS: %d\n", + ret); + return IRQ_NONE; + } + + dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", + active, mask, active & mask); + + active &= mask; + + if (!active) + return IRQ_NONE; + + if (active & M98090_CLD_MASK) { + dev_err(codec->dev, "M98090_CLD_MASK\n"); + } + + if (active & M98090_SLD_MASK) { + dev_dbg(codec->dev, "M98090_SLD_MASK\n"); } - snd_soc_update_bits(codec, MAX98090_0x06_DAI_IF, - MAX98090_DAI_IF_MASK, val); + + if (active & M98090_ULK_MASK) { + dev_err(codec->dev, "M98090_ULK_MASK\n"); + } + + if (active & M98090_JDET_MASK) { + dev_dbg(codec->dev, "M98090_JDET_MASK\n"); + + pm_wakeup_event(codec->dev, 100); + + schedule_delayed_work(&max98090->jack_work, + msecs_to_jiffies(100)); + } + + if (active & M98090_DRCACT_MASK) { + dev_dbg(codec->dev, "M98090_DRCACT_MASK\n"); + } + + if (active & M98090_DRCCLP_MASK) { + dev_err(codec->dev, "M98090_DRCCLP_MASK\n"); + } + + return IRQ_HANDLED; +} + +/** + * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ + * + * @codec: MAX98090 codec + * @jack: jack to report detection events on + * + * Enable microphone detection via IRQ on the MAX98090. If GPIOs are + * being used to bring out signals to the processor then only platform + * data configuration is needed for MAX98090 and processor GPIOs should + * be configured using snd_soc_jack_add_gpios() instead. + * + * If no jack is supplied detection will be disabled. + */ +int max98090_mic_detect(struct snd_soc_codec *codec, + struct snd_soc_jack *jack) +{ + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "max98090_mic_detect\n"); + + max98090->jack = jack; + if (jack) { + snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, + M98090_IJDET_MASK, + 1 << M98090_IJDET_SHIFT); + } else { + snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, + M98090_IJDET_MASK, + 0); + } + + /* Send an initial empty report */ + snd_soc_jack_report(max98090->jack, 0, + SND_JACK_HEADSET | SND_JACK_BTN_0); + + schedule_delayed_work(&max98090->jack_work, + msecs_to_jiffies(100)); return 0; } +EXPORT_SYMBOL_GPL(max98090_mic_detect); #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) static struct snd_soc_dai_ops max98090_dai_ops = { - .set_sysclk = max98090_dai_set_sysclk, - .set_fmt = max98090_dai_set_fmt, - .hw_params = max98090_dai_hw_params, + .set_sysclk = max98090_dai_set_sysclk, + .set_fmt = max98090_dai_set_fmt, + .set_tdm_slot = max98090_set_tdm_slot, + .hw_params = max98090_dai_hw_params, + .digital_mute = max98090_dai_digital_mute, }; -static struct snd_soc_dai_driver max98090_dai = { - .name = "max98090-Hifi", +static struct snd_soc_dai_driver max98090_dai[] = { +{ + .name = "HiFi", .playback = { - .stream_name = "Playback", - .channels_min = 1, - .channels_max = 2, - .rates = MAX98090_RATES, - .formats = MAX98090_FORMATS, + .stream_name = "HiFi Playback", + .channels_min = 2, + .channels_max = 2, + .rates = MAX98090_RATES, + .formats = MAX98090_FORMATS, + }, + .capture = { + .stream_name = "HiFi Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MAX98090_RATES, + .formats = MAX98090_FORMATS, }, - .ops = &max98090_dai_ops, + .ops = &max98090_dai_ops, +} }; +static void max98090_handle_pdata(struct snd_soc_codec *codec) +{ + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + struct max98090_pdata *pdata = max98090->pdata; + + if (!pdata) { + dev_err(codec->dev, "No platform data\n"); + return; + } + +} + static int max98090_probe(struct snd_soc_codec *codec) { - struct max98090_priv *priv = snd_soc_codec_get_drvdata(codec); - struct device *dev = codec->dev; - int ret; + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + struct max98090_cdata *cdata; + int ret = 0; + + dev_dbg(codec->dev, "max98090_probe\n"); + + max98090->codec = codec; + + codec->control_data = max98090->regmap; - codec->control_data = priv->regmap; ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); - if (ret < 0) { - dev_err(dev, "Failed to set cache I/O: %d\n", ret); + if (ret != 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); return ret; } - /* Device active */ - snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, - MAX98090_SHDNRUN, MAX98090_SHDNRUN); + /* Reset the codec, the DSP core, and disable all interrupts */ + max98090_reset(max98090); - return 0; + /* Initialize private data */ + + max98090->sysclk = (unsigned)-1; + + cdata = &max98090->dai[0]; + cdata->rate = (unsigned)-1; + cdata->fmt = (unsigned)-1; + + max98090->lin_state = 0; + max98090->pa1en = 0; + max98090->pa2en = 0; + max98090->extmic_mux = 0; + + ret = snd_soc_read(codec, M98090_REG_REVISION_ID); + if (ret < 0) { + dev_err(codec->dev, "Failed to read device revision: %d\n", + ret); + goto err_access; + } + + if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { + max98090->devtype = MAX98090; + dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret); + } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { + max98090->devtype = MAX98091; + dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret); + } else { + max98090->devtype = MAX98090; + dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret); + } + + max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; + + INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); + + /* Enable jack detection */ + snd_soc_write(codec, M98090_REG_JACK_DETECT, + M98090_JDETEN_MASK | M98090_JDEB_25MS); + + /* Register for interrupts */ + dev_dbg(codec->dev, "irq = %d\n", max98090->irq); + + ret = request_threaded_irq(max98090->irq, NULL, + max98090_interrupt, IRQF_TRIGGER_FALLING, + "max98090_interrupt", codec); + if (ret < 0) { + dev_err(codec->dev, "request_irq failed: %d\n", + ret); + } + + /* + * Clear any old interrupts. + * An old interrupt ocurring prior to installing the ISR + * can keep a new interrupt from generating a trigger. + */ + snd_soc_read(codec, M98090_REG_DEVICE_STATUS); + + /* High Performance is default */ + snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, + M98090_DACHP_MASK, + 1 << M98090_DACHP_SHIFT); + snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, + M98090_PERFMODE_MASK, + 0 << M98090_PERFMODE_SHIFT); + snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL, + M98090_ADCHP_MASK, + 1 << M98090_ADCHP_SHIFT); + + /* Turn on VCM bandgap reference */ + snd_soc_write(codec, M98090_REG_BIAS_CONTROL, + M98090_VCM_MODE_MASK); + + max98090_handle_pdata(codec); + + max98090_add_widgets(codec); + +err_access: + return ret; } static int max98090_remove(struct snd_soc_codec *codec) { + struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); + + cancel_delayed_work_sync(&max98090->jack_work); + return 0; } static struct snd_soc_codec_driver soc_codec_dev_max98090 = { - .probe = max98090_probe, - .remove = max98090_remove, - .controls = max98090_snd_controls, - .num_controls = ARRAY_SIZE(max98090_snd_controls), - .dapm_widgets = max98090_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(max98090_dapm_widgets), - .dapm_routes = max98090_audio_map, - .num_dapm_routes = ARRAY_SIZE(max98090_audio_map), + .probe = max98090_probe, + .remove = max98090_remove, + .set_bias_level = max98090_set_bias_level, }; static const struct regmap_config max98090_regmap = { - .reg_bits = 8, - .val_bits = 8, - .max_register = MAX98090_REG_END, - .volatile_reg = max98090_volatile, - .cache_type = REGCACHE_RBTREE, - .reg_defaults = max98090_reg_defaults, - .num_reg_defaults = ARRAY_SIZE(max98090_reg_defaults), + .reg_bits = 8, + .val_bits = 8, + + .max_register = MAX98090_MAX_REGISTER, + .reg_defaults = max98090_reg, + .num_reg_defaults = ARRAY_SIZE(max98090_reg), + .volatile_reg = max98090_volatile_register, + .readable_reg = max98090_readable_register, + .cache_type = REGCACHE_RBTREE, }; static int max98090_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) + const struct i2c_device_id *id) { - struct max98090_priv *priv; - struct device *dev = &i2c->dev; - unsigned int val; + struct max98090_priv *max98090; int ret; - priv = devm_kzalloc(dev, sizeof(struct max98090_priv), - GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); - if (IS_ERR(priv->regmap)) { - ret = PTR_ERR(priv->regmap); - dev_err(dev, "Failed to init regmap: %d\n", ret); - return ret; - } + pr_debug("max98090_i2c_probe\n"); - i2c_set_clientdata(i2c, priv); + max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), + GFP_KERNEL); + if (max98090 == NULL) + return -ENOMEM; - ret = regmap_read(priv->regmap, MAX98090_0xFF_REV_ID, &val); - if (ret < 0) { - dev_err(dev, "Failed to read device revision: %d\n", ret); - return ret; + max98090->devtype = id->driver_data; + i2c_set_clientdata(i2c, max98090); + max98090->control_data = i2c; + max98090->pdata = i2c->dev.platform_data; + max98090->irq = i2c->irq; + + max98090->regmap = regmap_init_i2c(i2c, &max98090_regmap); + if (IS_ERR(max98090->regmap)) { + ret = PTR_ERR(max98090->regmap); + dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); + goto err_enable; } - dev_info(dev, "revision 0x%02x\n", val); - ret = snd_soc_register_codec(dev, - &soc_codec_dev_max98090, - &max98090_dai, 1); + ret = snd_soc_register_codec(&i2c->dev, + &soc_codec_dev_max98090, max98090_dai, + ARRAY_SIZE(max98090_dai)); + if (ret < 0) + regmap_exit(max98090->regmap); +err_enable: return ret; } static int max98090_i2c_remove(struct i2c_client *client) { + struct max98090_priv *max98090 = dev_get_drvdata(&client->dev); snd_soc_unregister_codec(&client->dev); + regmap_exit(max98090->regmap); + return 0; +} + +static int max98090_runtime_resume(struct device *dev) +{ + struct max98090_priv *max98090 = dev_get_drvdata(dev); + + regcache_cache_only(max98090->regmap, false); + + regcache_sync(max98090->regmap); + return 0; } +static int max98090_runtime_suspend(struct device *dev) +{ + struct max98090_priv *max98090 = dev_get_drvdata(dev); + + regcache_cache_only(max98090->regmap, true); + + return 0; +} + +static struct dev_pm_ops max98090_pm = { + SET_RUNTIME_PM_OPS(max98090_runtime_suspend, + max98090_runtime_resume, NULL) +}; + static const struct i2c_device_id max98090_i2c_id[] = { - { "max98090", 0 }, + { "max98090", MAX98090 }, { } }; MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); @@ -565,13 +2384,15 @@ static struct i2c_driver max98090_i2c_driver = { .driver = { .name = "max98090", .owner = THIS_MODULE, + .pm = &max98090_pm, }, - .probe = max98090_i2c_probe, - .remove = max98090_i2c_remove, - .id_table = max98090_i2c_id, + .probe = max98090_i2c_probe, + .remove = max98090_i2c_remove, + .id_table = max98090_i2c_id, }; + module_i2c_driver(max98090_i2c_driver); MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); -MODULE_AUTHOR("Peter Hsiang, Kuninori Morimoto"); +MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/max98090.h b/sound/soc/codecs/max98090.h new file mode 100755 index 000000000000..7e103f249053 --- /dev/null +++ b/sound/soc/codecs/max98090.h @@ -0,0 +1,1549 @@ +/* + * max98090.h -- MAX98090 ALSA SoC Audio driver + * + * Copyright 2011-2012 Maxim Integrated Products + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MAX98090_H +#define _MAX98090_H + +#include <linux/version.h> + +/* One can override the Linux version here with an explicit version number */ +#define M98090_LINUX_VERSION LINUX_VERSION_CODE + +/* + * MAX98090 Register Definitions + */ + +#define M98090_REG_SOFTWARE_RESET 0x00 +#define M98090_REG_DEVICE_STATUS 0x01 +#define M98090_REG_JACK_STATUS 0x02 +#define M98090_REG_INTERRUPT_S 0x03 +#define M98090_REG_QUICK_SYSTEM_CLOCK 0x04 +#define M98090_REG_QUICK_SAMPLE_RATE 0x05 +#define M98090_REG_DAI_INTERFACE 0x06 +#define M98090_REG_DAC_PATH 0x07 +#define M98090_REG_MIC_DIRECT_TO_ADC 0x08 +#define M98090_REG_LINE_TO_ADC 0x09 +#define M98090_REG_ANALOG_MIC_LOOP 0x0A +#define M98090_REG_ANALOG_LINE_LOOP 0x0B +#define M98090_REG_RESERVED 0x0C +#define M98090_REG_LINE_INPUT_CONFIG 0x0D +#define M98090_REG_LINE_INPUT_LEVEL 0x0E +#define M98090_REG_INPUT_MODE 0x0F +#define M98090_REG_MIC1_INPUT_LEVEL 0x10 +#define M98090_REG_MIC2_INPUT_LEVEL 0x11 +#define M98090_REG_MIC_BIAS_VOLTAGE 0x12 +#define M98090_REG_DIGITAL_MIC_ENABLE 0x13 +#define M98090_REG_DIGITAL_MIC_CONFIG 0x14 +#define M98090_REG_LEFT_ADC_MIXER 0x15 +#define M98090_REG_RIGHT_ADC_MIXER 0x16 +#define M98090_REG_LEFT_ADC_LEVEL 0x17 +#define M98090_REG_RIGHT_ADC_LEVEL 0x18 +#define M98090_REG_ADC_BIQUAD_LEVEL 0x19 +#define M98090_REG_ADC_SIDETONE 0x1A +#define M98090_REG_SYSTEM_CLOCK 0x1B +#define M98090_REG_CLOCK_MODE 0x1C +#define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D +#define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E +#define M98090_REG_CLOCK_RATIO_MI_MSB 0x1F +#define M98090_REG_CLOCK_RATIO_MI_LSB 0x20 +#define M98090_REG_MASTER_MODE 0x21 +#define M98090_REG_INTERFACE_FORMAT 0x22 +#define M98090_REG_TDM_CONTROL 0x23 +#define M98090_REG_TDM_FORMAT 0x24 +#define M98090_REG_IO_CONFIGURATION 0x25 +#define M98090_REG_FILTER_CONFIG 0x26 +#define M98090_REG_DAI_PLAYBACK_LEVEL 0x27 +#define M98090_REG_DAI_PLAYBACK_LEVEL_EQ 0x28 +#define M98090_REG_LEFT_HP_MIXER 0x29 +#define M98090_REG_RIGHT_HP_MIXER 0x2A +#define M98090_REG_HP_CONTROL 0x2B +#define M98090_REG_LEFT_HP_VOLUME 0x2C +#define M98090_REG_RIGHT_HP_VOLUME 0x2D +#define M98090_REG_LEFT_SPK_MIXER 0x2E +#define M98090_REG_RIGHT_SPK_MIXER 0x2F +#define M98090_REG_SPK_CONTROL 0x30 +#define M98090_REG_LEFT_SPK_VOLUME 0x31 +#define M98090_REG_RIGHT_SPK_VOLUME 0x32 +#define M98090_REG_DRC_TIMING 0x33 +#define M98090_REG_DRC_COMPRESSOR 0x34 +#define M98090_REG_DRC_EXPANDER 0x35 +#define M98090_REG_DRC_GAIN 0x36 +#define M98090_REG_RCV_LOUTL_MIXER 0x37 +#define M98090_REG_RCV_LOUTL_CONTROL 0x38 +#define M98090_REG_RCV_LOUTL_VOLUME 0x39 +#define M98090_REG_LOUTR_MIXER 0x3A +#define M98090_REG_LOUTR_CONTROL 0x3B +#define M98090_REG_LOUTR_VOLUME 0x3C +#define M98090_REG_JACK_DETECT 0x3D +#define M98090_REG_INPUT_ENABLE 0x3E +#define M98090_REG_OUTPUT_ENABLE 0x3F +#define M98090_REG_LEVEL_CONTROL 0x40 +#define M98090_REG_DSP_FILTER_ENABLE 0x41 +#define M98090_REG_BIAS_CONTROL 0x42 +#define M98090_REG_DAC_CONTROL 0x43 +#define M98090_REG_ADC_CONTROL 0x44 +#define M98090_REG_DEVICE_SHUTDOWN 0x45 +#define M98090_REG_EQUALIZER_BASE 0x46 +#define M98090_REG_RECORD_BIQUAD_BASE 0xAF +#define M98090_REG_DMIC3_VOLUME 0xBE +#define M98090_REG_DMIC4_VOLUME 0xBF +#define M98090_REG_DMIC34_BQ_PREATTEN 0xC0 +#define M98090_REG_RECORD_TDM_SLOT 0xC1 +#define M98090_REG_SAMPLE_RATE 0xC2 +#define M98090_REG_DMIC34_BIQUAD_BASE 0xC3 +#define M98090_REG_REVISION_ID 0xFF + +#define M98090_REG_CNT (0xFF+1) +#define MAX98090_MAX_REGISTER 0xFF + +/* MAX98090 Register Bit Fields */ + +/* + * M98090_REG_SOFTWARE_RESET + */ +#define M98090_SWRESET_MASK (1<<7) +#define M98090_SWRESET_SHIFT 7 +#define M98090_SWRESET_WIDTH 1 + +/* + * M98090_REG_DEVICE_STATUS + */ +#define M98090_CLD_MASK (1<<7) +#define M98090_CLD_SHIFT 7 +#define M98090_CLD_WIDTH 1 +#define M98090_SLD_MASK (1<<6) +#define M98090_SLD_SHIFT 6 +#define M98090_SLD_WIDTH 1 +#define M98090_ULK_MASK (1<<5) +#define M98090_ULK_SHIFT 5 +#define M98090_ULK_WIDTH 1 +#define M98090_JDET_MASK (1<<2) +#define M98090_JDET_SHIFT 2 +#define M98090_JDET_WIDTH 1 +#define M98090_DRCACT_MASK (1<<1) +#define M98090_DRCACT_SHIFT 1 +#define M98090_DRCACT_WIDTH 1 +#define M98090_DRCCLP_MASK (1<<0) +#define M98090_DRCCLP_SHIFT 0 +#define M98090_DRCCLP_WIDTH 1 + +/* + * M98090_REG_JACK_STATUS + */ +#define M98090_LSNS_MASK (1<<2) +#define M98090_LSNS_SHIFT 2 +#define M98090_LSNS_WIDTH 1 +#define M98090_JKSNS_MASK (1<<1) +#define M98090_JKSNS_SHIFT 1 +#define M98090_JKSNS_WIDTH 1 + +/* + * M98090_REG_INTERRUPT_S + */ +#define M98090_ICLD_MASK (1<<7) +#define M98090_ICLD_SHIFT 7 +#define M98090_ICLD_WIDTH 1 +#define M98090_ISLD_MASK (1<<6) +#define M98090_ISLD_SHIFT 6 +#define M98090_ISLD_WIDTH 1 +#define M98090_IULK_MASK (1<<5) +#define M98090_IULK_SHIFT 5 +#define M98090_IULK_WIDTH 1 +#define M98090_IJDET_MASK (1<<2) +#define M98090_IJDET_SHIFT 2 +#define M98090_IJDET_WIDTH 1 +#define M98090_IDRCACT_MASK (1<<1) +#define M98090_IDRCACT_SHIFT 1 +#define M98090_IDRCACT_WIDTH 1 +#define M98090_IDRCCLP_MASK (1<<0) +#define M98090_IDRCCLP_SHIFT 0 +#define M98090_IDRCCLP_WIDTH 1 + +/* + * M98090_REG_QUICK_SYSTEM_CLOCK + */ +#define M98090_26M_MASK (1<<7) +#define M98090_26M_SHIFT 7 +#define M98090_26M_WIDTH 1 +#define M98090_19P2M_MASK (1<<6) +#define M98090_19P2M_SHIFT 6 +#define M98090_19P2M_WIDTH 1 +#define M98090_13M_MASK (1<<5) +#define M98090_13M_SHIFT 5 +#define M98090_13M_WIDTH 1 +#define M98090_12P288M_MASK (1<<4) +#define M98090_12P288M_SHIFT 4 +#define M98090_12P288M_WIDTH 1 +#define M98090_12M_MASK (1<<3) +#define M98090_12M_SHIFT 3 +#define M98090_12M_WIDTH 1 +#define M98090_11P2896M_MASK (1<<2) +#define M98090_11P2896M_SHIFT 2 +#define M98090_11P2896M_WIDTH 1 +#define M98090_256FS_MASK (1<<0) +#define M98090_256FS_SHIFT 0 +#define M98090_256FS_WIDTH 1 +#define M98090_CLK_ALL_SHIFT 0 +#define M98090_CLK_ALL_WIDTH 8 +#define M98090_CLK_ALL_NUM (1<<M98090_CLK_ALL_WIDTH) + +/* + * M98090_REG_QUICK_SAMPLE_RATE + */ +#define M98090_SR_96K_MASK (1<<5) +#define M98090_SR_96K_SHIFT 5 +#define M98090_SR_96K_WIDTH 1 +#define M98090_SR_32K_MASK (1<<4) +#define M98090_SR_32K_SHIFT 4 +#define M98090_SR_32K_WIDTH 1 +#define M98090_SR_48K_MASK (1<<3) +#define M98090_SR_48K_SHIFT 3 +#define M98090_SR_48K_WIDTH 1 +#define M98090_SR_44K1_MASK (1<<2) +#define M98090_SR_44K1_SHIFT 2 +#define M98090_SR_44K1_WIDTH 1 +#define M98090_SR_16K_MASK (1<<1) +#define M98090_SR_16K_SHIFT 1 +#define M98090_SR_16K_WIDTH 1 +#define M98090_SR_8K_MASK (1<<0) +#define M98090_SR_8K_SHIFT 0 +#define M98090_SR_8K_WIDTH 1 +#define M98090_SR_MASK 0x3F +#define M98090_SR_ALL_SHIFT 0 +#define M98090_SR_ALL_WIDTH 8 +#define M98090_SR_ALL_NUM (1<<M98090_SR_ALL_WIDTH) + +/* + * M98090_REG_DAI_INTERFACE + */ +#define M98090_RJ_M_MASK (1<<5) +#define M98090_RJ_M_SHIFT 5 +#define M98090_RJ_M_WIDTH 1 +#define M98090_RJ_S_MASK (1<<4) +#define M98090_RJ_S_SHIFT 4 +#define M98090_RJ_S_WIDTH 1 +#define M98090_LJ_M_MASK (1<<3) +#define M98090_LJ_M_SHIFT 3 +#define M98090_LJ_M_WIDTH 1 +#define M98090_LJ_S_MASK (1<<2) +#define M98090_LJ_S_SHIFT 2 +#define M98090_LJ_S_WIDTH 1 +#define M98090_I2S_M_MASK (1<<1) +#define M98090_I2S_M_SHIFT 1 +#define M98090_I2S_M_WIDTH 1 +#define M98090_I2S_S_MASK (1<<0) +#define M98090_I2S_S_SHIFT 0 +#define M98090_I2S_S_WIDTH 1 +#define M98090_DAI_ALL_SHIFT 0 +#define M98090_DAI_ALL_WIDTH 8 +#define M98090_DAI_ALL_NUM (1<<M98090_DAI_ALL_WIDTH) + +/* + * M98090_REG_DAC_PATH + */ +#define M98090_DIG2_HP_MASK (1<<7) +#define M98090_DIG2_HP_SHIFT 7 +#define M98090_DIG2_HP_WIDTH 1 +#define M98090_DIG2_EAR_MASK (1<<6) +#define M98090_DIG2_EAR_SHIFT 6 +#define M98090_DIG2_EAR_WIDTH 1 +#define M98090_DIG2_SPK_MASK (1<<5) +#define M98090_DIG2_SPK_SHIFT 5 +#define M98090_DIG2_SPK_WIDTH 1 +#define M98090_DIG2_LOUT_MASK (1<<4) +#define M98090_DIG2_LOUT_SHIFT 4 +#define M98090_DIG2_LOUT_WIDTH 1 +#define M98090_DIG2_ALL_SHIFT 0 +#define M98090_DIG2_ALL_WIDTH 8 +#define M98090_DIG2_ALL_NUM (1<<M98090_DIG2_ALL_WIDTH) + +/* + * M98090_REG_MIC_DIRECT_TO_ADC + */ +#define M98090_IN12_MIC1_MASK (1<<7) +#define M98090_IN12_MIC1_SHIFT 7 +#define M98090_IN12_MIC1_WIDTH 1 +#define M98090_IN34_MIC2_MASK (1<<6) +#define M98090_IN34_MIC2_SHIFT 6 +#define M98090_IN34_MIC2_WIDTH 1 +#define M98090_IN56_MIC1_MASK (1<<5) +#define M98090_IN56_MIC1_SHIFT 5 +#define M98090_IN56_MIC1_WIDTH 1 +#define M98090_IN56_MIC2_MASK (1<<4) +#define M98090_IN56_MIC2_SHIFT 4 +#define M98090_IN56_MIC2_WIDTH 1 +#define M98090_IN12_DADC_MASK (1<<3) +#define M98090_IN12_DADC_SHIFT 3 +#define M98090_IN12_DADC_WIDTH 1 +#define M98090_IN34_DADC_MASK (1<<2) +#define M98090_IN34_DADC_SHIFT 2 +#define M98090_IN34_DADC_WIDTH 1 +#define M98090_IN56_DADC_MASK (1<<1) +#define M98090_IN56_DADC_SHIFT 1 +#define M98090_IN56_DADC_WIDTH 1 +#define M98090_MIC_ALL_SHIFT 0 +#define M98090_MIC_ALL_WIDTH 8 +#define M98090_MIC_ALL_NUM (1<<M98090_MIC_ALL_WIDTH) + +/* + * M98090_REG_LINE_TO_ADC + */ +#define M98090_IN12S_AB_MASK (1<<7) +#define M98090_IN12S_AB_SHIFT 7 +#define M98090_IN12S_AB_WIDTH 1 +#define M98090_IN34S_AB_MASK (1<<6) +#define M98090_IN34S_AB_SHIFT 6 +#define M98090_IN34S_AB_WIDTH 1 +#define M98090_IN56S_AB_MASK (1<<5) +#define M98090_IN56S_AB_SHIFT 5 +#define M98090_IN56S_AB_WIDTH 1 +#define M98090_IN34D_A_MASK (1<<4) +#define M98090_IN34D_A_SHIFT 4 +#define M98090_IN34D_A_WIDTH 1 +#define M98090_IN56D_B_MASK (1<<3) +#define M98090_IN56D_B_SHIFT 3 +#define M98090_IN56D_B_WIDTH 1 +#define M98090_LINE_ALL_SHIFT 0 +#define M98090_LINE_ALL_WIDTH 8 +#define M98090_LINE_ALL_NUM (1<<M98090_LINE_ALL_WIDTH) + +/* + * M98090_REG_ANALOG_MIC_LOOP + */ +#define M98090_IN12_M1HPL_MASK (1<<7) +#define M98090_IN12_M1HPL_SHIFT 7 +#define M98090_IN12_M1HPL_WIDTH 1 +#define M98090_IN12_M1SPKL_MASK (1<<6) +#define M98090_IN12_M1SPKL_SHIFT 6 +#define M98090_IN12_M1SPKL_WIDTH 1 +#define M98090_IN12_M1EAR_MASK (1<<5) +#define M98090_IN12_M1EAR_SHIFT 5 +#define M98090_IN12_M1EAR_WIDTH 1 +#define M98090_IN12_M1LOUTL_MASK (1<<4) +#define M98090_IN12_M1LOUTL_SHIFT 4 +#define M98090_IN12_M1LOUTL_WIDTH 1 +#define M98090_IN34_M2HPR_MASK (1<<3) +#define M98090_IN34_M2HPR_SHIFT 3 +#define M98090_IN34_M2HPR_WIDTH 1 +#define M98090_IN34_M2SPKR_MASK (1<<2) +#define M98090_IN34_M2SPKR_SHIFT 2 +#define M98090_IN34_M2SPKR_WIDTH 1 +#define M98090_IN34_M2EAR_MASK (1<<1) +#define M98090_IN34_M2EAR_SHIFT 1 +#define M98090_IN34_M2EAR_WIDTH 1 +#define M98090_IN34_M2LOUTR_MASK (1<<0) +#define M98090_IN34_M2LOUTR_SHIFT 0 +#define M98090_IN34_M2LOUTR_WIDTH 1 +#define M98090_AMIC_ALL_SHIFT 0 +#define M98090_AMIC_ALL_WIDTH 8 +#define M98090_AMIC_ALL_NUM (1<<M98090_AMIC_ALL_WIDTH) + +/* + * M98090_REG_ANALOG_LINE_LOOP + */ +#define M98090_IN12S_ABHP_MASK (1<<7) +#define M98090_IN12S_ABHP_SHIFT 7 +#define M98090_IN12S_ABHP_WIDTH 1 +#define M98090_IN34D_ASPKL_MASK (1<<6) +#define M98090_IN34D_ASPKL_SHIFT 6 +#define M98090_IN34D_ASPKL_WIDTH 1 +#define M98090_IN34D_AEAR_MASK (1<<5) +#define M98090_IN34D_AEAR_SHIFT 5 +#define M98090_IN34D_AEAR_WIDTH 1 +#define M98090_IN12S_ABLOUT_MASK (1<<4) +#define M98090_IN12S_ABLOUT_SHIFT 4 +#define M98090_IN12S_ABLOUT_WIDTH 1 +#define M98090_IN34S_ABHP_MASK (1<<3) +#define M98090_IN34S_ABHP_SHIFT 3 +#define M98090_IN34S_ABHP_WIDTH 1 +#define M98090_IN56D_BSPKR_MASK (1<<2) +#define M98090_IN56D_BSPKR_SHIFT 2 +#define M98090_IN56D_BSPKR_WIDTH 1 +#define M98090_IN56D_BEAR_MASK (1<<1) +#define M98090_IN56D_BEAR_SHIFT 1 +#define M98090_IN56D_BEAR_WIDTH 1 +#define M98090_IN34S_ABLOUT_MASK (1<<0) +#define M98090_IN34S_ABLOUT_SHIFT 0 +#define M98090_IN34S_ABLOUT_WIDTH 1 +#define M98090_ALIN_ALL_SHIFT 0 +#define M98090_ALIN_ALL_WIDTH 8 +#define M98090_ALIN_ALL_NUM (1<<M98090_ALIN_ALL_WIDTH) + +/* + * M98090_REG_RESERVED + */ + +/* + * M98090_REG_LINE_INPUT_CONFIG + */ +#define M98090_IN34DIFF_MASK (1<<7) +#define M98090_IN34DIFF_SHIFT 7 +#define M98090_IN34DIFF_WIDTH 1 +#define M98090_IN56DIFF_MASK (1<<6) +#define M98090_IN56DIFF_SHIFT 6 +#define M98090_IN56DIFF_WIDTH 1 +#define M98090_IN1SEEN_MASK (1<<5) +#define M98090_IN1SEEN_SHIFT 5 +#define M98090_IN1SEEN_WIDTH 1 +#define M98090_IN2SEEN_MASK (1<<4) +#define M98090_IN2SEEN_SHIFT 4 +#define M98090_IN2SEEN_WIDTH 1 +#define M98090_IN3SEEN_MASK (1<<3) +#define M98090_IN3SEEN_SHIFT 3 +#define M98090_IN3SEEN_WIDTH 1 +#define M98090_IN4SEEN_MASK (1<<2) +#define M98090_IN4SEEN_SHIFT 2 +#define M98090_IN4SEEN_WIDTH 1 +#define M98090_IN5SEEN_MASK (1<<1) +#define M98090_IN5SEEN_SHIFT 1 +#define M98090_IN5SEEN_WIDTH 1 +#define M98090_IN6SEEN_MASK (1<<0) +#define M98090_IN6SEEN_SHIFT 0 +#define M98090_IN6SEEN_WIDTH 1 + +/* + * M98090_REG_LINE_INPUT_LEVEL + */ +#define M98090_MIXG135_MASK (1<<7) +#define M98090_MIXG135_SHIFT 7 +#define M98090_MIXG135_WIDTH 1 +#define M98090_MIXG135_NUM (1<<M98090_MIXG135_WIDTH) +#define M98090_MIXG246_MASK (1<<6) +#define M98090_MIXG246_SHIFT 6 +#define M98090_MIXG246_WIDTH 1 +#define M98090_MIXG246_NUM (1<<M98090_MIXG246_WIDTH) +#define M98090_LINAPGA_MASK (7<<3) +#define M98090_LINAPGA_SHIFT 3 +#define M98090_LINAPGA_WIDTH 3 +#define M98090_LINAPGA_NUM 6 +#define M98090_LINBPGA_MASK (7<<0) +#define M98090_LINBPGA_SHIFT 0 +#define M98090_LINBPGA_WIDTH 3 +#define M98090_LINBPGA_NUM 6 + +/* + * M98090_REG_INPUT_MODE + */ +#define M98090_EXTBUFA_MASK (1<<7) +#define M98090_EXTBUFA_SHIFT 7 +#define M98090_EXTBUFA_WIDTH 1 +#define M98090_EXTBUFA_NUM (1<<M98090_EXTBUFA_WIDTH) +#define M98090_EXTBUFB_MASK (1<<6) +#define M98090_EXTBUFB_SHIFT 6 +#define M98090_EXTBUFB_WIDTH 1 +#define M98090_EXTBUFB_NUM (1<<M98090_EXTBUFB_WIDTH) +#define M98090_EXTMIC_MASK (3<<0) +#define M98090_EXTMIC_SHIFT 0 +#define M98090_EXTMIC1_SHIFT 0 +#define M98090_EXTMIC2_SHIFT 1 +#define M98090_EXTMIC_WIDTH 2 +#define M98090_EXTMIC_NONE (0<<0) +#define M98090_EXTMIC_MIC1 (1<<0) +#define M98090_EXTMIC_MIC2 (2<<0) + +/* + * M98090_REG_MIC1_INPUT_LEVEL + */ +#define M98090_MIC_PA1EN_MASK (3<<5) +#define M98090_MIC_PA1EN_SHIFT 5 +#define M98090_MIC_PA1EN_WIDTH 2 +#define M98090_MIC_PA1EN_NUM 3 +#define M98090_MIC_PGAM1_MASK (31<<0) +#define M98090_MIC_PGAM1_SHIFT 0 +#define M98090_MIC_PGAM1_WIDTH 5 +#define M98090_MIC_PGAM1_NUM 21 + +/* + * M98090_REG_MIC2_INPUT_LEVEL + */ +#define M98090_MIC_PA2EN_MASK (3<<5) +#define M98090_MIC_PA2EN_SHIFT 5 +#define M98090_MIC_PA2EN_WIDTH 2 +#define M98090_MIC_PA2EN_NUM 3 +#define M98090_MIC_PGAM2_MASK (31<<0) +#define M98090_MIC_PGAM2_SHIFT 0 +#define M98090_MIC_PGAM2_WIDTH 5 +#define M98090_MIC_PGAM2_NUM 21 + +/* + * M98090_REG_MIC_BIAS_VOLTAGE + */ +#define M98090_MBVSEL_MASK (3<<0) +#define M98090_MBVSEL_SHIFT 0 +#define M98090_MBVSEL_WIDTH 2 +#define M98090_MBVSEL_2V8 (3<<0) +#define M98090_MBVSEL_2V55 (2<<0) +#define M98090_MBVSEL_2V4 (1<<0) +#define M98090_MBVSEL_2V2 (0<<0) + +/* + * M98090_REG_DIGITAL_MIC_ENABLE + */ +#define M98090_MICCLK_MASK (7<<4) +#define M98090_MICCLK_SHIFT 4 +#define M98090_MICCLK_WIDTH 3 +#define M98090_DIGMIC4_MASK (1<<3) +#define M98090_DIGMIC4_SHIFT 3 +#define M98090_DIGMIC4_WIDTH 1 +#define M98090_DIGMIC4_NUM (1<<M98090_DIGMIC4_WIDTH) +#define M98090_DIGMIC3_MASK (1<<2) +#define M98090_DIGMIC3_SHIFT 2 +#define M98090_DIGMIC3_WIDTH 1 +#define M98090_DIGMIC3_NUM (1<<M98090_DIGMIC3_WIDTH) +#define M98090_DIGMICR_MASK (1<<1) +#define M98090_DIGMICR_SHIFT 1 +#define M98090_DIGMICR_WIDTH 1 +#define M98090_DIGMICR_NUM (1<<M98090_DIGMICR_WIDTH) +#define M98090_DIGMICL_MASK (1<<0) +#define M98090_DIGMICL_SHIFT 0 +#define M98090_DIGMICL_WIDTH 1 +#define M98090_DIGMICL_NUM (1<<M98090_DIGMICL_WIDTH) + +/* + * M98090_REG_DIGITAL_MIC_CONFIG + */ +#define M98090_DMIC_COMP_MASK (15<<4) +#define M98090_DMIC_COMP_SHIFT 4 +#define M98090_DMIC_COMP_WIDTH 4 +#define M98090_DMIC_COMP_NUM (1<<M98090_DMIC_COMP_WIDTH) +#define M98090_DMIC_FREQ_MASK (3<<0) +#define M98090_DMIC_FREQ_SHIFT 0 +#define M98090_DMIC_FREQ_WIDTH 2 + +/* + * M98090_REG_LEFT_ADC_MIXER + */ +#define M98090_MIXADL_MIC2_MASK (1<<6) +#define M98090_MIXADL_MIC2_SHIFT 6 +#define M98090_MIXADL_MIC2_WIDTH 1 +#define M98090_MIXADL_MIC1_MASK (1<<5) +#define M98090_MIXADL_MIC1_SHIFT 5 +#define M98090_MIXADL_MIC1_WIDTH 1 +#define M98090_MIXADL_LINEB_MASK (1<<4) +#define M98090_MIXADL_LINEB_SHIFT 4 +#define M98090_MIXADL_LINEB_WIDTH 1 +#define M98090_MIXADL_LINEA_MASK (1<<3) +#define M98090_MIXADL_LINEA_SHIFT 3 +#define M98090_MIXADL_LINEA_WIDTH 1 +#define M98090_MIXADL_IN65DIFF_MASK (1<<2) +#define M98090_MIXADL_IN65DIFF_SHIFT 2 +#define M98090_MIXADL_IN65DIFF_WIDTH 1 +#define M98090_MIXADL_IN34DIFF_MASK (1<<1) +#define M98090_MIXADL_IN34DIFF_SHIFT 1 +#define M98090_MIXADL_IN34DIFF_WIDTH 1 +#define M98090_MIXADL_IN12DIFF_MASK (1<<0) +#define M98090_MIXADL_IN12DIFF_SHIFT 0 +#define M98090_MIXADL_IN12DIFF_WIDTH 1 +#define M98090_MIXADL_MASK (255<<0) +#define M98090_MIXADL_SHIFT 0 +#define M98090_MIXADL_WIDTH 8 + +/* + * M98090_REG_RIGHT_ADC_MIXER + */ +#define M98090_MIXADR_MIC2_MASK (1<<6) +#define M98090_MIXADR_MIC2_SHIFT 6 +#define M98090_MIXADR_MIC2_WIDTH 1 +#define M98090_MIXADR_MIC1_MASK (1<<5) +#define M98090_MIXADR_MIC1_SHIFT 5 +#define M98090_MIXADR_MIC1_WIDTH 1 +#define M98090_MIXADR_LINEB_MASK (1<<4) +#define M98090_MIXADR_LINEB_SHIFT 4 +#define M98090_MIXADR_LINEB_WIDTH 1 +#define M98090_MIXADR_LINEA_MASK (1<<3) +#define M98090_MIXADR_LINEA_SHIFT 3 +#define M98090_MIXADR_LINEA_WIDTH 1 +#define M98090_MIXADR_IN65DIFF_MASK (1<<2) +#define M98090_MIXADR_IN65DIFF_SHIFT 2 +#define M98090_MIXADR_IN65DIFF_WIDTH 1 +#define M98090_MIXADR_IN34DIFF_MASK (1<<1) +#define M98090_MIXADR_IN34DIFF_SHIFT 1 +#define M98090_MIXADR_IN34DIFF_WIDTH 1 +#define M98090_MIXADR_IN12DIFF_MASK (1<<0) +#define M98090_MIXADR_IN12DIFF_SHIFT 0 +#define M98090_MIXADR_IN12DIFF_WIDTH 1 +#define M98090_MIXADR_MASK (255<<0) +#define M98090_MIXADR_SHIFT 0 +#define M98090_MIXADR_WIDTH 8 + +/* + * M98090_REG_LEFT_ADC_LEVEL + */ +#define M98090_AVLG_MASK (7<<4) +#define M98090_AVLG_SHIFT 4 +#define M98090_AVLG_WIDTH 3 +#define M98090_AVLG_NUM (1<<M98090_AVLG_WIDTH) +#define M98090_AVL_MASK (15<<0) +#define M98090_AVL_SHIFT 0 +#define M98090_AVL_WIDTH 4 +#define M98090_AVL_NUM (1<<M98090_AVL_WIDTH) + +/* + * M98090_REG_RIGHT_ADC_LEVEL + */ +#define M98090_AVRG_MASK (7<<4) +#define M98090_AVRG_SHIFT 4 +#define M98090_AVRG_WIDTH 3 +#define M98090_AVRG_NUM (1<<M98090_AVRG_WIDTH) +#define M98090_AVR_MASK (15<<0) +#define M98090_AVR_SHIFT 0 +#define M98090_AVR_WIDTH 4 +#define M98090_AVR_NUM (1<<M98090_AVR_WIDTH) + +/* + * M98090_REG_ADC_BIQUAD_LEVEL + */ +#define M98090_AVBQ_MASK (15<<0) +#define M98090_AVBQ_SHIFT 0 +#define M98090_AVBQ_WIDTH 4 +#define M98090_AVBQ_NUM (1<<M98090_AVBQ_WIDTH) + +/* + * M98090_REG_ADC_SIDETONE + */ +#define M98090_DSTSR_MASK (1<<7) +#define M98090_DSTSR_SHIFT 7 +#define M98090_DSTSR_WIDTH 1 +#define M98090_DSTSL_MASK (1<<6) +#define M98090_DSTSL_SHIFT 6 +#define M98090_DSTSL_WIDTH 1 +#define M98090_DVST_MASK (31<<0) +#define M98090_DVST_SHIFT 0 +#define M98090_DVST_WIDTH 5 +#define M98090_DVST_NUM 31 + +/* + * M98090_REG_SYSTEM_CLOCK + */ +#define M98090_PSCLK_MASK (3<<4) +#define M98090_PSCLK_SHIFT 4 +#define M98090_PSCLK_WIDTH 2 +#define M98090_PSCLK_DISABLED (0<<4) +#define M98090_PSCLK_DIV1 (1<<4) +#define M98090_PSCLK_DIV2 (2<<4) +#define M98090_PSCLK_DIV4 (3<<4) + +/* + * M98090_REG_CLOCK_MODE + */ +#define M98090_FREQ_MASK (15<<4) +#define M98090_FREQ_SHIFT 4 +#define M98090_FREQ_WIDTH 4 +#define M98090_USE_M1_MASK (1<<0) +#define M98090_USE_M1_SHIFT 0 +#define M98090_USE_M1_WIDTH 1 +#define M98090_USE_M1_NUM (1<<M98090_USE_M1_WIDTH) + +/* + * M98090_REG_CLOCK_RATIO_NI_MSB + */ +#define M98090_NI_HI_MASK (127<<0) +#define M98090_NI_HI_SHIFT 0 +#define M98090_NI_HI_WIDTH 7 +#define M98090_NI_HI_NUM (1<<M98090_NI_HI_WIDTH) + +/* + * M98090_REG_CLOCK_RATIO_NI_LSB + */ +#define M98090_NI_LO_MASK (255<<0) +#define M98090_NI_LO_SHIFT 0 +#define M98090_NI_LO_WIDTH 8 +#define M98090_NI_LO_NUM (1<<M98090_NI_LO_WIDTH) + +/* + * M98090_REG_CLOCK_RATIO_MI_MSB + */ +#define M98090_MI_HI_MASK (255<<0) +#define M98090_MI_HI_SHIFT 0 +#define M98090_MI_HI_WIDTH 8 +#define M98090_MI_HI_NUM (1<<M98090_MI_HI_WIDTH) + +/* + * M98090_REG_CLOCK_RATIO_MI_LSB + */ +#define M98090_MI_LO_MASK (255<<0) +#define M98090_MI_LO_SHIFT 0 +#define M98090_MI_LO_WIDTH 8 +#define M98090_MI_LO_NUM (1<<M98090_MI_LO_WIDTH) + +/* + * M98090_REG_MASTER_MODE + */ +#define M98090_MAS_MASK (1<<7) +#define M98090_MAS_SHIFT 7 +#define M98090_MAS_WIDTH 1 +#define M98090_BSEL_MASK (1<<0) +#define M98090_BSEL_SHIFT 0 +#define M98090_BSEL_WIDTH 1 +#define M98090_BSEL_32 (1<<0) +#define M98090_BSEL_48 (2<<0) +#define M98090_BSEL_64 (3<<0) + +/* + * M98090_REG_INTERFACE_FORMAT + */ +#define M98090_RJ_MASK (1<<5) +#define M98090_RJ_SHIFT 5 +#define M98090_RJ_WIDTH 1 +#define M98090_WCI_MASK (1<<4) +#define M98090_WCI_SHIFT 4 +#define M98090_WCI_WIDTH 1 +#define M98090_BCI_MASK (1<<3) +#define M98090_BCI_SHIFT 3 +#define M98090_BCI_WIDTH 1 +#define M98090_DLY_MASK (1<<2) +#define M98090_DLY_SHIFT 2 +#define M98090_DLY_WIDTH 1 +#define M98090_WS_MASK (3<<0) +#define M98090_WS_SHIFT 0 +#define M98090_WS_WIDTH 2 +#define M98090_WS_NUM (1<<M98090_WS_WIDTH) + +/* + * M98090_REG_TDM_CONTROL + */ +#define M98090_FSW_MASK (1<<1) +#define M98090_FSW_SHIFT 1 +#define M98090_FSW_WIDTH 1 +#define M98090_TDM_MASK (1<<0) +#define M98090_TDM_SHIFT 0 +#define M98090_TDM_WIDTH 1 +#define M98090_TDM_NUM (1<<M98090_TDM_WIDTH) + +/* + * M98090_REG_TDM_FORMAT + */ +#define M98090_TDM_SLOTL_MASK (3<<6) +#define M98090_TDM_SLOTL_SHIFT 6 +#define M98090_TDM_SLOTL_WIDTH 2 +#define M98090_TDM_SLOTL_NUM (1<<M98090_TDM_SLOTL_WIDTH) +#define M98090_TDM_SLOTR_MASK (3<<4) +#define M98090_TDM_SLOTR_SHIFT 4 +#define M98090_TDM_SLOTR_WIDTH 2 +#define M98090_TDM_SLOTR_NUM (1<<M98090_TDM_SLOTR_WIDTH) +#define M98090_TDM_SLOTDLY_MASK (15<<0) +#define M98090_TDM_SLOTDLY_SHIFT 0 +#define M98090_TDM_SLOTDLY_WIDTH 4 +#define M98090_TDM_SLOTDLY_NUM (1<<M98090_TDM_SLOTDLY_WIDTH) + +/* + * M98090_REG_IO_CONFIGURATION + */ +#define M98090_LTEN_MASK (1<<5) +#define M98090_LTEN_SHIFT 5 +#define M98090_LTEN_WIDTH 1 +#define M98090_LTEN_NUM (1<<M98090_LTEN_WIDTH) +#define M98090_LBEN_MASK (1<<4) +#define M98090_LBEN_SHIFT 4 +#define M98090_LBEN_WIDTH 1 +#define M98090_LBEN_NUM (1<<M98090_LBEN_WIDTH) +#define M98090_DMONO_MASK (1<<3) +#define M98090_DMONO_SHIFT 3 +#define M98090_DMONO_WIDTH 1 +#define M98090_DMONO_NUM (1<<M98090_DMONO_WIDTH) +#define M98090_HIZOFF_MASK (1<<2) +#define M98090_HIZOFF_SHIFT 2 +#define M98090_HIZOFF_WIDTH 1 +#define M98090_HIZOFF_NUM (1<<M98090_HIZOFF_WIDTH) +#define M98090_SDOEN_MASK (1<<1) +#define M98090_SDOEN_SHIFT 1 +#define M98090_SDOEN_WIDTH 1 +#define M98090_SDOEN_NUM (1<<M98090_SDOEN_WIDTH) +#define M98090_SDIEN_MASK (1<<0) +#define M98090_SDIEN_SHIFT 0 +#define M98090_SDIEN_WIDTH 1 +#define M98090_SDIEN_NUM (1<<M98090_SDIEN_WIDTH) + +/* + * M98090_REG_FILTER_CONFIG + */ +#define M98090_MODE_MASK (1<<7) +#define M98090_MODE_SHIFT 7 +#define M98090_MODE_WIDTH 1 +#define M98090_AHPF_MASK (1<<6) +#define M98090_AHPF_SHIFT 6 +#define M98090_AHPF_WIDTH 1 +#define M98090_AHPF_NUM (1<<M98090_AHPF_WIDTH) +#define M98090_DHPF_MASK (1<<5) +#define M98090_DHPF_SHIFT 5 +#define M98090_DHPF_WIDTH 1 +#define M98090_DHPF_NUM (1<<M98090_DHPF_WIDTH) +#define M98090_DHF_MASK (1<<4) +#define M98090_DHF_SHIFT 4 +#define M98090_DHF_WIDTH 1 +#define M98090_FLT_DMIC34MODE_MASK (1<<3) +#define M98090_FLT_DMIC34MODE_SHIFT 3 +#define M98090_FLT_DMIC34MODE_WIDTH 1 +#define M98090_FLT_DMIC34HPF_MASK (1<<2) +#define M98090_FLT_DMIC34HPF_SHIFT 2 +#define M98090_FLT_DMIC34HPF_WIDTH 1 +#define M98090_FLT_DMIC34HPF_NUM (1<<M98090_FLT_DMIC34HPF_WIDTH) + +/* + * M98090_REG_DAI_PLAYBACK_LEVEL + */ +#define M98090_DVM_MASK (1<<7) +#define M98090_DVM_SHIFT 7 +#define M98090_DVM_WIDTH 1 +#define M98090_DVG_MASK (3<<4) +#define M98090_DVG_SHIFT 4 +#define M98090_DVG_WIDTH 2 +#define M98090_DVG_NUM (1<<M98090_DVG_WIDTH) +#define M98090_DV_MASK (15<<0) +#define M98090_DV_SHIFT 0 +#define M98090_DV_WIDTH 4 +#define M98090_DV_NUM (1<<M98090_DV_WIDTH) + +/* + * M98090_REG_DAI_PLAYBACK_LEVEL_EQ + */ +#define M98090_EQCLPN_MASK (1<<4) +#define M98090_EQCLPN_SHIFT 4 +#define M98090_EQCLPN_WIDTH 1 +#define M98090_EQCLPN_NUM (1<<M98090_EQCLPN_WIDTH) +#define M98090_DVEQ_MASK (15<<0) +#define M98090_DVEQ_SHIFT 0 +#define M98090_DVEQ_WIDTH 4 +#define M98090_DVEQ_NUM (1<<M98090_DVEQ_WIDTH) + +/* + * M98090_REG_LEFT_HP_MIXER + */ +#define M98090_MIXHPL_MIC2_MASK (1<<5) +#define M98090_MIXHPL_MIC2_SHIFT 5 +#define M98090_MIXHPL_MIC2_WIDTH 1 +#define M98090_MIXHPL_MIC1_MASK (1<<4) +#define M98090_MIXHPL_MIC1_SHIFT 4 +#define M98090_MIXHPL_MIC1_WIDTH 1 +#define M98090_MIXHPL_LINEB_MASK (1<<3) +#define M98090_MIXHPL_LINEB_SHIFT 3 +#define M98090_MIXHPL_LINEB_WIDTH 1 +#define M98090_MIXHPL_LINEA_MASK (1<<2) +#define M98090_MIXHPL_LINEA_SHIFT 2 +#define M98090_MIXHPL_LINEA_WIDTH 1 +#define M98090_MIXHPL_DACR_MASK (1<<1) +#define M98090_MIXHPL_DACR_SHIFT 1 +#define M98090_MIXHPL_DACR_WIDTH 1 +#define M98090_MIXHPL_DACL_MASK (1<<0) +#define M98090_MIXHPL_DACL_SHIFT 0 +#define M98090_MIXHPL_DACL_WIDTH 1 +#define M98090_MIXHPL_MASK (63<<0) +#define M98090_MIXHPL_SHIFT 0 +#define M98090_MIXHPL_WIDTH 6 + +/* + * M98090_REG_RIGHT_HP_MIXER + */ +#define M98090_MIXHPR_MIC2_MASK (1<<5) +#define M98090_MIXHPR_MIC2_SHIFT 5 +#define M98090_MIXHPR_MIC2_WIDTH 1 +#define M98090_MIXHPR_MIC1_MASK (1<<4) +#define M98090_MIXHPR_MIC1_SHIFT 4 +#define M98090_MIXHPR_MIC1_WIDTH 1 +#define M98090_MIXHPR_LINEB_MASK (1<<3) +#define M98090_MIXHPR_LINEB_SHIFT 3 +#define M98090_MIXHPR_LINEB_WIDTH 1 +#define M98090_MIXHPR_LINEA_MASK (1<<2) +#define M98090_MIXHPR_LINEA_SHIFT 2 +#define M98090_MIXHPR_LINEA_WIDTH 1 +#define M98090_MIXHPR_DACR_MASK (1<<1) +#define M98090_MIXHPR_DACR_SHIFT 1 +#define M98090_MIXHPR_DACR_WIDTH 1 +#define M98090_MIXHPR_DACL_MASK (1<<0) +#define M98090_MIXHPR_DACL_SHIFT 0 +#define M98090_MIXHPR_DACL_WIDTH 1 +#define M98090_MIXHPR_MASK (63<<0) +#define M98090_MIXHPR_SHIFT 0 +#define M98090_MIXHPR_WIDTH 6 + +/* + * M98090_REG_HP_CONTROL + */ +#define M98090_MIXHPRSEL_MASK (1<<5) +#define M98090_MIXHPRSEL_SHIFT 5 +#define M98090_MIXHPRSEL_WIDTH 1 +#define M98090_MIXHPLSEL_MASK (1<<4) +#define M98090_MIXHPLSEL_SHIFT 4 +#define M98090_MIXHPLSEL_WIDTH 1 +#define M98090_MIXHPRG_MASK (3<<2) +#define M98090_MIXHPRG_SHIFT 2 +#define M98090_MIXHPRG_WIDTH 2 +#define M98090_MIXHPRG_NUM (1<<M98090_MIXHPRG_WIDTH) +#define M98090_MIXHPLG_MASK (3<<0) +#define M98090_MIXHPLG_SHIFT 0 +#define M98090_MIXHPLG_WIDTH 2 +#define M98090_MIXHPLG_NUM (1<<M98090_MIXHPLG_WIDTH) + +/* + * M98090_REG_LEFT_HP_VOLUME + */ +#define M98090_HPLM_MASK (1<<7) +#define M98090_HPLM_SHIFT 7 +#define M98090_HPLM_WIDTH 1 +#define M98090_HPVOLL_MASK (31<<0) +#define M98090_HPVOLL_SHIFT 0 +#define M98090_HPVOLL_WIDTH 5 +#define M98090_HPVOLL_NUM (1<<M98090_HPVOLL_WIDTH) + +/* + * M98090_REG_RIGHT_HP_VOLUME + */ +#define M98090_HPRM_MASK (1<<7) +#define M98090_HPRM_SHIFT 7 +#define M98090_HPRM_WIDTH 1 +#define M98090_HPVOLR_MASK (31<<0) +#define M98090_HPVOLR_SHIFT 0 +#define M98090_HPVOLR_WIDTH 5 +#define M98090_HPVOLR_NUM (1<<M98090_HPVOLR_WIDTH) + +/* + * M98090_REG_LEFT_SPK_MIXER + */ +#define M98090_MIXSPL_MIC2_MASK (1<<5) +#define M98090_MIXSPL_MIC2_SHIFT 5 +#define M98090_MIXSPL_MIC2_WIDTH 1 +#define M98090_MIXSPL_MIC1_MASK (1<<4) +#define M98090_MIXSPL_MIC1_SHIFT 4 +#define M98090_MIXSPL_MIC1_WIDTH 1 +#define M98090_MIXSPL_LINEB_MASK (1<<3) +#define M98090_MIXSPL_LINEB_SHIFT 3 +#define M98090_MIXSPL_LINEB_WIDTH 1 +#define M98090_MIXSPL_LINEA_MASK (1<<2) +#define M98090_MIXSPL_LINEA_SHIFT 2 +#define M98090_MIXSPL_LINEA_WIDTH 1 +#define M98090_MIXSPL_DACR_MASK (1<<1) +#define M98090_MIXSPL_DACR_SHIFT 1 +#define M98090_MIXSPL_DACR_WIDTH 1 +#define M98090_MIXSPL_DACL_MASK (1<<0) +#define M98090_MIXSPL_DACL_SHIFT 0 +#define M98090_MIXSPL_DACL_WIDTH 1 +#define M98090_MIXSPL_MASK (63<<0) +#define M98090_MIXSPL_SHIFT 0 +#define M98090_MIXSPL_WIDTH 6 +#define M98090_MIXSPR_DACR_MASK (1<<1) +#define M98090_MIXSPR_DACR_SHIFT 1 +#define M98090_MIXSPR_DACR_WIDTH 1 + + +/* + * M98090_REG_RIGHT_SPK_MIXER + */ +#define M98090_SPK_SLAVE_MASK (1<<6) +#define M98090_SPK_SLAVE_SHIFT 6 +#define M98090_SPK_SLAVE_WIDTH 1 +#define M98090_MIXSPR_MIC2_MASK (1<<5) +#define M98090_MIXSPR_MIC2_SHIFT 5 +#define M98090_MIXSPR_MIC2_WIDTH 1 +#define M98090_MIXSPR_MIC1_MASK (1<<4) +#define M98090_MIXSPR_MIC1_SHIFT 4 +#define M98090_MIXSPR_MIC1_WIDTH 1 +#define M98090_MIXSPR_LINEB_MASK (1<<3) +#define M98090_MIXSPR_LINEB_SHIFT 3 +#define M98090_MIXSPR_LINEB_WIDTH 1 +#define M98090_MIXSPR_LINEA_MASK (1<<2) +#define M98090_MIXSPR_LINEA_SHIFT 2 +#define M98090_MIXSPR_LINEA_WIDTH 1 +#define M98090_MIXSPR_DACR_MASK (1<<1) +#define M98090_MIXSPR_DACR_SHIFT 1 +#define M98090_MIXSPR_DACR_WIDTH 1 +#define M98090_MIXSPR_DACL_MASK (1<<0) +#define M98090_MIXSPR_DACL_SHIFT 0 +#define M98090_MIXSPR_DACL_WIDTH 1 +#define M98090_MIXSPR_MASK (63<<0) +#define M98090_MIXSPR_SHIFT 0 +#define M98090_MIXSPR_WIDTH 6 + +/* + * M98090_REG_SPK_CONTROL + */ +#define M98090_MIXSPRG_MASK (3<<2) +#define M98090_MIXSPRG_SHIFT 2 +#define M98090_MIXSPRG_WIDTH 2 +#define M98090_MIXSPRG_NUM (1<<M98090_MIXSPRG_WIDTH) +#define M98090_MIXSPLG_MASK (3<<0) +#define M98090_MIXSPLG_SHIFT 0 +#define M98090_MIXSPLG_WIDTH 2 +#define M98090_MIXSPLG_NUM (1<<M98090_MIXSPLG_WIDTH) + +/* + * M98090_REG_LEFT_SPK_VOLUME + */ +#define M98090_SPLM_MASK (1<<7) +#define M98090_SPLM_SHIFT 7 +#define M98090_SPLM_WIDTH 1 +#define M98090_SPVOLL_MASK (63<<0) +#define M98090_SPVOLL_SHIFT 0 +#define M98090_SPVOLL_WIDTH 6 +#define M98090_SPVOLL_NUM 40 + +/* + * M98090_REG_RIGHT_SPK_VOLUME + */ +#define M98090_SPRM_MASK (1<<7) +#define M98090_SPRM_SHIFT 7 +#define M98090_SPRM_WIDTH 1 +#define M98090_SPVOLR_MASK (63<<0) +#define M98090_SPVOLR_SHIFT 0 +#define M98090_SPVOLR_WIDTH 6 +#define M98090_SPVOLR_NUM 40 + +/* + * M98090_REG_DRC_TIMING + */ +#define M98090_DRCEN_MASK (1<<7) +#define M98090_DRCEN_SHIFT 7 +#define M98090_DRCEN_WIDTH 1 +#define M98090_DRCEN_NUM (1<<M98090_DRCEN_WIDTH) +#define M98090_DRCRLS_MASK (7<<4) +#define M98090_DRCRLS_SHIFT 4 +#define M98090_DRCRLS_WIDTH 3 +#define M98090_DRCATK_MASK (7<<0) +#define M98090_DRCATK_SHIFT 0 +#define M98090_DRCATK_WIDTH 3 + +/* + * M98090_REG_DRC_COMPRESSOR + */ +#define M98090_DRCCMP_MASK (7<<5) +#define M98090_DRCCMP_SHIFT 5 +#define M98090_DRCCMP_WIDTH 3 +#define M98090_DRCTHC_MASK (31<<0) +#define M98090_DRCTHC_SHIFT 0 +#define M98090_DRCTHC_WIDTH 5 +#define M98090_DRCTHC_NUM (1<<M98090_DRCTHC_WIDTH) + +/* + * M98090_REG_DRC_EXPANDER + */ +#define M98090_DRCEXP_MASK (7<<5) +#define M98090_DRCEXP_SHIFT 5 +#define M98090_DRCEXP_WIDTH 3 +#define M98090_DRCTHE_MASK (31<<0) +#define M98090_DRCTHE_SHIFT 0 +#define M98090_DRCTHE_WIDTH 5 +#define M98090_DRCTHE_NUM (1<<M98090_DRCTHE_WIDTH) + +/* + * M98090_REG_DRC_GAIN + */ +#define M98090_DRCG_MASK (31<<0) +#define M98090_DRCG_SHIFT 0 +#define M98090_DRCG_WIDTH 5 +#define M98090_DRCG_NUM 13 + +/* + * M98090_REG_RCV_LOUTL_MIXER + */ +#define M98090_MIXRCVL_MIC2_MASK (1<<5) +#define M98090_MIXRCVL_MIC2_SHIFT 5 +#define M98090_MIXRCVL_MIC2_WIDTH 1 +#define M98090_MIXRCVL_MIC1_MASK (1<<4) +#define M98090_MIXRCVL_MIC1_SHIFT 4 +#define M98090_MIXRCVL_MIC1_WIDTH 1 +#define M98090_MIXRCVL_LINEB_MASK (1<<3) +#define M98090_MIXRCVL_LINEB_SHIFT 3 +#define M98090_MIXRCVL_LINEB_WIDTH 1 +#define M98090_MIXRCVL_LINEA_MASK (1<<2) +#define M98090_MIXRCVL_LINEA_SHIFT 2 +#define M98090_MIXRCVL_LINEA_WIDTH 1 +#define M98090_MIXRCVL_DACR_MASK (1<<1) +#define M98090_MIXRCVL_DACR_SHIFT 1 +#define M98090_MIXRCVL_DACR_WIDTH 1 +#define M98090_MIXRCVL_DACL_MASK (1<<0) +#define M98090_MIXRCVL_DACL_SHIFT 0 +#define M98090_MIXRCVL_DACL_WIDTH 1 +#define M98090_MIXRCVL_MASK (63<<0) +#define M98090_MIXRCVL_SHIFT 0 +#define M98090_MIXRCVL_WIDTH 6 + +/* + * M98090_REG_RCV_LOUTL_CONTROL + */ +#define M98090_MIXRCVLG_MASK (3<<0) +#define M98090_MIXRCVLG_SHIFT 0 +#define M98090_MIXRCVLG_WIDTH 2 +#define M98090_MIXRCVLG_NUM (1<<M98090_MIXRCVLG_WIDTH) + +/* + * M98090_REG_RCV_LOUTL_VOLUME + */ +#define M98090_RCVLM_MASK (1<<7) +#define M98090_RCVLM_SHIFT 7 +#define M98090_RCVLM_WIDTH 1 +#define M98090_RCVLVOL_MASK (31<<0) +#define M98090_RCVLVOL_SHIFT 0 +#define M98090_RCVLVOL_WIDTH 5 +#define M98090_RCVLVOL_NUM (1<<M98090_RCVLVOL_WIDTH) + +/* + * M98090_REG_LOUTR_MIXER + */ +#define M98090_LINMOD_MASK (1<<7) +#define M98090_LINMOD_SHIFT 7 +#define M98090_LINMOD_WIDTH 1 +#define M98090_MIXRCVR_MIC2_MASK (1<<5) +#define M98090_MIXRCVR_MIC2_SHIFT 5 +#define M98090_MIXRCVR_MIC2_WIDTH 1 +#define M98090_MIXRCVR_MIC1_MASK (1<<4) +#define M98090_MIXRCVR_MIC1_SHIFT 4 +#define M98090_MIXRCVR_MIC1_WIDTH 1 +#define M98090_MIXRCVR_LINEB_MASK (1<<3) +#define M98090_MIXRCVR_LINEB_SHIFT 3 +#define M98090_MIXRCVR_LINEB_WIDTH 1 +#define M98090_MIXRCVR_LINEA_MASK (1<<2) +#define M98090_MIXRCVR_LINEA_SHIFT 2 +#define M98090_MIXRCVR_LINEA_WIDTH 1 +#define M98090_MIXRCVR_DACR_MASK (1<<1) +#define M98090_MIXRCVR_DACR_SHIFT 1 +#define M98090_MIXRCVR_DACR_WIDTH 1 +#define M98090_MIXRCVR_DACL_MASK (1<<0) +#define M98090_MIXRCVR_DACL_SHIFT 0 +#define M98090_MIXRCVR_DACL_WIDTH 1 +#define M98090_MIXRCVR_MASK (63<<0) +#define M98090_MIXRCVR_SHIFT 0 +#define M98090_MIXRCVR_WIDTH 6 + +/* + * M98090_REG_LOUTR_CONTROL + */ +#define M98090_MIXRCVRG_MASK (3<<0) +#define M98090_MIXRCVRG_SHIFT 0 +#define M98090_MIXRCVRG_WIDTH 2 +#define M98090_MIXRCVRG_NUM (1<<M98090_MIXRCVRG_WIDTH) + +/* + * M98090_REG_LOUTR_VOLUME + */ +#define M98090_RCVRM_MASK (1<<7) +#define M98090_RCVRM_SHIFT 7 +#define M98090_RCVRM_WIDTH 1 +#define M98090_RCVRVOL_MASK (31<<0) +#define M98090_RCVRVOL_SHIFT 0 +#define M98090_RCVRVOL_WIDTH 5 +#define M98090_RCVRVOL_NUM (1<<M98090_RCVRVOL_WIDTH) + +/* + * M98090_REG_JACK_DETECT + */ +#define M98090_JDETEN_MASK (1<<7) +#define M98090_JDETEN_SHIFT 7 +#define M98090_JDETEN_WIDTH 1 +#define M98090_JDWK_MASK (1<<6) +#define M98090_JDWK_SHIFT 6 +#define M98090_JDWK_WIDTH 1 +#define M98090_JDEB_MASK (3<<0) +#define M98090_JDEB_SHIFT 0 +#define M98090_JDEB_WIDTH 2 +#define M98090_JDEB_25MS (0<<0) +#define M98090_JDEB_50MS (1<<0) +#define M98090_JDEB_100MS (2<<0) +#define M98090_JDEB_200MS (3<<0) + +/* + * M98090_REG_INPUT_ENABLE + */ +#define M98090_MBEN_MASK (1<<4) +#define M98090_MBEN_SHIFT 4 +#define M98090_MBEN_WIDTH 1 +#define M98090_LINEAEN_MASK (1<<3) +#define M98090_LINEAEN_SHIFT 3 +#define M98090_LINEAEN_WIDTH 1 +#define M98090_LINEBEN_MASK (1<<2) +#define M98090_LINEBEN_SHIFT 2 +#define M98090_LINEBEN_WIDTH 1 +#define M98090_ADREN_MASK (1<<1) +#define M98090_ADREN_SHIFT 1 +#define M98090_ADREN_WIDTH 1 +#define M98090_ADLEN_MASK (1<<0) +#define M98090_ADLEN_SHIFT 0 +#define M98090_ADLEN_WIDTH 1 + +/* + * M98090_REG_OUTPUT_ENABLE + */ +#define M98090_HPREN_MASK (1<<7) +#define M98090_HPREN_SHIFT 7 +#define M98090_HPREN_WIDTH 1 +#define M98090_HPLEN_MASK (1<<6) +#define M98090_HPLEN_SHIFT 6 +#define M98090_HPLEN_WIDTH 1 +#define M98090_SPREN_MASK (1<<5) +#define M98090_SPREN_SHIFT 5 +#define M98090_SPREN_WIDTH 1 +#define M98090_SPLEN_MASK (1<<4) +#define M98090_SPLEN_SHIFT 4 +#define M98090_SPLEN_WIDTH 1 +#define M98090_RCVLEN_MASK (1<<3) +#define M98090_RCVLEN_SHIFT 3 +#define M98090_RCVLEN_WIDTH 1 +#define M98090_RCVREN_MASK (1<<2) +#define M98090_RCVREN_SHIFT 2 +#define M98090_RCVREN_WIDTH 1 +#define M98090_DAREN_MASK (1<<1) +#define M98090_DAREN_SHIFT 1 +#define M98090_DAREN_WIDTH 1 +#define M98090_DALEN_MASK (1<<0) +#define M98090_DALEN_SHIFT 0 +#define M98090_DALEN_WIDTH 1 + +/* + * M98090_REG_LEVEL_CONTROL + */ +#define M98090_ZDENN_MASK (1<<2) +#define M98090_ZDENN_SHIFT 2 +#define M98090_ZDENN_WIDTH 1 +#define M98090_ZDENN_NUM (1<<M98090_ZDENN_WIDTH) +#define M98090_VS2ENN_MASK (1<<1) +#define M98090_VS2ENN_SHIFT 1 +#define M98090_VS2ENN_WIDTH 1 +#define M98090_VS2ENN_NUM (1<<M98090_VS2ENN_WIDTH) +#define M98090_VSENN_MASK (1<<0) +#define M98090_VSENN_SHIFT 0 +#define M98090_VSENN_WIDTH 1 +#define M98090_VSENN_NUM (1<<M98090_VSENN_WIDTH) + +/* + * M98090_REG_DSP_FILTER_ENABLE + */ +#define M98090_DMIC34BQEN_MASK (1<<4) +#define M98090_DMIC34BQEN_SHIFT 4 +#define M98090_DMIC34BQEN_WIDTH 1 +#define M98090_DMIC34BQEN_NUM (1<<M98090_DMIC34BQEN_WIDTH) +#define M98090_ADCBQEN_MASK (1<<3) +#define M98090_ADCBQEN_SHIFT 3 +#define M98090_ADCBQEN_WIDTH 1 +#define M98090_ADCBQEN_NUM (1<<M98090_ADCBQEN_WIDTH) +#define M98090_EQ3BANDEN_MASK (1<<2) +#define M98090_EQ3BANDEN_SHIFT 2 +#define M98090_EQ3BANDEN_WIDTH 1 +#define M98090_EQ3BANDEN_NUM (1<<M98090_EQ3BANDEN_WIDTH) +#define M98090_EQ5BANDEN_MASK (1<<1) +#define M98090_EQ5BANDEN_SHIFT 1 +#define M98090_EQ5BANDEN_WIDTH 1 +#define M98090_EQ5BANDEN_NUM (1<<M98090_EQ5BANDEN_WIDTH) +#define M98090_EQ7BANDEN_MASK (1<<0) +#define M98090_EQ7BANDEN_SHIFT 0 +#define M98090_EQ7BANDEN_WIDTH 1 +#define M98090_EQ7BANDEN_NUM (1<<M98090_EQ7BANDEN_WIDTH) + +/* + * M98090_REG_BIAS_CONTROL + */ +#define M98090_VCM_MODE_MASK (1<<0) +#define M98090_VCM_MODE_SHIFT 0 +#define M98090_VCM_MODE_WIDTH 1 +#define M98090_VCM_MODE_NUM (1<<M98090_VCM_MODE_WIDTH) + +/* + * M98090_REG_DAC_CONTROL + */ +#define M98090_PERFMODE_MASK (1<<1) +#define M98090_PERFMODE_SHIFT 1 +#define M98090_PERFMODE_WIDTH 1 +#define M98090_PERFMODE_NUM (1<<M98090_PERFMODE_WIDTH) +#define M98090_DACHP_MASK (1<<0) +#define M98090_DACHP_SHIFT 0 +#define M98090_DACHP_WIDTH 1 +#define M98090_DACHP_NUM (1<<M98090_DACHP_WIDTH) + +/* + * M98090_REG_ADC_CONTROL + */ +#define M98090_OSR128_MASK (1<<2) +#define M98090_OSR128_SHIFT 2 +#define M98090_OSR128_WIDTH 1 +#define M98090_ADCDITHER_MASK (1<<1) +#define M98090_ADCDITHER_SHIFT 1 +#define M98090_ADCDITHER_WIDTH 1 +#define M98090_ADCDITHER_NUM (1<<M98090_ADCDITHER_WIDTH) +#define M98090_ADCHP_MASK (1<<0) +#define M98090_ADCHP_SHIFT 0 +#define M98090_ADCHP_WIDTH 1 +#define M98090_ADCHP_NUM (1<<M98090_ADCHP_WIDTH) + +/* + * M98090_REG_DEVICE_SHUTDOWN + */ +#define M98090_SHDNN_MASK (1<<7) +#define M98090_SHDNN_SHIFT 7 +#define M98090_SHDNN_WIDTH 1 + +/* + * M98090_REG_EQUALIZER_BASE + */ +#define M98090_B0_1_HI_MASK (255<<0) +#define M98090_B0_1_HI_SHIFT 0 +#define M98090_B0_1_HI_WIDTH 8 +#define M98090_B0_1_MID_MASK (255<<0) +#define M98090_B0_1_MID_SHIFT 0 +#define M98090_B0_1_MID_WIDTH 8 +#define M98090_B0_1_LO_MASK (255<<0) +#define M98090_B0_1_LO_SHIFT 0 +#define M98090_B0_1_LO_WIDTH 8 +#define M98090_B1_1_HI_MASK (255<<0) +#define M98090_B1_1_HI_SHIFT 0 +#define M98090_B1_1_HI_WIDTH 8 +#define M98090_B1_1_MID_MASK (255<<0) +#define M98090_B1_1_MID_SHIFT 0 +#define M98090_B1_1_MID_WIDTH 8 +#define M98090_B1_1_LO_MASK (255<<0) +#define M98090_B1_1_LO_SHIFT 0 +#define M98090_B1_1_LO_WIDTH 8 +#define M98090_B2_1_HI_MASK (255<<0) +#define M98090_B2_1_HI_SHIFT 0 +#define M98090_B2_1_HI_WIDTH 8 +#define M98090_B2_1_MID_MASK (255<<0) +#define M98090_B2_1_MID_SHIFT 0 +#define M98090_B2_1_MID_WIDTH 8 +#define M98090_B2_1_LO_MASK (255<<0) +#define M98090_B2_1_LO_SHIFT 0 +#define M98090_B2_1_LO_WIDTH 8 +#define M98090_A1_1_HI_MASK (255<<0) +#define M98090_A1_1_HI_SHIFT 0 +#define M98090_A1_1_HI_WIDTH 8 +#define M98090_A1_1_MID_MASK (255<<0) +#define M98090_A1_1_MID_SHIFT 0 +#define M98090_A1_1_MID_WIDTH 8 +#define M98090_A1_1_LO_MASK (255<<0) +#define M98090_A1_1_LO_SHIFT 0 +#define M98090_A1_1_LO_WIDTH 8 +#define M98090_A2_1_HI_MASK (255<<0) +#define M98090_A2_1_HI_SHIFT 0 +#define M98090_A2_1_HI_WIDTH 8 +#define M98090_A2_1_MID_MASK (255<<0) +#define M98090_A2_1_MID_SHIFT 0 +#define M98090_A2_1_MID_WIDTH 8 +#define M98090_A2_1_LO_MASK (255<<0) +#define M98090_A2_1_LO_SHIFT 0 +#define M98090_A2_1_LO_WIDTH 8 + +#define M98090_COEFS_PER_BAND 5 +#define M98090_COEFS_BLK_SZ (M98090_COEFS_PER_BAND * 3) +#define M98090_COEFS_MAX_SZ (M98090_COEFS_BLK_SZ * 7) + +/* + * M98090_REG_RECORD_BIQUAD_BASE + */ +#define M98090_REC_B0_HI_MASK (255<<0) +#define M98090_REC_B0_HI_SHIFT 0 +#define M98090_REC_B0_HI_WIDTH 8 +#define M98090_REC_B0_MID_MASK (255<<0) +#define M98090_REC_B0_MID_SHIFT 0 +#define M98090_REC_B0_MID_WIDTH 8 +#define M98090_REC_B0_LO_MASK (255<<0) +#define M98090_REC_B0_LO_SHIFT 0 +#define M98090_REC_B0_LO_WIDTH 8 +#define M98090_REC_B1_HI_MASK (255<<0) +#define M98090_REC_B1_HI_SHIFT 0 +#define M98090_REC_B1_HI_WIDTH 8 +#define M98090_REC_B1_MID_MASK (255<<0) +#define M98090_REC_B1_MID_SHIFT 0 +#define M98090_REC_B1_MID_WIDTH 8 +#define M98090_REC_B1_LO_MASK (255<<0) +#define M98090_REC_B1_LO_SHIFT 0 +#define M98090_REC_B1_LO_WIDTH 8 +#define M98090_REC_B2_HI_MASK (255<<0) +#define M98090_REC_B2_HI_SHIFT 0 +#define M98090_REC_B2_HI_WIDTH 8 +#define M98090_REC_B2_MID_MASK (255<<0) +#define M98090_REC_B2_MID_SHIFT 0 +#define M98090_REC_B2_MID_WIDTH 8 +#define M98090_REC_B2_LO_MASK (255<<0) +#define M98090_REC_B2_LO_SHIFT 0 +#define M98090_REC_B2_LO_WIDTH 8 +#define M98090_REC_A1_HI_MASK (255<<0) +#define M98090_REC_A1_HI_SHIFT 0 +#define M98090_REC_A1_HI_WIDTH 8 +#define M98090_REC_A1_MID_MASK (255<<0) +#define M98090_REC_A1_MID_SHIFT 0 +#define M98090_REC_A1_MID_WIDTH 8 +#define M98090_REC_A1_LO_MASK (255<<0) +#define M98090_REC_A1_LO_SHIFT 0 +#define M98090_REC_A1_LO_WIDTH 8 +#define M98090_REC_A2_HI_MASK (255<<0) +#define M98090_REC_A2_HI_SHIFT 0 +#define M98090_REC_A2_HI_WIDTH 8 +#define M98090_REC_A2_MID_MASK (255<<0) +#define M98090_REC_A2_MID_SHIFT 0 +#define M98090_REC_A2_MID_WIDTH 8 +#define M98090_REC_A2_LO_MASK (255<<0) +#define M98090_REC_A2_LO_SHIFT 0 +#define M98090_REC_A2_LO_WIDTH 8 + +/* + * M98090_REG_DMIC3_VOLUME + */ +#define M98090_DMIC_AV3G_MASK (7<<4) +#define M98090_DMIC_AV3G_SHIFT 4 +#define M98090_DMIC_AV3G_WIDTH 3 +#define M98090_DMIC_AV3G_NUM (1<<M98090_DMIC_AV3G_WIDTH) +#define M98090_DMIC_AV3_MASK (15<<0) +#define M98090_DMIC_AV3_SHIFT 0 +#define M98090_DMIC_AV3_WIDTH 4 +#define M98090_DMIC_AV3_NUM (1<<M98090_DMIC_AV3_WIDTH) + +/* + * M98090_REG_DMIC4_VOLUME + */ +#define M98090_DMIC_AV4G_MASK (7<<4) +#define M98090_DMIC_AV4G_SHIFT 4 +#define M98090_DMIC_AV4G_WIDTH 3 +#define M98090_DMIC_AV4G_NUM (1<<M98090_DMIC_AV4G_WIDTH) +#define M98090_DMIC_AV4_MASK (15<<0) +#define M98090_DMIC_AV4_SHIFT 0 +#define M98090_DMIC_AV4_WIDTH 4 +#define M98090_DMIC_AV4_NUM (1<<M98090_DMIC_AV4_WIDTH) + +/* + * M98090_REG_DMIC34_BQ_PREATTEN + */ +#define M98090_AV34BQ_MASK (15<<0) +#define M98090_AV34BQ_SHIFT 0 +#define M98090_AV34BQ_WIDTH 4 +#define M98090_AV34BQ_NUM (1<<M98090_AV34BQ_WIDTH) + +/* + * M98090_REG_RECORD_TDM_SLOT + */ +#define M98090_TDM_SLOTADCL_MASK (3<<6) +#define M98090_TDM_SLOTADCL_SHIFT 6 +#define M98090_TDM_SLOTADCL_WIDTH 2 +#define M98090_TDM_SLOTADCL_NUM (1<<M98090_TDM_SLOTADCL_WIDTH) +#define M98090_TDM_SLOTADCR_MASK (3<<4) +#define M98090_TDM_SLOTADCR_SHIFT 4 +#define M98090_TDM_SLOTADCR_WIDTH 2 +#define M98090_TDM_SLOTADCR_NUM (1<<M98090_TDM_SLOTADCR_WIDTH) +#define M98090_TDM_SLOTDMIC3_MASK (3<<2) +#define M98090_TDM_SLOTDMIC3_SHIFT 2 +#define M98090_TDM_SLOTDMIC3_WIDTH 2 +#define M98090_TDM_SLOTDMIC3_NUM (1<<M98090_TDM_SLOTDMIC3_WIDTH) +#define M98090_TDM_SLOTDMIC4_MASK (3<<0) +#define M98090_TDM_SLOTDMIC4_SHIFT 0 +#define M98090_TDM_SLOTDMIC4_WIDTH 2 +#define M98090_TDM_SLOTDMIC4_NUM (1<<M98090_TDM_SLOTDMIC4_WIDTH) + +/* + * M98090_REG_SAMPLE_RATE + */ +#define M98090_DMIC34_ZEROPAD_MASK (1<<4) +#define M98090_DMIC34_ZEROPAD_SHIFT 4 +#define M98090_DMIC34_ZEROPAD_WIDTH 1 +#define M98090_DMIC34_ZEROPAD_NUM (1<<M98090_DIGMIC4_WIDTH) +#define M98090_DMIC34_SRDIV_MASK (7<<0) +#define M98090_DMIC34_SRDIV_SHIFT 0 +#define M98090_DMIC34_SRDIV_WIDTH 3 + +/* + * M98090_REG_DMIC34_BIQUAD_BASE + */ +#define M98090_DMIC34_B0_HI_MASK (255<<0) +#define M98090_DMIC34_B0_HI_SHIFT 0 +#define M98090_DMIC34_B0_HI_WIDTH 8 +#define M98090_DMIC34_B0_MID_MASK (255<<0) +#define M98090_DMIC34_B0_MID_SHIFT 0 +#define M98090_DMIC34_B0_MID_WIDTH 8 +#define M98090_DMIC34_B0_LO_MASK (255<<0) +#define M98090_DMIC34_B0_LO_SHIFT 0 +#define M98090_DMIC34_B0_LO_WIDTH 8 +#define M98090_DMIC34_B1_HI_MASK (255<<0) +#define M98090_DMIC34_B1_HI_SHIFT 0 +#define M98090_DMIC34_B1_HI_WIDTH 8 +#define M98090_DMIC34_B1_MID_MASK (255<<0) +#define M98090_DMIC34_B1_MID_SHIFT 0 +#define M98090_DMIC34_B1_MID_WIDTH 8 +#define M98090_DMIC34_B1_LO_MASK (255<<0) +#define M98090_DMIC34_B1_LO_SHIFT 0 +#define M98090_DMIC34_B1_LO_WIDTH 8 +#define M98090_DMIC34_B2_HI_MASK (255<<0) +#define M98090_DMIC34_B2_HI_SHIFT 0 +#define M98090_DMIC34_B2_HI_WIDTH 8 +#define M98090_DMIC34_B2_MID_MASK (255<<0) +#define M98090_DMIC34_B2_MID_SHIFT 0 +#define M98090_DMIC34_B2_MID_WIDTH 8 +#define M98090_DMIC34_B2_LO_MASK (255<<0) +#define M98090_DMIC34_B2_LO_SHIFT 0 +#define M98090_DMIC34_B2_LO_WIDTH 8 +#define M98090_DMIC34_A1_HI_MASK (255<<0) +#define M98090_DMIC34_A1_HI_SHIFT 0 +#define M98090_DMIC34_A1_HI_WIDTH 8 +#define M98090_DMIC34_A1_MID_MASK (255<<0) +#define M98090_DMIC34_A1_MID_SHIFT 0 +#define M98090_DMIC34_A1_MID_WIDTH 8 +#define M98090_DMIC34_A1_LO_MASK (255<<0) +#define M98090_DMIC34_A1_LO_SHIFT 0 +#define M98090_DMIC34_A1_LO_WIDTH 8 +#define M98090_DMIC34_A2_HI_MASK (255<<0) +#define M98090_DMIC34_A2_HI_SHIFT 0 +#define M98090_DMIC34_A2_HI_WIDTH 8 +#define M98090_DMIC34_A2_MID_MASK (255<<0) +#define M98090_DMIC34_A2_MID_SHIFT 0 +#define M98090_DMIC34_A2_MID_WIDTH 8 +#define M98090_DMIC34_A2_LO_MASK (255<<0) +#define M98090_DMIC34_A2_LO_SHIFT 0 +#define M98090_DMIC34_A2_LO_WIDTH 8 + +#define M98090_JACK_STATE_NO_HEADSET 0 +#define M98090_JACK_STATE_NO_HEADSET_2 1 +#define M98090_JACK_STATE_HEADPHONE 2 +#define M98090_JACK_STATE_HEADSET 3 + +/* + * M98090_REG_REVISION_ID + */ +#define M98090_REVID_MASK (255<<0) +#define M98090_REVID_SHIFT 0 +#define M98090_REVID_WIDTH 8 +#define M98090_REVID_NUM (1<<M98090_REVID_WIDTH) + +#define M98090_BYTE1(w) ((w >> 8) & 0xff) +#define M98090_BYTE0(w) (w & 0xff) + +/* Silicon revision number */ +#define M98090_REVA 0x40 +#define M98091_REVA 0x50 + +enum max98090_type { + MAX98090, + MAX98091, +}; + +struct max98090_cdata { + unsigned int rate; + unsigned int fmt; +}; + +struct max98090_priv { + struct regmap *regmap; + struct snd_soc_codec *codec; + enum max98090_type devtype; + void *control_data; + struct max98090_pdata *pdata; + unsigned int sysclk; + unsigned int bclk; + unsigned int lrclk; + struct max98090_cdata dai[1]; + int irq; + int jack_state; + struct delayed_work jack_work; + struct snd_soc_jack *jack; + unsigned int dai_fmt; + int tdm_slots; + int tdm_width; + u8 lin_state; + unsigned int pa1en; + unsigned int pa2en; + unsigned int extmic_mux; + unsigned int sidetone; +}; + +int max98090_mic_detect(struct snd_soc_codec *codec, + struct snd_soc_jack *jack); + +#endif diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index 5708a973a776..65d09d60b7c6 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -85,6 +85,9 @@ struct aic3x_priv { #define AIC3X_MODEL_33 1 #define AIC3X_MODEL_3007 2 u16 model; + + /* Selects the micbias voltage */ + enum aic3x_micbias_voltage micbias_vg; }; /* @@ -195,6 +198,37 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, return ret; } +/* + * mic bias power on/off share the same register bits with + * output voltage of mic bias. when power on mic bias, we + * need reclaim it to voltage value. + * 0x0 = Powered off + * 0x1 = MICBIAS output is powered to 2.0V, + * 0x2 = MICBIAS output is powered to 2.5V + * 0x3 = MICBIAS output is connected to AVDD + */ +static int mic_bias_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + /* change mic bias voltage to user defined */ + snd_soc_update_bits(codec, MICBIAS_CTRL, + MICBIAS_LEVEL_MASK, + aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); + break; + + case SND_SOC_DAPM_PRE_PMD: + snd_soc_update_bits(codec, MICBIAS_CTRL, + MICBIAS_LEVEL_MASK, 0); + break; + } + return 0; +} + static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; static const char *aic3x_left_hpcom_mux[] = @@ -596,12 +630,9 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), /* Mic Bias */ - SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", - MICBIAS_CTRL, 6, 3, 1, 0), - SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", - MICBIAS_CTRL, 6, 3, 2, 0), - SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", - MICBIAS_CTRL, 6, 3, 3, 0), + SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, + mic_bias_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), /* Output mixers */ SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, @@ -1210,13 +1241,13 @@ static struct snd_soc_dai_driver aic3x_dai = { .name = "tlv320aic3x-hifi", .playback = { .stream_name = "Playback", - .channels_min = 1, + .channels_min = 2, .channels_max = 2, .rates = AIC3X_RATES, .formats = AIC3X_FORMATS,}, .capture = { .stream_name = "Capture", - .channels_min = 1, + .channels_min = 2, .channels_max = 2, .rates = AIC3X_RATES, .formats = AIC3X_FORMATS,}, @@ -1386,6 +1417,24 @@ static int aic3x_probe(struct snd_soc_codec *codec) if (aic3x->model == AIC3X_MODEL_3007) snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); + /* set mic bias voltage */ + switch (aic3x->micbias_vg) { + case AIC3X_MICBIAS_2_0V: + case AIC3X_MICBIAS_2_5V: + case AIC3X_MICBIAS_AVDDV: + snd_soc_update_bits(codec, MICBIAS_CTRL, + MICBIAS_LEVEL_MASK, + (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); + break; + case AIC3X_MICBIAS_OFF: + /* + * noting to do. target won't enter here. This is just to avoid + * compile time warning "warning: enumeration value + * 'AIC3X_MICBIAS_OFF' not handled in switch" + */ + break; + } + aic3x_add_widgets(codec); list_add(&aic3x->list, &reset_list); @@ -1461,6 +1510,7 @@ static int aic3x_i2c_probe(struct i2c_client *i2c, struct aic3x_setup_data *ai3x_setup; struct device_node *np = i2c->dev.of_node; int ret; + u32 value; aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); if (aic3x == NULL) { @@ -1474,6 +1524,7 @@ static int aic3x_i2c_probe(struct i2c_client *i2c, if (pdata) { aic3x->gpio_reset = pdata->gpio_reset; aic3x->setup = pdata->setup; + aic3x->micbias_vg = pdata->micbias_vg; } else if (np) { ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup), GFP_KERNEL); @@ -1493,6 +1544,26 @@ static int aic3x_i2c_probe(struct i2c_client *i2c, aic3x->setup = ai3x_setup; } + if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { + switch (value) { + case 1 : + aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; + break; + case 2 : + aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; + break; + case 3 : + aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; + break; + default : + aic3x->micbias_vg = AIC3X_MICBIAS_OFF; + dev_err(&i2c->dev, "Unsuitable MicBias voltage " + "found in DT\n"); + } + } else { + aic3x->micbias_vg = AIC3X_MICBIAS_OFF; + } + } else { aic3x->gpio_reset = -1; } diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h index 6db3c41b0163..e521ac3ddde8 100644 --- a/sound/soc/codecs/tlv320aic3x.h +++ b/sound/soc/codecs/tlv320aic3x.h @@ -238,6 +238,10 @@ /* Default input volume */ #define DEFAULT_GAIN 0x20 +/* MICBIAS Control Register */ +#define MICBIAS_LEVEL_SHIFT (6) +#define MICBIAS_LEVEL_MASK (3 << 6) + /* headset detection / button API */ /* The AIC3x supports detection of stereo headsets (GND + left + right signal) diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c index 782b0cded2e6..4f358393d6d6 100644 --- a/sound/soc/codecs/tlv320dac33.c +++ b/sound/soc/codecs/tlv320dac33.c @@ -1452,20 +1452,6 @@ static int dac33_soc_remove(struct snd_soc_codec *codec) return 0; } -static int dac33_soc_suspend(struct snd_soc_codec *codec) -{ - dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); - - return 0; -} - -static int dac33_soc_resume(struct snd_soc_codec *codec) -{ - dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - - return 0; -} - static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { .read = dac33_read_reg_cache, .write = dac33_write_locked, @@ -1476,8 +1462,6 @@ static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { .reg_cache_default = dac33_reg, .probe = dac33_soc_probe, .remove = dac33_soc_remove, - .suspend = dac33_soc_suspend, - .resume = dac33_soc_resume, .controls = dac33_snd_controls, .num_controls = ARRAY_SIZE(dac33_snd_controls), diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c index 63b280b06035..8e6e5b016021 100644 --- a/sound/soc/codecs/twl4030.c +++ b/sound/soc/codecs/twl4030.c @@ -41,6 +41,11 @@ /* Register descriptions are here */ #include <linux/mfd/twl4030-audio.h> +/* TWL4030 PMBR1 Register */ +#define TWL4030_PMBR1_REG 0x0D +/* TWL4030 PMBR1 Register GPIO6 mux bits */ +#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2) + /* Shadow register used by the audio driver */ #define TWL4030_REG_SW_SHADOW 0x4A #define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1) @@ -348,19 +353,32 @@ static void twl4030_init_chip(struct snd_soc_codec *codec) pdata = twl4030_get_pdata(codec); - if (pdata && pdata->hs_extmute && - gpio_is_valid(pdata->hs_extmute_gpio)) { - int ret; - - if (!pdata->hs_extmute_gpio) - dev_warn(codec->dev, - "Extmute GPIO is 0 is this correct?\n"); - - ret = gpio_request_one(pdata->hs_extmute_gpio, - GPIOF_OUT_INIT_LOW, "hs_extmute"); - if (ret) { - dev_err(codec->dev, "Failed to get hs_extmute GPIO\n"); - pdata->hs_extmute_gpio = -1; + if (pdata && pdata->hs_extmute) { + if (gpio_is_valid(pdata->hs_extmute_gpio)) { + int ret; + + if (!pdata->hs_extmute_gpio) + dev_warn(codec->dev, + "Extmute GPIO is 0 is this correct?\n"); + + ret = gpio_request_one(pdata->hs_extmute_gpio, + GPIOF_OUT_INIT_LOW, + "hs_extmute"); + if (ret) { + dev_err(codec->dev, + "Failed to get hs_extmute GPIO\n"); + pdata->hs_extmute_gpio = -1; + } + } else { + u8 pin_mux; + + /* Set TWL4030 GPIO6 as EXTMUTE signal */ + twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux, + TWL4030_PMBR1_REG); + pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03); + pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02); + twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux, + TWL4030_PMBR1_REG); } } @@ -1306,6 +1324,9 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0, + TWL4030_REG_VOICE_IF, 6, 0), + /* Analog bypasses */ SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, &twl4030_dapm_abypassr1_control), @@ -1438,6 +1459,9 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0, + TWL4030_REG_VOICE_IF, 5, 0), + /* Analog/Digital mic path selection. TX1 Left/Right: either analog Left/Right or Digimic0 TX2 Left/Right: either analog Left/Right or Digimic1 */ @@ -1473,10 +1497,15 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0, NULL, 0), - SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), - SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), - SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), + /* Microphone bias */ + SND_SOC_DAPM_SUPPLY("Mic Bias 1", + TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Mic Bias 2", + TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("Headset Mic Bias", + TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0), }; static const struct snd_soc_dapm_route intercon[] = { @@ -1485,17 +1514,16 @@ static const struct snd_soc_dapm_route intercon[] = { {"DAC Left1", NULL, "HiFi Playback"}, {"DAC Right2", NULL, "HiFi Playback"}, {"DAC Left2", NULL, "HiFi Playback"}, - {"DAC Voice", NULL, "Voice Playback"}, + {"DAC Voice", NULL, "VAIFIN"}, /* ADC -> Stream mapping */ {"HiFi Capture", NULL, "ADC Virtual Left1"}, {"HiFi Capture", NULL, "ADC Virtual Right1"}, {"HiFi Capture", NULL, "ADC Virtual Left2"}, {"HiFi Capture", NULL, "ADC Virtual Right2"}, - {"Voice Capture", NULL, "ADC Virtual Left1"}, - {"Voice Capture", NULL, "ADC Virtual Right1"}, - {"Voice Capture", NULL, "ADC Virtual Left2"}, - {"Voice Capture", NULL, "ADC Virtual Right2"}, + {"VAIFOUT", NULL, "ADC Virtual Left2"}, + {"VAIFOUT", NULL, "ADC Virtual Right2"}, + {"VAIFOUT", NULL, "VIF Enable"}, {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, @@ -1510,6 +1538,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"DAC Right1", NULL, "AIF Enable"}, {"DAC Left2", NULL, "AIF Enable"}, {"DAC Right1", NULL, "AIF Enable"}, + {"DAC Voice", NULL, "VIF Enable"}, {"Digital R2 Playback Mixer", NULL, "AIF Enable"}, {"Digital L2 Playback Mixer", NULL, "AIF Enable"}, @@ -2267,18 +2296,6 @@ static struct snd_soc_dai_driver twl4030_dai[] = { }, }; -static int twl4030_soc_suspend(struct snd_soc_codec *codec) -{ - twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); - return 0; -} - -static int twl4030_soc_resume(struct snd_soc_codec *codec) -{ - twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - return 0; -} - static int twl4030_soc_probe(struct snd_soc_codec *codec) { struct twl4030_priv *twl4030; @@ -2316,8 +2333,6 @@ static int twl4030_soc_remove(struct snd_soc_codec *codec) static struct snd_soc_codec_driver soc_codec_dev_twl4030 = { .probe = twl4030_soc_probe, .remove = twl4030_soc_remove, - .suspend = twl4030_soc_suspend, - .resume = twl4030_soc_resume, .read = twl4030_read_reg_cache, .write = twl4030_write, .set_bias_level = twl4030_set_bias_level, diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 3fc3fc64dd8b..9b9a6e587610 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -69,13 +69,8 @@ struct twl6040_data { int hs_power_mode_locked; unsigned int clk_in; unsigned int sysclk; - u16 hs_left_step; - u16 hs_right_step; - u16 hf_left_step; - u16 hf_right_step; struct twl6040_jack_data hs_jack; struct snd_soc_codec *codec; - struct workqueue_struct *workqueue; struct mutex mutex; }; @@ -404,8 +399,7 @@ static irqreturn_t twl6040_audio_handler(int irq, void *data) struct snd_soc_codec *codec = data; struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - queue_delayed_work(priv->workqueue, &priv->hs_jack.work, - msecs_to_jiffies(200)); + schedule_delayed_work(&priv->hs_jack.work, msecs_to_jiffies(200)); return IRQ_HANDLED; } @@ -1115,7 +1109,6 @@ static int twl6040_suspend(struct snd_soc_codec *codec) static int twl6040_resume(struct snd_soc_codec *codec) { twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - twl6040_set_bias_level(codec, codec->dapm.suspend_bias_level); return 0; } @@ -1127,83 +1120,46 @@ static int twl6040_resume(struct snd_soc_codec *codec) static int twl6040_probe(struct snd_soc_codec *codec) { struct twl6040_data *priv; - struct twl6040_codec_data *pdata = dev_get_platdata(codec->dev); struct platform_device *pdev = container_of(codec->dev, struct platform_device, dev); int ret = 0; - priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL); + priv = devm_kzalloc(codec->dev, sizeof(*priv), GFP_KERNEL); if (priv == NULL) return -ENOMEM; + snd_soc_codec_set_drvdata(codec, priv); priv->codec = codec; codec->control_data = dev_get_drvdata(codec->dev->parent); - if (pdata && pdata->hs_left_step && pdata->hs_right_step) { - priv->hs_left_step = pdata->hs_left_step; - priv->hs_right_step = pdata->hs_right_step; - } else { - priv->hs_left_step = 1; - priv->hs_right_step = 1; - } - - if (pdata && pdata->hf_left_step && pdata->hf_right_step) { - priv->hf_left_step = pdata->hf_left_step; - priv->hf_right_step = pdata->hf_right_step; - } else { - priv->hf_left_step = 1; - priv->hf_right_step = 1; - } - priv->plug_irq = platform_get_irq(pdev, 0); if (priv->plug_irq < 0) { dev_err(codec->dev, "invalid irq\n"); - ret = -EINVAL; - goto work_err; - } - - priv->workqueue = alloc_workqueue("twl6040-codec", 0, 0); - if (!priv->workqueue) { - ret = -ENOMEM; - goto work_err; + return -EINVAL; } INIT_DELAYED_WORK(&priv->hs_jack.work, twl6040_accessory_work); mutex_init(&priv->mutex); - ret = request_threaded_irq(priv->plug_irq, NULL, twl6040_audio_handler, - 0, "twl6040_irq_plug", codec); + ret = devm_request_threaded_irq(codec->dev, priv->plug_irq, NULL, + twl6040_audio_handler, IRQF_NO_SUSPEND, + "twl6040_irq_plug", codec); if (ret) { dev_err(codec->dev, "PLUG IRQ request failed: %d\n", ret); - goto plugirq_err; + return ret; } twl6040_init_chip(codec); /* power on device */ - ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - if (!ret) - return 0; - - /* Error path */ - free_irq(priv->plug_irq, codec); -plugirq_err: - destroy_workqueue(priv->workqueue); -work_err: - kfree(priv); - return ret; + return twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); } static int twl6040_remove(struct snd_soc_codec *codec) { - struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); - free_irq(priv->plug_irq, codec); - destroy_workqueue(priv->workqueue); - kfree(priv); return 0; } diff --git a/sound/soc/codecs/wm2000.c b/sound/soc/codecs/wm2000.c index 12bcae63a7f0..f2ac38b61a1b 100644 --- a/sound/soc/codecs/wm2000.c +++ b/sound/soc/codecs/wm2000.c @@ -26,6 +26,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/firmware.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/pm.h> #include <linux/i2c.h> @@ -62,6 +63,7 @@ enum wm2000_anc_mode { struct wm2000_priv { struct i2c_client *i2c; struct regmap *regmap; + struct clk *mclk; struct regulator_bulk_data supplies[WM2000_NUM_SUPPLIES]; @@ -71,11 +73,12 @@ struct wm2000_priv { unsigned int anc_eng_ena:1; unsigned int spk_ena:1; - unsigned int mclk_div:1; unsigned int speech_clarity:1; int anc_download_size; char *anc_download; + + struct mutex lock; }; static int wm2000_write(struct i2c_client *i2c, unsigned int reg, @@ -131,6 +134,7 @@ static int wm2000_poll_bit(struct i2c_client *i2c, static int wm2000_power_up(struct i2c_client *i2c, int analogue) { struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev); + unsigned long rate; int ret; BUG_ON(wm2000->anc_mode != ANC_OFF); @@ -143,7 +147,8 @@ static int wm2000_power_up(struct i2c_client *i2c, int analogue) return ret; } - if (!wm2000->mclk_div) { + rate = clk_get_rate(wm2000->mclk); + if (rate <= 13500000) { dev_dbg(&i2c->dev, "Disabling MCLK divider\n"); wm2000_write(i2c, WM2000_REG_SYS_CTL2, WM2000_MCLK_DIV2_ENA_CLR); @@ -550,6 +555,15 @@ static int wm2000_anc_transition(struct wm2000_priv *wm2000, return -EINVAL; } + /* Maintain clock while active */ + if (anc_transitions[i].source == ANC_OFF) { + ret = clk_prepare_enable(wm2000->mclk); + if (ret != 0) { + dev_err(&i2c->dev, "Failed to enable MCLK: %d\n", ret); + return ret; + } + } + for (j = 0; j < ARRAY_SIZE(anc_transitions[j].step); j++) { if (!anc_transitions[i].step[j]) break; @@ -559,7 +573,10 @@ static int wm2000_anc_transition(struct wm2000_priv *wm2000, return ret; } - return 0; + if (anc_transitions[i].dest == ANC_OFF) + clk_disable_unprepare(wm2000->mclk); + + return ret; } static int wm2000_anc_set_mode(struct wm2000_priv *wm2000) @@ -599,13 +616,20 @@ static int wm2000_anc_mode_put(struct snd_kcontrol *kcontrol, struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); int anc_active = ucontrol->value.enumerated.item[0]; + int ret; if (anc_active > 1) return -EINVAL; + mutex_lock(&wm2000->lock); + wm2000->anc_active = anc_active; - return wm2000_anc_set_mode(wm2000); + ret = wm2000_anc_set_mode(wm2000); + + mutex_unlock(&wm2000->lock); + + return ret; } static int wm2000_speaker_get(struct snd_kcontrol *kcontrol, @@ -625,16 +649,24 @@ static int wm2000_speaker_put(struct snd_kcontrol *kcontrol, struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); int val = ucontrol->value.enumerated.item[0]; + int ret; if (val > 1) return -EINVAL; + mutex_lock(&wm2000->lock); + wm2000->spk_ena = val; - return wm2000_anc_set_mode(wm2000); + ret = wm2000_anc_set_mode(wm2000); + + mutex_unlock(&wm2000->lock); + + return ret; } static const struct snd_kcontrol_new wm2000_controls[] = { + SOC_SINGLE("ANC Volume", WM2000_REG_ANC_GAIN_CTRL, 0, 255, 0), SOC_SINGLE_BOOL_EXT("WM2000 ANC Switch", 0, wm2000_anc_mode_get, wm2000_anc_mode_put), @@ -648,6 +680,9 @@ static int wm2000_anc_power_event(struct snd_soc_dapm_widget *w, { struct snd_soc_codec *codec = w->codec; struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); + int ret; + + mutex_lock(&wm2000->lock); if (SND_SOC_DAPM_EVENT_ON(event)) wm2000->anc_eng_ena = 1; @@ -655,7 +690,11 @@ static int wm2000_anc_power_event(struct snd_soc_dapm_widget *w, if (SND_SOC_DAPM_EVENT_OFF(event)) wm2000->anc_eng_ena = 0; - return wm2000_anc_set_mode(wm2000); + ret = wm2000_anc_set_mode(wm2000); + + mutex_unlock(&wm2000->lock); + + return ret; } static const struct snd_soc_dapm_widget wm2000_dapm_widgets[] = { @@ -702,6 +741,9 @@ static bool wm2000_readable_reg(struct device *dev, unsigned int reg) { switch (reg) { case WM2000_REG_SYS_START: + case WM2000_REG_ANC_GAIN_CTRL: + case WM2000_REG_MSE_TH1: + case WM2000_REG_MSE_TH2: case WM2000_REG_SPEECH_CLARITY: case WM2000_REG_SYS_WATCHDOG: case WM2000_REG_ANA_VMID_PD_TIME: @@ -737,6 +779,8 @@ static int wm2000_probe(struct snd_soc_codec *codec) { struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); + snd_soc_codec_set_cache_io(codec, 16, 8, SND_SOC_REGMAP); + /* This will trigger a transition to standby mode by default */ wm2000_anc_set_mode(wm2000); @@ -782,6 +826,8 @@ static int wm2000_i2c_probe(struct i2c_client *i2c, return -ENOMEM; } + mutex_init(&wm2000->lock); + dev_set_drvdata(&i2c->dev, wm2000); wm2000->regmap = devm_regmap_init_i2c(i2c, &wm2000_regmap); @@ -823,10 +869,16 @@ static int wm2000_i2c_probe(struct i2c_client *i2c, reg = wm2000_read(i2c, WM2000_REG_REVISON); dev_info(&i2c->dev, "revision %c\n", reg + 'A'); + wm2000->mclk = devm_clk_get(&i2c->dev, "MCLK"); + if (IS_ERR(wm2000->mclk)) { + ret = PTR_ERR(wm2000->mclk); + dev_err(&i2c->dev, "Failed to get MCLK: %d\n", ret); + goto err_supplies; + } + filename = "wm2000_anc.bin"; pdata = dev_get_platdata(&i2c->dev); if (pdata) { - wm2000->mclk_div = pdata->mclkdiv2; wm2000->speech_clarity = !pdata->speech_enh_disable; if (pdata->download_file) diff --git a/sound/soc/codecs/wm2000.h b/sound/soc/codecs/wm2000.h index abcd82a93995..fb812cd9e77d 100644 --- a/sound/soc/codecs/wm2000.h +++ b/sound/soc/codecs/wm2000.h @@ -10,6 +10,9 @@ #define _WM2000_H #define WM2000_REG_SYS_START 0x8000 +#define WM2000_REG_ANC_GAIN_CTRL 0x8fa2 +#define WM2000_REG_MSE_TH2 0x8fdf +#define WM2000_REG_MSE_TH1 0x8fe0 #define WM2000_REG_SPEECH_CLARITY 0x8fef #define WM2000_REG_SYS_WATCHDOG 0x8ff6 #define WM2000_REG_ANA_VMID_PD_TIME 0x8ff7 diff --git a/sound/soc/codecs/wm2200.c b/sound/soc/codecs/wm2200.c index d8c65f574658..ddc98f02ecbd 100644 --- a/sound/soc/codecs/wm2200.c +++ b/sound/soc/codecs/wm2200.c @@ -1109,6 +1109,16 @@ static int wm2200_mixer_values[] = { static WM2200_MUX_CTL_DECL(name##_aux5); \ static WM2200_MUX_CTL_DECL(name##_aux6); +static const char *wm2200_rxanc_input_sel_texts[] = { + "None", "IN1", "IN2", "IN3", +}; + +static const struct soc_enum wm2200_rxanc_input_sel = + SOC_ENUM_SINGLE(WM2200_RXANC_SRC, + WM2200_IN_RXANC_SEL_SHIFT, + ARRAY_SIZE(wm2200_rxanc_input_sel_texts), + wm2200_rxanc_input_sel_texts); + static const struct snd_kcontrol_new wm2200_snd_controls[] = { SOC_SINGLE("IN1 High Performance Switch", WM2200_IN1L_CONTROL, WM2200_IN1_OSR_SHIFT, 1, 0), @@ -1126,9 +1136,9 @@ SOC_DOUBLE_R_TLV("IN3 Volume", WM2200_IN3L_CONTROL, WM2200_IN3R_CONTROL, SOC_DOUBLE_R("IN1 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L, WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("IN2 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L, +SOC_DOUBLE_R("IN2 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_2L, WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("IN3 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L, +SOC_DOUBLE_R("IN3 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_3L, WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_MUTE_SHIFT, 1, 1), SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_1L, @@ -1141,6 +1151,12 @@ SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_3L, WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SND_SOC_BYTES_MASK("EQL Coefficients", WM2200_EQL_1, 20, WM2200_EQL_ENA), +SND_SOC_BYTES_MASK("EQR Coefficients", WM2200_EQR_1, 20, WM2200_EQR_ENA), + +SND_SOC_BYTES("LHPF1 Coefficeints", WM2200_HPLPF1_2, 1), +SND_SOC_BYTES("LHPF2 Coefficeints", WM2200_HPLPF2_2, 1), + SOC_SINGLE("OUT1 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_1L, WM2200_OUT1_OSR_SHIFT, 1, 0), SOC_SINGLE("OUT2 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_2L, @@ -1162,6 +1178,7 @@ SOC_DOUBLE_R_TLV("OUT2 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_2L, digital_tlv), SOC_DOUBLE("OUT2 Switch", WM2200_PDM_1, WM2200_SPK1L_MUTE_SHIFT, WM2200_SPK1R_MUTE_SHIFT, 1, 1), +SOC_ENUM("RxANC Src", wm2200_rxanc_input_sel), }; WM2200_MIXER_ENUMS(OUT1L, WM2200_OUT1LMIX_INPUT_1_SOURCE); @@ -1548,6 +1565,10 @@ static int wm2200_probe(struct snd_soc_codec *codec) return ret; } + ret = snd_soc_add_codec_controls(codec, wm_adsp_fw_controls, 2); + if (ret != 0) + return ret; + return ret; } @@ -2182,6 +2203,7 @@ static int wm2200_i2c_probe(struct i2c_client *i2c, struct wm2200_priv *wm2200; unsigned int reg; int ret, i; + int val; wm2200 = devm_kzalloc(&i2c->dev, sizeof(struct wm2200_priv), GFP_KERNEL); @@ -2205,6 +2227,9 @@ static int wm2200_i2c_probe(struct i2c_client *i2c, wm2200->dsp[i].num = i + 1; wm2200->dsp[i].dev = &i2c->dev; wm2200->dsp[i].regmap = wm2200->regmap; + wm2200->dsp[i].sysclk_reg = WM2200_CLOCKING_3; + wm2200->dsp[i].sysclk_mask = WM2200_SYSCLK_FREQ_MASK; + wm2200->dsp[i].sysclk_shift = WM2200_SYSCLK_FREQ_SHIFT; } wm2200->dsp[0].base = WM2200_DSP1_CONTROL_1; @@ -2215,6 +2240,9 @@ static int wm2200_i2c_probe(struct i2c_client *i2c, wm2200->dsp[1].mem = wm2200_dsp2_regions; wm2200->dsp[1].num_mems = ARRAY_SIZE(wm2200_dsp2_regions); + for (i = 0; i < ARRAY_SIZE(wm2200->dsp); i++) + wm_adsp1_init(&wm2200->dsp[i]); + if (pdata) wm2200->pdata = *pdata; @@ -2326,6 +2354,36 @@ static int wm2200_i2c_probe(struct i2c_client *i2c, regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_16 + i, i); } + for (i = 0; i < WM2200_MAX_MICBIAS; i++) { + if (!wm2200->pdata.micbias[i].mb_lvl && + !wm2200->pdata.micbias[i].bypass) + continue; + + /* Apply default for bypass mode */ + if (!wm2200->pdata.micbias[i].mb_lvl) + wm2200->pdata.micbias[i].mb_lvl + = WM2200_MBIAS_LVL_1V5; + + val = (wm2200->pdata.micbias[i].mb_lvl -1) + << WM2200_MICB1_LVL_SHIFT; + + if (wm2200->pdata.micbias[i].discharge) + val |= WM2200_MICB1_DISCH; + + if (wm2200->pdata.micbias[i].fast_start) + val |= WM2200_MICB1_RATE; + + if (wm2200->pdata.micbias[i].bypass) + val |= WM2200_MICB1_MODE; + + regmap_update_bits(wm2200->regmap, + WM2200_MIC_BIAS_CTRL_1 + i, + WM2200_MICB1_LVL_MASK | + WM2200_MICB1_DISCH | + WM2200_MICB1_MODE | + WM2200_MICB1_RATE, val); + } + for (i = 0; i < ARRAY_SIZE(wm2200->pdata.in_mode); i++) { regmap_update_bits(wm2200->regmap, wm2200_mic_ctrl_reg[i], WM2200_IN1_MODE_MASK | diff --git a/sound/soc/codecs/wm5100.c b/sound/soc/codecs/wm5100.c index 54397a508073..ac1745d030d6 100644 --- a/sound/soc/codecs/wm5100.c +++ b/sound/soc/codecs/wm5100.c @@ -563,6 +563,19 @@ SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L, SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L, WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1), +SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA), +SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA), +SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA), +SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA), + +SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5, + WM5100_DRCL_ENA | WM5100_DRCR_ENA), + +SND_SOC_BYTES("LHPF1 Coefficeints", WM5100_HPLPF1_2, 1), +SND_SOC_BYTES("LHPF2 Coefficeints", WM5100_HPLPF2_2, 1), +SND_SOC_BYTES("LHPF3 Coefficeints", WM5100_HPLPF3_2, 1), +SND_SOC_BYTES("LHPF4 Coefficeints", WM5100_HPLPF4_2, 1), + SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L, WM5100_OUT1_OSR_SHIFT, 1, 0), SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L, diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c index 1440b3f9b7bb..5e85b645f2eb 100644 --- a/sound/soc/codecs/wm5102.c +++ b/sound/soc/codecs/wm5102.c @@ -45,6 +45,7 @@ static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); static DECLARE_TLV_DB_SCALE(noise_tlv, 0, 600, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); static const struct wm_adsp_region wm5102_dsp1_regions[] = { { .type = WMFW_ADSP2_PM, .base = 0x100000 }, @@ -603,6 +604,17 @@ static int wm5102_sysclk_ev(struct snd_soc_dapm_widget *w, return 0; } +#define WM5102_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ + SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) + static const struct snd_kcontrol_new wm5102_snd_controls[] = { SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT, 1, 0), @@ -611,32 +623,44 @@ SOC_SINGLE("IN2 High Performance Switch", ARIZONA_IN2L_CONTROL, SOC_SINGLE("IN3 High Performance Switch", ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT, 1, 0), -SOC_DOUBLE_R_RANGE_TLV("IN1 Volume", ARIZONA_IN1L_CONTROL, - ARIZONA_IN1R_CONTROL, - ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), -SOC_DOUBLE_R_RANGE_TLV("IN2 Volume", ARIZONA_IN2L_CONTROL, - ARIZONA_IN2R_CONTROL, - ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), -SOC_DOUBLE_R_RANGE_TLV("IN3 Volume", ARIZONA_IN3L_CONTROL, - ARIZONA_IN3R_CONTROL, - ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), - -SOC_DOUBLE_R("IN1 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L, - ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_IN1L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("IN2 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L, - ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("IN3 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3L, - ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_IN3L_MUTE_SHIFT, 1, 1), - -SOC_DOUBLE_R_TLV("IN1 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, - ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_IN1L_DIG_VOL_SHIFT, - 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("IN2 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, - ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2L_DIG_VOL_SHIFT, - 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("IN3 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, - ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_IN3L_DIG_VOL_SHIFT, - 0xbf, 0, digital_tlv), +SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL, + ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL, + ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), + +SOC_SINGLE("IN1L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN1R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN2L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN2R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN3L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3L, + ARIZONA_IN3L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN3R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3R, + ARIZONA_IN3R_MUTE_SHIFT, 1, 1), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, + ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R, + ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), @@ -774,6 +798,22 @@ SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +WM5102_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +WM5102_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), +WM5102_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L), +WM5102_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R), +WM5102_NG_SRC("EPOUT", ARIZONA_NOISE_GATE_SELECT_3L), +WM5102_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L), +WM5102_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R), +WM5102_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L), +WM5102_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R), + ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), @@ -880,6 +920,18 @@ ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE); ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE); ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); + ARIZONA_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE); @@ -1002,6 +1054,26 @@ SND_SOC_DAPM_PGA("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0, SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), + SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, @@ -1138,6 +1210,18 @@ ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"), ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"), ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"), +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), + +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), + WM_ADSP2("DSP1", 0), SND_SOC_DAPM_OUTPUT("HPOUT1L"), @@ -1193,6 +1277,14 @@ SND_SOC_DAPM_OUTPUT("SPKDAT1R"), { name, "ASRC1R", "ASRC1R" }, \ { name, "ASRC2L", "ASRC2L" }, \ { name, "ASRC2R", "ASRC2R" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ { name, "DSP1.1", "DSP1" }, \ { name, "DSP1.2", "DSP1" }, \ { name, "DSP1.3", "DSP1" }, \ @@ -1289,6 +1381,18 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { { "ASRC2L", NULL, "ASRC2L Input" }, { "ASRC2R", NULL, "ASRC2R Input" }, + { "ISRC1DEC1", NULL, "ISRC1DEC1 Input" }, + { "ISRC1DEC2", NULL, "ISRC1DEC2 Input" }, + + { "ISRC1INT1", NULL, "ISRC1INT1 Input" }, + { "ISRC1INT2", NULL, "ISRC1INT2 Input" }, + + { "ISRC2DEC1", NULL, "ISRC2DEC1 Input" }, + { "ISRC2DEC2", NULL, "ISRC2DEC2 Input" }, + + { "ISRC2INT1", NULL, "ISRC2INT1 Input" }, + { "ISRC2INT2", NULL, "ISRC2INT2 Input" }, + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), @@ -1336,6 +1440,18 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { ARIZONA_MUX_ROUTES("ASRC2L"), ARIZONA_MUX_ROUTES("ASRC2R"), + ARIZONA_MUX_ROUTES("ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2"), + + ARIZONA_MUX_ROUTES("ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2"), + + ARIZONA_MUX_ROUTES("ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2"), + ARIZONA_DSP_ROUTES("DSP1"), { "AEC Loopback", "HPOUT1L", "OUT1L" }, @@ -1463,6 +1579,10 @@ static int wm5102_codec_probe(struct snd_soc_codec *codec) if (ret != 0) return ret; + ret = snd_soc_add_codec_controls(codec, wm_adsp_fw_controls, 1); + if (ret != 0) + return ret; + snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); priv->core.arizona->dapm = &codec->dapm; diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c index 7a090968c4f7..23199372d518 100644 --- a/sound/soc/codecs/wm5110.c +++ b/sound/soc/codecs/wm5110.c @@ -41,6 +41,21 @@ static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); static DECLARE_TLV_DB_SCALE(noise_tlv, 0, 600, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); + +#define WM5110_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ + SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ + SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0) static const struct snd_kcontrol_new wm5110_snd_controls[] = { SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL, @@ -52,37 +67,52 @@ SOC_SINGLE("IN3 High Performance Switch", ARIZONA_IN3L_CONTROL, SOC_SINGLE("IN4 High Performance Switch", ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT, 1, 0), -SOC_DOUBLE_R_RANGE_TLV("IN1 Volume", ARIZONA_IN1L_CONTROL, - ARIZONA_IN1R_CONTROL, - ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), -SOC_DOUBLE_R_RANGE_TLV("IN2 Volume", ARIZONA_IN2L_CONTROL, - ARIZONA_IN2R_CONTROL, - ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), -SOC_DOUBLE_R_RANGE_TLV("IN3 Volume", ARIZONA_IN3L_CONTROL, - ARIZONA_IN3R_CONTROL, - ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), - -SOC_DOUBLE_R("IN1 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L, - ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_IN1L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("IN2 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L, - ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("IN3 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3L, - ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_IN3L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("IN4 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_4L, - ARIZONA_ADC_DIGITAL_VOLUME_4R, ARIZONA_IN4L_MUTE_SHIFT, 1, 1), - -SOC_DOUBLE_R_TLV("IN1 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, - ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_IN1L_DIG_VOL_SHIFT, - 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("IN2 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, - ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2L_DIG_VOL_SHIFT, - 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("IN3 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, - ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_IN3L_DIG_VOL_SHIFT, - 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("IN4 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L, - ARIZONA_ADC_DIGITAL_VOLUME_4R, ARIZONA_IN4L_DIG_VOL_SHIFT, - 0xbf, 0, digital_tlv), +SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL, + ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL, + ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), + +SOC_SINGLE("IN1L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN1R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN2L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN2R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN3L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3L, + ARIZONA_IN3L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN3R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3R, + ARIZONA_IN3R_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN4L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_4L, + ARIZONA_IN4L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("IN4R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_4R, + ARIZONA_IN4R_MUTE_SHIFT, 1, 1), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, + ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R, + ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN4L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L, + ARIZONA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN4R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4R, + ARIZONA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), @@ -263,6 +293,25 @@ SOC_DOUBLE("SPKDAT2 Switch", ARIZONA_PDM_SPK2_CTRL_1, ARIZONA_SPK2L_MUTE_SHIFT, SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +WM5110_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +WM5110_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), +WM5110_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L), +WM5110_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R), +WM5110_NG_SRC("HPOUT3L", ARIZONA_NOISE_GATE_SELECT_3L), +WM5110_NG_SRC("HPOUT3R", ARIZONA_NOISE_GATE_SELECT_3R), +WM5110_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L), +WM5110_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R), +WM5110_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L), +WM5110_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R), +WM5110_NG_SRC("SPKDAT2L", ARIZONA_NOISE_GATE_SELECT_6L), +WM5110_NG_SRC("SPKDAT2R", ARIZONA_NOISE_GATE_SELECT_6R), + ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index fb92fb47d636..ec0efc1443ba 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -283,18 +283,16 @@ static int pga_event(struct snd_soc_dapm_widget *w, out->ramp = WM8350_RAMP_UP; out->active = 1; - if (!delayed_work_pending(&codec->dapm.delayed_work)) - schedule_delayed_work(&codec->dapm.delayed_work, - msecs_to_jiffies(1)); + schedule_delayed_work(&codec->dapm.delayed_work, + msecs_to_jiffies(1)); break; case SND_SOC_DAPM_PRE_PMD: out->ramp = WM8350_RAMP_DOWN; out->active = 0; - if (!delayed_work_pending(&codec->dapm.delayed_work)) - schedule_delayed_work(&codec->dapm.delayed_work, - msecs_to_jiffies(1)); + schedule_delayed_work(&codec->dapm.delayed_work, + msecs_to_jiffies(1)); break; } diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c index d321a875b029..1704b1e119cb 100644 --- a/sound/soc/codecs/wm8804.c +++ b/sound/soc/codecs/wm8804.c @@ -395,9 +395,6 @@ static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id, /* power down the PLL before reprogramming it */ snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1); - if (!freq_in || !freq_out) - return 0; - /* set PLLN and PRESCALE */ snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10, pll_div.n | (pll_div.prescale << 4)); diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index bd4b0db4cdaa..e9710280e5e1 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -2873,22 +2873,20 @@ static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source, ret = 0; - if (fll1 & WM8962_FLL_ENA) { - /* This should be a massive overestimate but go even - * higher if we'll error out - */ - if (wm8962->irq) - timeout = msecs_to_jiffies(5); - else - timeout = msecs_to_jiffies(1); + /* This should be a massive overestimate but go even + * higher if we'll error out + */ + if (wm8962->irq) + timeout = msecs_to_jiffies(5); + else + timeout = msecs_to_jiffies(1); - timeout = wait_for_completion_timeout(&wm8962->fll_lock, - timeout); + timeout = wait_for_completion_timeout(&wm8962->fll_lock, + timeout); - if (timeout == 0 && wm8962->irq) { - dev_err(codec->dev, "FLL lock timed out"); - ret = -ETIMEDOUT; - } + if (timeout == 0 && wm8962->irq) { + dev_err(codec->dev, "FLL lock timed out"); + ret = -ETIMEDOUT; } wm8962->fll_fref = Fref; @@ -3189,7 +3187,7 @@ static void wm8962_init_beep(struct snd_soc_codec *codec) struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); int ret; - wm8962->beep = input_allocate_device(); + wm8962->beep = devm_input_allocate_device(codec->dev); if (!wm8962->beep) { dev_err(codec->dev, "Failed to allocate beep device\n"); return; @@ -3210,7 +3208,6 @@ static void wm8962_init_beep(struct snd_soc_codec *codec) ret = input_register_device(wm8962->beep); if (ret != 0) { - input_free_device(wm8962->beep); wm8962->beep = NULL; dev_err(codec->dev, "Failed to register beep device\n"); } @@ -3227,7 +3224,6 @@ static void wm8962_free_beep(struct snd_soc_codec *codec) struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); device_remove_file(codec->dev, &dev_attr_beep); - input_unregister_device(wm8962->beep); cancel_work_sync(&wm8962->beep_work); wm8962->beep = NULL; @@ -3758,10 +3754,17 @@ static const struct i2c_device_id wm8962_i2c_id[] = { }; MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); +static const struct of_device_id wm8962_of_match[] = { + { .compatible = "wlf,wm8962", }, + { } +}; +MODULE_DEVICE_TABLE(of, wm8962_of_match); + static struct i2c_driver wm8962_i2c_driver = { .driver = { .name = "wm8962", .owner = THIS_MODULE, + .of_match_table = wm8962_of_match, .pm = &wm8962_pm, }, .probe = wm8962_i2c_probe, diff --git a/sound/soc/codecs/wm8983.c b/sound/soc/codecs/wm8983.c index 9fe1e041da49..c9c707b8698f 100644 --- a/sound/soc/codecs/wm8983.c +++ b/sound/soc/codecs/wm8983.c @@ -851,30 +851,33 @@ static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id, struct pll_div pll_div; codec = dai->codec; - if (freq_in && freq_out) { + if (!freq_in || !freq_out) { + /* disable the PLL */ + snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, + WM8983_PLLEN_MASK, 0); + return 0; + } else { ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); if (ret) return ret; - } - - /* disable the PLL before re-programming it */ - snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, - WM8983_PLLEN_MASK, 0); - if (!freq_in || !freq_out) - return 0; + /* disable the PLL before re-programming it */ + snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, + WM8983_PLLEN_MASK, 0); + + /* set PLLN and PRESCALE */ + snd_soc_write(codec, WM8983_PLL_N, + (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT) + | pll_div.n); + /* set PLLK */ + snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff); + snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff); + snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18)); + /* enable the PLL */ + snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, + WM8983_PLLEN_MASK, WM8983_PLLEN); + } - /* set PLLN and PRESCALE */ - snd_soc_write(codec, WM8983_PLL_N, - (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT) - | pll_div.n); - /* set PLLK */ - snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff); - snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff); - snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18)); - /* enable the PLL */ - snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1, - WM8983_PLLEN_MASK, WM8983_PLLEN); return 0; } diff --git a/sound/soc/codecs/wm8985.c b/sound/soc/codecs/wm8985.c index ab3782657ac8..dd6ce3bc01cf 100644 --- a/sound/soc/codecs/wm8985.c +++ b/sound/soc/codecs/wm8985.c @@ -830,33 +830,30 @@ static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id, struct pll_div pll_div; codec = dai->codec; - if (freq_in && freq_out) { + if (!freq_in || !freq_out) { + /* disable the PLL */ + snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, + WM8985_PLLEN_MASK, 0); + } else { ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); if (ret) return ret; - } - /* disable the PLL before reprogramming it */ - snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, - WM8985_PLLEN_MASK, 0); - - if (!freq_in || !freq_out) - return 0; - - /* set PLLN and PRESCALE */ - snd_soc_write(codec, WM8985_PLL_N, - (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT) - | pll_div.n); - /* set PLLK */ - snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff); - snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff); - snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18)); - /* set the source of the clock to be the PLL */ - snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL, - WM8985_CLKSEL_MASK, WM8985_CLKSEL); - /* enable the PLL */ - snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, - WM8985_PLLEN_MASK, WM8985_PLLEN); + /* set PLLN and PRESCALE */ + snd_soc_write(codec, WM8985_PLL_N, + (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT) + | pll_div.n); + /* set PLLK */ + snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff); + snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff); + snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18)); + /* set the source of the clock to be the PLL */ + snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL, + WM8985_CLKSEL_MASK, WM8985_CLKSEL); + /* enable the PLL */ + snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, + WM8985_PLLEN_MASK, WM8985_PLLEN); + } return 0; } diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index b6b654837585..f3f7e75f8628 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c @@ -15,6 +15,7 @@ #include <linux/init.h> #include <linux/delay.h> #include <linux/firmware.h> +#include <linux/list.h> #include <linux/pm.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> @@ -103,9 +104,19 @@ #define ADSP1_START_SHIFT 0 /* DSP1_START */ #define ADSP1_START_WIDTH 1 /* DSP1_START */ -#define ADSP2_CONTROL 0 -#define ADSP2_CLOCKING 1 -#define ADSP2_STATUS1 4 +/* + * ADSP1 Control 31 + */ +#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ +#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ +#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +#define ADSP2_CONTROL 0x0 +#define ADSP2_CLOCKING 0x1 +#define ADSP2_STATUS1 0x4 +#define ADSP2_WDMA_CONFIG_1 0x30 +#define ADSP2_WDMA_CONFIG_2 0x31 +#define ADSP2_RDMA_CONFIG_1 0x34 /* * ADSP2 Control @@ -143,6 +154,109 @@ #define ADSP2_RAM_RDY_SHIFT 0 #define ADSP2_RAM_RDY_WIDTH 1 +struct wm_adsp_buf { + struct list_head list; + void *buf; +}; + +static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len, + struct list_head *list) +{ + struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL); + + if (buf == NULL) + return NULL; + + buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA); + if (!buf->buf) { + kfree(buf); + return NULL; + } + + if (list) + list_add_tail(&buf->list, list); + + return buf; +} + +static void wm_adsp_buf_free(struct list_head *list) +{ + while (!list_empty(list)) { + struct wm_adsp_buf *buf = list_first_entry(list, + struct wm_adsp_buf, + list); + list_del(&buf->list); + kfree(buf->buf); + kfree(buf); + } +} + +#define WM_ADSP_NUM_FW 4 + +static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = { + "MBC/VSS", "Tx", "Tx Speaker", "Rx ANC" +}; + +static struct { + const char *file; +} wm_adsp_fw[WM_ADSP_NUM_FW] = { + { .file = "mbc-vss" }, + { .file = "tx" }, + { .file = "tx-spk" }, + { .file = "rx-anc" }, +}; + +static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = adsp[e->shift_l].fw; + + return 0; +} + +static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec); + + if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw) + return 0; + + if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW) + return -EINVAL; + + if (adsp[e->shift_l].running) + return -EBUSY; + + adsp[e->shift_l].fw = ucontrol->value.integer.value[0]; + + return 0; +} + +static const struct soc_enum wm_adsp_fw_enum[] = { + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), +}; + +const struct snd_kcontrol_new wm_adsp_fw_controls[] = { + SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0], + wm_adsp_fw_get, wm_adsp_fw_put), + SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1], + wm_adsp_fw_get, wm_adsp_fw_put), + SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2], + wm_adsp_fw_get, wm_adsp_fw_put), + SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3], + wm_adsp_fw_get, wm_adsp_fw_put), +}; +EXPORT_SYMBOL_GPL(wm_adsp_fw_controls); static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, int type) @@ -156,8 +270,29 @@ static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, return NULL; } +static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region, + unsigned int offset) +{ + switch (region->type) { + case WMFW_ADSP1_PM: + return region->base + (offset * 3); + case WMFW_ADSP1_DM: + return region->base + (offset * 2); + case WMFW_ADSP2_XM: + return region->base + (offset * 2); + case WMFW_ADSP2_YM: + return region->base + (offset * 2); + case WMFW_ADSP1_ZM: + return region->base + (offset * 2); + default: + WARN_ON(NULL != "Unknown memory region type"); + return offset; + } +} + static int wm_adsp_load(struct wm_adsp *dsp) { + LIST_HEAD(buf_list); const struct firmware *firmware; struct regmap *regmap = dsp->regmap; unsigned int pos = 0; @@ -169,7 +304,7 @@ static int wm_adsp_load(struct wm_adsp *dsp) const struct wm_adsp_region *mem; const char *region_name; char *file, *text; - void *buf; + struct wm_adsp_buf *buf; unsigned int reg; int regions = 0; int ret, offset, type, sizes; @@ -178,7 +313,8 @@ static int wm_adsp_load(struct wm_adsp *dsp) if (file == NULL) return -ENOMEM; - snprintf(file, PAGE_SIZE, "%s-dsp%d.wmfw", dsp->part, dsp->num); + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num, + wm_adsp_fw[dsp->fw].file); file[PAGE_SIZE - 1] = '\0'; ret = request_firmware(&firmware, file, dsp->dev); @@ -283,27 +419,27 @@ static int wm_adsp_load(struct wm_adsp *dsp) case WMFW_ADSP1_PM: BUG_ON(!mem); region_name = "PM"; - reg = mem->base + (offset * 3); + reg = wm_adsp_region_to_reg(mem, offset); break; case WMFW_ADSP1_DM: BUG_ON(!mem); region_name = "DM"; - reg = mem->base + (offset * 2); + reg = wm_adsp_region_to_reg(mem, offset); break; case WMFW_ADSP2_XM: BUG_ON(!mem); region_name = "XM"; - reg = mem->base + (offset * 2); + reg = wm_adsp_region_to_reg(mem, offset); break; case WMFW_ADSP2_YM: BUG_ON(!mem); region_name = "YM"; - reg = mem->base + (offset * 2); + reg = wm_adsp_region_to_reg(mem, offset); break; case WMFW_ADSP1_ZM: BUG_ON(!mem); region_name = "ZM"; - reg = mem->base + (offset * 2); + reg = wm_adsp_region_to_reg(mem, offset); break; default: adsp_warn(dsp, @@ -323,18 +459,16 @@ static int wm_adsp_load(struct wm_adsp *dsp) } if (reg) { - buf = kmemdup(region->data, le32_to_cpu(region->len), - GFP_KERNEL | GFP_DMA); + buf = wm_adsp_buf_alloc(region->data, + le32_to_cpu(region->len), + &buf_list); if (!buf) { adsp_err(dsp, "Out of memory\n"); return -ENOMEM; } - ret = regmap_raw_write(regmap, reg, buf, - le32_to_cpu(region->len)); - - kfree(buf); - + ret = regmap_raw_write_async(regmap, reg, buf->buf, + le32_to_cpu(region->len)); if (ret != 0) { adsp_err(dsp, "%s.%d: Failed to write %d bytes at %d in %s: %d\n", @@ -348,12 +482,20 @@ static int wm_adsp_load(struct wm_adsp *dsp) pos += le32_to_cpu(region->len) + sizeof(*region); regions++; } - + + ret = regmap_async_complete(regmap); + if (ret != 0) { + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + goto out_fw; + } + if (pos > firmware->size) adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", file, regions, pos - firmware->size); out_fw: + regmap_async_complete(regmap); + wm_adsp_buf_free(&buf_list); release_firmware(firmware); out: kfree(file); @@ -361,22 +503,222 @@ out: return ret; } +static int wm_adsp_setup_algs(struct wm_adsp *dsp) +{ + struct regmap *regmap = dsp->regmap; + struct wmfw_adsp1_id_hdr adsp1_id; + struct wmfw_adsp2_id_hdr adsp2_id; + struct wmfw_adsp1_alg_hdr *adsp1_alg; + struct wmfw_adsp2_alg_hdr *adsp2_alg; + void *alg, *buf; + struct wm_adsp_alg_region *region; + const struct wm_adsp_region *mem; + unsigned int pos, term; + size_t algs, buf_size; + __be32 val; + int i, ret; + + switch (dsp->type) { + case WMFW_ADSP1: + mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); + break; + case WMFW_ADSP2: + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + break; + default: + mem = NULL; + break; + } + + if (mem == NULL) { + BUG_ON(mem != NULL); + return -EINVAL; + } + + switch (dsp->type) { + case WMFW_ADSP1: + ret = regmap_raw_read(regmap, mem->base, &adsp1_id, + sizeof(adsp1_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", + ret); + return ret; + } + + buf = &adsp1_id; + buf_size = sizeof(adsp1_id); + + algs = be32_to_cpu(adsp1_id.algs); + adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", + be32_to_cpu(adsp1_id.fw.id), + (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8, + be32_to_cpu(adsp1_id.fw.ver) & 0xff, + algs); + + pos = sizeof(adsp1_id) / 2; + term = pos + ((sizeof(*adsp1_alg) * algs) / 2); + break; + + case WMFW_ADSP2: + ret = regmap_raw_read(regmap, mem->base, &adsp2_id, + sizeof(adsp2_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", + ret); + return ret; + } + + buf = &adsp2_id; + buf_size = sizeof(adsp2_id); + + algs = be32_to_cpu(adsp2_id.algs); + adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", + be32_to_cpu(adsp2_id.fw.id), + (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8, + be32_to_cpu(adsp2_id.fw.ver) & 0xff, + algs); + + pos = sizeof(adsp2_id) / 2; + term = pos + ((sizeof(*adsp2_alg) * algs) / 2); + break; + + default: + BUG_ON(NULL == "Unknown DSP type"); + return -EINVAL; + } + + if (algs == 0) { + adsp_err(dsp, "No algorithms\n"); + return -EINVAL; + } + + if (algs > 1024) { + adsp_err(dsp, "Algorithm count %zx excessive\n", algs); + print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET, + buf, buf_size); + return -EINVAL; + } + + /* Read the terminator first to validate the length */ + ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list end: %d\n", + ret); + return ret; + } + + if (be32_to_cpu(val) != 0xbedead) + adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n", + term, be32_to_cpu(val)); + + alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA); + if (!alg) + return -ENOMEM; + + ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list: %d\n", + ret); + goto out; + } + + adsp1_alg = alg; + adsp2_alg = alg; + + for (i = 0; i < algs; i++) { + switch (dsp->type) { + case WMFW_ADSP1: + adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", + i, be32_to_cpu(adsp1_alg[i].alg.id), + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp1_alg[i].dm), + be32_to_cpu(adsp1_alg[i].zm)); + + region = kzalloc(sizeof(*region), GFP_KERNEL); + if (!region) + return -ENOMEM; + region->type = WMFW_ADSP1_DM; + region->alg = be32_to_cpu(adsp1_alg[i].alg.id); + region->base = be32_to_cpu(adsp1_alg[i].dm); + list_add_tail(®ion->list, &dsp->alg_regions); + + region = kzalloc(sizeof(*region), GFP_KERNEL); + if (!region) + return -ENOMEM; + region->type = WMFW_ADSP1_ZM; + region->alg = be32_to_cpu(adsp1_alg[i].alg.id); + region->base = be32_to_cpu(adsp1_alg[i].zm); + list_add_tail(®ion->list, &dsp->alg_regions); + break; + + case WMFW_ADSP2: + adsp_info(dsp, + "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", + i, be32_to_cpu(adsp2_alg[i].alg.id), + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp2_alg[i].xm), + be32_to_cpu(adsp2_alg[i].ym), + be32_to_cpu(adsp2_alg[i].zm)); + + region = kzalloc(sizeof(*region), GFP_KERNEL); + if (!region) + return -ENOMEM; + region->type = WMFW_ADSP2_XM; + region->alg = be32_to_cpu(adsp2_alg[i].alg.id); + region->base = be32_to_cpu(adsp2_alg[i].xm); + list_add_tail(®ion->list, &dsp->alg_regions); + + region = kzalloc(sizeof(*region), GFP_KERNEL); + if (!region) + return -ENOMEM; + region->type = WMFW_ADSP2_YM; + region->alg = be32_to_cpu(adsp2_alg[i].alg.id); + region->base = be32_to_cpu(adsp2_alg[i].ym); + list_add_tail(®ion->list, &dsp->alg_regions); + + region = kzalloc(sizeof(*region), GFP_KERNEL); + if (!region) + return -ENOMEM; + region->type = WMFW_ADSP2_ZM; + region->alg = be32_to_cpu(adsp2_alg[i].alg.id); + region->base = be32_to_cpu(adsp2_alg[i].zm); + list_add_tail(®ion->list, &dsp->alg_regions); + break; + } + } + +out: + kfree(alg); + return ret; +} + static int wm_adsp_load_coeff(struct wm_adsp *dsp) { + LIST_HEAD(buf_list); struct regmap *regmap = dsp->regmap; struct wmfw_coeff_hdr *hdr; struct wmfw_coeff_item *blk; const struct firmware *firmware; + const struct wm_adsp_region *mem; + struct wm_adsp_alg_region *alg_region; const char *region_name; int ret, pos, blocks, type, offset, reg; char *file; - void *buf; + struct wm_adsp_buf *buf; + int tmp; file = kzalloc(PAGE_SIZE, GFP_KERNEL); if (file == NULL) return -ENOMEM; - snprintf(file, PAGE_SIZE, "%s-dsp%d.bin", dsp->part, dsp->num); + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num, + wm_adsp_fw[dsp->fw].file); file[PAGE_SIZE - 1] = '\0'; ret = request_firmware(&firmware, file, dsp->dev); @@ -399,6 +741,16 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) goto out_fw; } + switch (be32_to_cpu(hdr->rev) & 0xff) { + case 1: + break; + default: + adsp_err(dsp, "%s: Unsupported coefficient file format %d\n", + file, be32_to_cpu(hdr->rev) & 0xff); + ret = -EINVAL; + goto out_fw; + } + adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, (le32_to_cpu(hdr->ver) >> 16) & 0xff, (le32_to_cpu(hdr->ver) >> 8) & 0xff, @@ -411,8 +763,8 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) pos - firmware->size > sizeof(*blk)) { blk = (void*)(&firmware->data[pos]); - type = be32_to_cpu(blk->type) & 0xff; - offset = le32_to_cpu(blk->offset) & 0xffffff; + type = le16_to_cpu(blk->type); + offset = le16_to_cpu(blk->offset); adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", file, blocks, le32_to_cpu(blk->id), @@ -425,52 +777,105 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) reg = 0; region_name = "Unknown"; switch (type) { - case WMFW_NAME_TEXT: - case WMFW_INFO_TEXT: + case (WMFW_NAME_TEXT << 8): + case (WMFW_INFO_TEXT << 8): break; - case WMFW_ABSOLUTE: + case (WMFW_ABSOLUTE << 8): region_name = "register"; reg = offset; break; + + case WMFW_ADSP1_DM: + case WMFW_ADSP1_ZM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", + file, blocks, le32_to_cpu(blk->len), + type, le32_to_cpu(blk->id)); + + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", type); + break; + } + + reg = 0; + list_for_each_entry(alg_region, + &dsp->alg_regions, list) { + if (le32_to_cpu(blk->id) == alg_region->alg && + type == alg_region->type) { + reg = alg_region->base; + reg = wm_adsp_region_to_reg(mem, + reg); + reg += offset; + } + } + + if (reg == 0) + adsp_err(dsp, "No %x for algorithm %x\n", + type, le32_to_cpu(blk->id)); + break; + default: - adsp_err(dsp, "Unknown region type %x\n", type); + adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", + file, blocks, type, pos); break; } if (reg) { - buf = kmemdup(blk->data, le32_to_cpu(blk->len), - GFP_KERNEL | GFP_DMA); + buf = wm_adsp_buf_alloc(blk->data, + le32_to_cpu(blk->len), + &buf_list); if (!buf) { adsp_err(dsp, "Out of memory\n"); return -ENOMEM; } - ret = regmap_raw_write(regmap, reg, blk->data, - le32_to_cpu(blk->len)); + adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", + file, blocks, le32_to_cpu(blk->len), + reg); + ret = regmap_raw_write_async(regmap, reg, buf->buf, + le32_to_cpu(blk->len)); if (ret != 0) { adsp_err(dsp, "%s.%d: Failed to write to %x in %s\n", file, blocks, reg, region_name); } - - kfree(buf); } - pos += le32_to_cpu(blk->len) + sizeof(*blk); + tmp = le32_to_cpu(blk->len) % 4; + if (tmp) + pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk); + else + pos += le32_to_cpu(blk->len) + sizeof(*blk); + blocks++; } + ret = regmap_async_complete(regmap); + if (ret != 0) + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + if (pos > firmware->size) adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", file, blocks, pos - firmware->size); out_fw: release_firmware(firmware); + wm_adsp_buf_free(&buf_list); out: kfree(file); return 0; } +int wm_adsp1_init(struct wm_adsp *adsp) +{ + INIT_LIST_HEAD(&adsp->alg_regions); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp1_init); + int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) @@ -479,16 +884,46 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); struct wm_adsp *dsp = &dsps[w->shift]; int ret; + int val; switch (event) { case SND_SOC_DAPM_POST_PMU: regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, ADSP1_SYS_ENA, ADSP1_SYS_ENA); + /* + * For simplicity set the DSP clock rate to be the + * SYSCLK rate rather than making it configurable. + */ + if(dsp->sysclk_reg) { + ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); + if (ret != 0) { + adsp_err(dsp, "Failed to read SYSCLK state: %d\n", + ret); + return ret; + } + + val = (val & dsp->sysclk_mask) + >> dsp->sysclk_shift; + + ret = regmap_update_bits(dsp->regmap, + dsp->base + ADSP1_CONTROL_31, + ADSP1_CLK_SEL_MASK, val); + if (ret != 0) { + adsp_err(dsp, "Failed to set clock rate: %d\n", + ret); + return ret; + } + } + ret = wm_adsp_load(dsp); if (ret != 0) goto err; + ret = wm_adsp_setup_algs(dsp); + if (ret != 0) + goto err; + ret = wm_adsp_load_coeff(dsp); if (ret != 0) goto err; @@ -560,6 +995,7 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, struct snd_soc_codec *codec = w->codec; struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_adsp_alg_region *alg_region; unsigned int val; int ret; @@ -625,6 +1061,10 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, if (ret != 0) goto err; + ret = wm_adsp_setup_algs(dsp); + if (ret != 0) + goto err; + ret = wm_adsp_load_coeff(dsp); if (ret != 0) goto err; @@ -635,13 +1075,22 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, ADSP2_CORE_ENA | ADSP2_START); if (ret != 0) goto err; + + dsp->running = true; break; case SND_SOC_DAPM_PRE_PMD: + dsp->running = false; + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); + /* Make sure DMAs are quiesced */ + regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); + if (dsp->dvfs) { ret = regulator_set_voltage(dsp->dvfs, 1200000, 1800000); @@ -656,6 +1105,14 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w, "Failed to enable supply: %d\n", ret); } + + while (!list_empty(&dsp->alg_regions)) { + alg_region = list_first_entry(&dsp->alg_regions, + struct wm_adsp_alg_region, + list); + list_del(&alg_region->list); + kfree(alg_region); + } break; default: @@ -685,6 +1142,8 @@ int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs) return ret; } + INIT_LIST_HEAD(&adsp->alg_regions); + if (dvfs) { adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD"); if (IS_ERR(adsp->dvfs)) { diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h index ffd29a4609e2..cb8871a3ec00 100644 --- a/sound/soc/codecs/wm_adsp.h +++ b/sound/soc/codecs/wm_adsp.h @@ -25,6 +25,13 @@ struct wm_adsp_region { unsigned int base; }; +struct wm_adsp_alg_region { + struct list_head list; + unsigned int alg; + int type; + unsigned int base; +}; + struct wm_adsp { const char *part; int num; @@ -33,10 +40,18 @@ struct wm_adsp { struct regmap *regmap; int base; + int sysclk_reg; + int sysclk_mask; + int sysclk_shift; + + struct list_head alg_regions; const struct wm_adsp_region *mem; int num_mems; + int fw; + bool running; + struct regulator *dvfs; }; @@ -50,6 +65,9 @@ struct wm_adsp { .shift = num, .event = wm_adsp2_event, \ .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD } +extern const struct snd_kcontrol_new wm_adsp_fw_controls[]; + +int wm_adsp1_init(struct wm_adsp *adsp); int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs); int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); diff --git a/sound/soc/codecs/wmfw.h b/sound/soc/codecs/wmfw.h index 5632ded67fdd..ef163360a745 100644 --- a/sound/soc/codecs/wmfw.h +++ b/sound/soc/codecs/wmfw.h @@ -93,15 +93,20 @@ struct wmfw_adsp2_alg_hdr { struct wmfw_coeff_hdr { u8 magic[4]; __le32 len; - __le32 ver; + union { + __be32 rev; + __le32 ver; + }; + union { + __be32 core; + __le32 core_ver; + }; u8 data[]; } __packed; struct wmfw_coeff_item { - union { - __be32 type; - __le32 offset; - }; + __le16 offset; + __le16 type; __le32 id; __le32 ver; __le32 sr; |