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Diffstat (limited to 'arch/sh/boards/renesas/r7780rp/io.c')
-rw-r--r--arch/sh/boards/renesas/r7780rp/io.c103
1 files changed, 33 insertions, 70 deletions
diff --git a/arch/sh/boards/renesas/r7780rp/io.c b/arch/sh/boards/renesas/r7780rp/io.c
index f73ca3f0f5a1..db92d6e6ae99 100644
--- a/arch/sh/boards/renesas/r7780rp/io.c
+++ b/arch/sh/boards/renesas/r7780rp/io.c
@@ -1,6 +1,4 @@
/*
- * linux/arch/sh/kernel/io_r7780rp.c
- *
* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
* Based largely on io_se.c.
*
@@ -10,37 +8,13 @@
* placeholder code from io_r7780rp.c left in with the
* expectation of later SuperIO and PCMCIA access.
*/
-
+#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/r7780rp/r7780rp.h>
#include <asm/addrspace.h>
#include <asm/io.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include "../../../drivers/pci/pci-sh7780.h"
-
-/*
- * The 7780 R7780RP-1 uses the built-in PCI controller (PCIC)
- * of the 7780 processor, and has a SuperIO accessible via the PCI.
- * The board also includes a PCMCIA controller on its memory bus,
- * like the other Solution Engine boards.
- */
-
-#define SH7780_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
-#define PCIIOBR (volatile long *)PCI_REG(SH7780_PCIIOBR)
-#define PCIMBR (volatile long *)PCI_REG(SH7780_PCIMBR)
-#define PCI_IO_AREA SH7780_PCI_IO_BASE
-#define PCI_MEM_AREA SH7780_PCI_CONFIG_BASE
-
-#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7780_PCIIOBR_MASK))
-
-static inline void delay(void)
-{
- ctrl_inw(0xa0000000);
-}
-
static inline unsigned long port2adr(unsigned int port)
{
if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
@@ -78,17 +52,6 @@ static inline int shifted_port(unsigned long port)
return 1;
}
-/* In case someone configures the kernel w/o PCI support: in that */
-/* scenario, don't ever bother to check for PCI-window addresses */
-
-/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */
-#if defined(CONFIG_PCI)
-#define CHECK_SH7780_PCIIO(port) \
- ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7780_PCI_IO_SIZE)))
-#else
-#define CHECK_SH7780_PCIIO(port) (0)
-#endif
-
#if defined(CONFIG_NE2000) || defined(CONFIG_NE2000_MODULE)
#define CHECK_AX88796L_PORT(port) \
((port >= AX88796L_IO_BASE) && (port < (AX88796L_IO_BASE+0x20)))
@@ -109,8 +72,8 @@ u8 r7780rp_inb(unsigned long port)
return ctrl_inw(port88796l(port, 0)) & 0xff;
else if (PXSEG(port))
return ctrl_inb(port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- return ctrl_inb(PCI_IOMAP(port));
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ return ctrl_inb(pci_ioaddr(port));
return ctrl_inw(port2adr(port)) & 0xff;
}
@@ -123,12 +86,12 @@ u8 r7780rp_inb_p(unsigned long port)
v = ctrl_inw(port88796l(port, 0)) & 0xff;
else if (PXSEG(port))
v = ctrl_inb(port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- v = ctrl_inb(PCI_IOMAP(port));
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ v = ctrl_inb(pci_ioaddr(port));
else
v = ctrl_inw(port2adr(port)) & 0xff;
- delay();
+ ctrl_delay();
return v;
}
@@ -139,8 +102,8 @@ u16 r7780rp_inw(unsigned long port)
maybebadio(port);
else if (PXSEG(port))
return ctrl_inw(port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- return ctrl_inw(PCI_IOMAP(port));
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ return ctrl_inw(pci_ioaddr(port));
else
maybebadio(port);
@@ -153,8 +116,8 @@ u32 r7780rp_inl(unsigned long port)
maybebadio(port);
else if (PXSEG(port))
return ctrl_inl(port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- return ctrl_inl(PCI_IOMAP(port));
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ return ctrl_inl(pci_ioaddr(port));
else
maybebadio(port);
@@ -167,8 +130,8 @@ void r7780rp_outb(u8 value, unsigned long port)
ctrl_outw(value, port88796l(port, 0));
else if (PXSEG(port))
ctrl_outb(value, port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- ctrl_outb(value, PCI_IOMAP(port));
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ ctrl_outb(value, pci_ioaddr(port));
else
ctrl_outw(value, port2adr(port));
}
@@ -179,12 +142,12 @@ void r7780rp_outb_p(u8 value, unsigned long port)
ctrl_outw(value, port88796l(port, 0));
else if (PXSEG(port))
ctrl_outb(value, port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- ctrl_outb(value, PCI_IOMAP(port));
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ ctrl_outb(value, pci_ioaddr(port));
else
ctrl_outw(value, port2adr(port));
- delay();
+ ctrl_delay();
}
void r7780rp_outw(u16 value, unsigned long port)
@@ -193,8 +156,8 @@ void r7780rp_outw(u16 value, unsigned long port)
maybebadio(port);
else if (PXSEG(port))
ctrl_outw(value, port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- ctrl_outw(value, PCI_IOMAP(port));
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ ctrl_outw(value, pci_ioaddr(port));
else
maybebadio(port);
}
@@ -205,8 +168,8 @@ void r7780rp_outl(u32 value, unsigned long port)
maybebadio(port);
else if (PXSEG(port))
ctrl_outl(value, port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- ctrl_outl(value, PCI_IOMAP(port));
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ ctrl_outl(value, pci_ioaddr(port));
else
maybebadio(port);
}
@@ -223,8 +186,8 @@ void r7780rp_insb(unsigned long port, void *dst, unsigned long count)
} else if (PXSEG(port)) {
while (count--)
*buf++ = *(volatile u8 *)port;
- } else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
- volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
+ } else if (is_pci_ioaddr(port) || shifted_port(port)) {
+ volatile u8 *bp = (volatile u8 *)pci_ioaddr(port);
while (count--)
*buf++ = *bp;
@@ -244,8 +207,8 @@ void r7780rp_insw(unsigned long port, void *dst, unsigned long count)
p = (volatile u16 *)port88796l(port, 1);
else if (PXSEG(port))
p = (volatile u16 *)port;
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- p = (volatile u16 *)PCI_IOMAP(port);
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ p = (volatile u16 *)pci_ioaddr(port);
else
p = (volatile u16 *)port2adr(port);
@@ -259,8 +222,8 @@ void r7780rp_insl(unsigned long port, void *dst, unsigned long count)
if (CHECK_AX88796L_PORT(port))
maybebadio(port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
- volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
+ else if (is_pci_ioaddr(port) || shifted_port(port)) {
+ volatile u32 *p = (volatile u32 *)pci_ioaddr(port);
while (count--)
*buf++ = *p;
@@ -280,8 +243,8 @@ void r7780rp_outsb(unsigned long port, const void *src, unsigned long count)
} else if (PXSEG(port))
while (count--)
ctrl_outb(*buf++, port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
- volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
+ else if (is_pci_ioaddr(port) || shifted_port(port)) {
+ volatile u8 *bp = (volatile u8 *)pci_ioaddr(port);
while (count--)
*bp = *buf++;
@@ -301,8 +264,8 @@ void r7780rp_outsw(unsigned long port, const void *src, unsigned long count)
p = (volatile u16 *)port88796l(port, 1);
else if (PXSEG(port))
p = (volatile u16 *)port;
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- p = (volatile u16 *)PCI_IOMAP(port);
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ p = (volatile u16 *)pci_ioaddr(port);
else
p = (volatile u16 *)port2adr(port);
@@ -316,8 +279,8 @@ void r7780rp_outsl(unsigned long port, const void *src, unsigned long count)
if (CHECK_AX88796L_PORT(port))
maybebadio(port);
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
- volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
+ else if (is_pci_ioaddr(port) || shifted_port(port)) {
+ volatile u32 *p = (volatile u32 *)pci_ioaddr(port);
while (count--)
*p = *buf++;
@@ -331,8 +294,8 @@ void __iomem *r7780rp_ioport_map(unsigned long port, unsigned int size)
return (void __iomem *)port88796l(port, size > 1);
else if (PXSEG(port))
return (void __iomem *)port;
- else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
- return (void __iomem *)PCI_IOMAP(port);
+ else if (is_pci_ioaddr(port) || shifted_port(port))
+ return (void __iomem *)pci_ioaddr(port);
return (void __iomem *)port2adr(port);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 01:38:31 +0000