diff options
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/class.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c | 57 |
7 files changed, 68 insertions, 5 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 67f1d9bd3403..0fdbcffaa54d 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -32,6 +32,7 @@ #define G82_CHANNEL_GPFIFO 0x0000826f #define FERMI_CHANNEL_GPFIFO 0x0000906f #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f +#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f #define NV50_DISP 0x00005070 #define G82_DISP 0x00008270 diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index 05321ce7ab15..97cdeab8e44c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -116,6 +116,7 @@ extern struct nvkm_oclass *gf100_fifo_oclass; extern struct nvkm_oclass *gk104_fifo_oclass; extern struct nvkm_oclass *gk20a_fifo_oclass; extern struct nvkm_oclass *gk208_fifo_oclass; +extern struct nvkm_oclass *gm204_fifo_oclass; int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32, struct nvkm_notify *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 108d048da764..7f4248271915 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -127,9 +127,9 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; -#if 0 - device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; + device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; +#if 0 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; #endif device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild index c5a2d8718c5b..42891cb71ea3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild @@ -9,3 +9,4 @@ nvkm-y += nvkm/engine/fifo/gf100.o nvkm-y += nvkm/engine/fifo/gk104.o nvkm-y += nvkm/engine/fifo/gk20a.o nvkm-y += nvkm/engine/fifo/gk208.o +nvkm-y += nvkm/engine/fifo/gm204.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 9585539e59f2..e10f9644140f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -323,8 +323,8 @@ gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) return nvkm_fifo_channel_fini(&chan->base, suspend); } -static struct nvkm_ofuncs -gk104_fifo_ofuncs = { +struct nvkm_ofuncs +gk104_fifo_chan_ofuncs = { .ctor = gk104_fifo_chan_ctor, .dtor = _nvkm_fifo_channel_dtor, .init = gk104_fifo_chan_init, @@ -337,7 +337,7 @@ gk104_fifo_ofuncs = { static struct nvkm_oclass gk104_fifo_sclass[] = { - { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_ofuncs }, + { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs }, {} }; @@ -774,6 +774,7 @@ gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit) while (object) { switch (nv_mclass(object)) { case KEPLER_CHANNEL_GPFIFO_A: + case MAXWELL_CHANNEL_GPFIFO_A: gk104_fifo_recover(priv, engine, (void *)object); break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index 3046e00ed6ba..318d30d6ee1a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -13,4 +13,6 @@ struct gk104_fifo_impl { struct nvkm_oclass base; u32 channels; }; + +extern struct nvkm_ofuncs gk104_fifo_chan_ofuncs; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c new file mode 100644 index 000000000000..749d525dd8e3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c @@ -0,0 +1,57 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "gk104.h" + +#include <nvif/class.h> + +static struct nvkm_oclass +gm204_fifo_sclass[] = { + { MAXWELL_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs }, + {} +}; + +static int +gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject); + if (ret == 0) { + struct gk104_fifo_priv *priv = (void *)*pobject; + nv_engine(priv)->sclass = gm204_fifo_sclass; + } + return ret; +} + +struct nvkm_oclass * +gm204_fifo_oclass = &(struct gk104_fifo_impl) { + .base.handle = NV_ENGINE(FIFO, 0x24), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gm204_fifo_ctor, + .dtor = gk104_fifo_dtor, + .init = gk104_fifo_init, + .fini = _nvkm_fifo_fini, + }, + .channels = 4096, +}.base; |