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authorMark Zhang <markz@nvidia.com>2013-12-26 16:44:24 -0800
committerPeter De Schrijver <pdeschrijver@nvidia.com>2014-02-17 16:18:16 +0200
commit82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874 (patch)
tree0c9a829ca83489a35631d43e3f124bfcd35eb7d5 /drivers/hv/channel_mgmt.c
parent0e766c2d9fc8cd2ad0e0fe97ff4e264cb686fc32 (diff)
clk: tegra: fix host1x clock on Tegra124
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents. Change thte id to tegra_clk_host1x_8 so that the correct clock gets registered. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Diffstat (limited to 'drivers/hv/channel_mgmt.c')
0 files changed, 0 insertions, 0 deletions