diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-04-14 18:44:38 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-04-14 18:44:38 -0700 |
| commit | 2bb590b80b2f057d9277adc86a0858843d15fca6 (patch) | |
| tree | 5938e2c0bc92c575a458f3118cf3a6b6e65d3d6c /arch/mips/mm/c-r4k.c | |
| parent | c0e03084000a54d75d1440cce5b71aa9db5a5836 (diff) | |
| parent | 41ef2d5678d83af030125550329b6ae8b74618fa (diff) | |
Merge 3.9-rc7 into staging-next
We want these fixes here.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index ecca559b8d7b..2078915eacb9 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void) return; default: - if (c->isa_level == MIPS_CPU_ISA_M32R1 || - c->isa_level == MIPS_CPU_ISA_M32R2 || - c->isa_level == MIPS_CPU_ISA_M64R1 || - c->isa_level == MIPS_CPU_ISA_M64R2) { + if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { #ifdef CONFIG_MIPS_CPU_SCACHE if (mips_sc_init ()) { scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; |