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authorJesper Nilsson <jesper.nilsson@axis.com>2010-08-03 17:34:28 +0200
committerJesper Nilsson <jesper.nilsson@axis.com>2010-08-04 13:02:30 +0200
commit98560bd83e73b5c0cf38e3d984892f46a405a172 (patch)
tree7ebd32772309f6ea50866b3fe7a9364ce3c77996 /arch/cris/arch-v32/mach-a3/hw_settings.S
parent2d0503d1a6816e920e5b827bbe4eea7370c8130e (diff)
CRIS: Add more delays in DDR setup
Also, make DDR latency configurable. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Diffstat (limited to 'arch/cris/arch-v32/mach-a3/hw_settings.S')
-rw-r--r--arch/cris/arch-v32/mach-a3/hw_settings.S2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/cris/arch-v32/mach-a3/hw_settings.S b/arch/cris/arch-v32/mach-a3/hw_settings.S
index 258a6329cd4a..0145725a1ce5 100644
--- a/arch/cris/arch-v32/mach-a3/hw_settings.S
+++ b/arch/cris/arch-v32/mach-a3/hw_settings.S
@@ -31,6 +31,8 @@
; Register values
.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg)
.dword CONFIG_ETRAX_DDR2_CONFIG
+ .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency)
+ .dword CONFIG_ETRAX_DDR2_LATENCY
.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing)
.dword CONFIG_ETRAX_DDR2_TIMING
.dword CONFIG_ETRAX_DDR2_MRS