diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2010-11-19 23:01:05 +0530 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2010-12-18 09:32:55 -0800 |
| commit | b0f20ff9d7e347c284ea7718597c978a2969ad7b (patch) | |
| tree | 376cd6cc0cdb6ad0714b3ea76974179e7ac6e5e8 /arch/arm/mach-omap2/omap4-common.c | |
| parent | 11e0264046e00544eb044fafc27125babd105e41 (diff) | |
omap4: l2x0: Set share override bit
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap4-common.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap4-common.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index b3cea78b5f09..2006da10f5f5 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -80,6 +80,7 @@ static int __init omap_l2_cache_init(void) aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; } else { aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | + (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT)); } |