diff options
| author | Imre Deak <imre.deak@solidboot.com> | 2007-03-05 17:22:58 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2007-09-20 18:34:49 -0700 |
| commit | df2c2e70f0cb3fa2586beffc41fcd7e093453bc5 (patch) | |
| tree | a26db59b0a0af428cd94d0160997e05b5e5e1a26 /arch/arm/mach-omap1/clock.h | |
| parent | c72d8950baf737fe4da1982a8fad1f33fecdde2e (diff) | |
ARM: OMAP: add SoSSI clock
This is needed, so that disabling the SoSSI clock during idle can
be prevented.
Signed-off-by: Imre Deak <imre.deak@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap1/clock.h')
| -rw-r--r-- | arch/arm/mach-omap1/clock.h | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 4d6060c2facb..6eadf72828d8 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -17,6 +17,8 @@ static int omap1_clk_enable_generic(struct clk * clk); static void omap1_clk_disable_generic(struct clk * clk); static void omap1_ckctl_recalc(struct clk * clk); static void omap1_watchdog_recalc(struct clk * clk); +static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); +static void omap1_sossi_recalc(struct clk *clk); static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); static int omap1_clk_enable_dsp_domain(struct clk * clk); static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); @@ -168,9 +170,10 @@ static struct clk ck_dpll1 = { static struct arm_idlect1_clk ck_dpll1out = { .clk = { - .name = "ck_dpll1out", + .name = "ck_dpll1out", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | + ENABLE_REG_32BIT | RATE_PROPAGATES, .enable_reg = (void __iomem *)ARM_IDLECT2, .enable_bit = EN_CKOUT_ARM, .recalc = &followparent_recalc, @@ -180,6 +183,19 @@ static struct arm_idlect1_clk ck_dpll1out = { .idlect_shift = 12, }; +static struct clk sossi_ck = { + .name = "ck_sossi", + .parent = &ck_dpll1out.clk, + .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | + ENABLE_REG_32BIT, + .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, + .enable_bit = 16, + .recalc = &omap1_sossi_recalc, + .set_rate = &omap1_set_sossi_rate, + .enable = &omap1_clk_enable_generic, + .disable = &omap1_clk_disable_generic, +}; + static struct clk arm_ck = { .name = "arm_ck", .parent = &ck_dpll1, @@ -760,6 +776,7 @@ static struct clk * onchip_clks[] = { &ck_dpll1, /* CK_GEN1 clocks */ &ck_dpll1out.clk, + &sossi_ck, &arm_ck, &armper_ck.clk, &arm_gpio_ck, |