diff options
author | Rob Herring <robh@kernel.org> | 2015-09-21 10:51:09 -0500 |
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committer | Rob Herring <robh@kernel.org> | 2015-10-22 09:21:21 -0500 |
commit | efdbd7345f8836f7495f3ac6ee237d86cb3bb6b0 (patch) | |
tree | 58263b9ed39c7378fe8df2e796edae86815342c4 /Documentation/devicetree/bindings/display/msm/mdp.txt | |
parent | 9ffecb10283508260936b96022d4ee43a7798b4c (diff) |
dt-bindings: consolidate display related bindings
This is a quite large renaming to consolidate display related bindings
into a single "display" directory from various scattered locations of
video, drm, gpu, fb, mipi, and panel. The prior location was somewhat
based on the Linux driver location, but bindings should be independent
of that.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'Documentation/devicetree/bindings/display/msm/mdp.txt')
-rw-r--r-- | Documentation/devicetree/bindings/display/msm/mdp.txt | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/mdp.txt b/Documentation/devicetree/bindings/display/msm/mdp.txt new file mode 100644 index 000000000000..1a0598e5279d --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdp.txt @@ -0,0 +1,48 @@ +Qualcomm adreno/snapdragon display controller + +Required properties: +- compatible: + * "qcom,mdp" - mdp4 +- reg: Physical base address and length of the controller's registers. +- interrupts: The interrupt signal from the display controller. +- connectors: array of phandles for output device(s) +- clocks: device clocks + See ../clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required: + * "core_clk" + * "iface_clk" + * "lut_clk" + * "src_clk" + * "hdmi_clk" + * "mpd_clk" + +Optional properties: +- gpus: phandle for gpu device + +Example: + +/ { + ... + + mdp: qcom,mdp@5100000 { + compatible = "qcom,mdp"; + reg = <0x05100000 0xf0000>; + interrupts = <GIC_SPI 75 0>; + connectors = <&hdmi>; + gpus = <&gpu>; + clock-names = + "core_clk", + "iface_clk", + "lut_clk", + "src_clk", + "hdmi_clk", + "mdp_clk"; + clocks = + <&mmcc MDP_SRC>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc TV_SRC>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>; + }; +}; |