diff options
| -rw-r--r-- | src/r600_exa.c | 41 | ||||
| -rw-r--r-- | src/r600_textured_videofuncs.c | 12 | ||||
| -rw-r--r-- | src/r6xx_accel.c | 10 |
3 files changed, 26 insertions, 37 deletions
diff --git a/src/r600_exa.c b/src/r600_exa.c index 462bbb8..f2136ae 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -352,11 +352,6 @@ R600DoneSolid(PixmapPtr pPix) CLEAR (draw_conf); CLEAR (vtx_res); -#ifdef XF86DRM_MODE - if (info->cs) - radeon_bo_unmap(accel_state->vb_bo); -#endif - if (accel_state->vb_index == 0) { R600IBDiscard(pScrn, accel_state->ib); r600_vb_discard(pScrn); @@ -405,11 +400,6 @@ R600DoneSolid(PixmapPtr pPix) accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0); R600CPFlushIndirect(pScrn, accel_state->ib); - - accel_state->src_bo[0] = NULL; - accel_state->src_bo[1] = NULL; - accel_state->dst_bo = NULL; - accel_state->vb_bo = NULL; } static void @@ -453,6 +443,10 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn, r600_cp_start(pScrn); /* Init */ +#if defined(XF86DRM_MODE) + if (info->cs) + accel_state->XInited3D = FALSE; +#endif start_3d(pScrn, accel_state->ib); set_default_state(pScrn, accel_state->ib); @@ -619,11 +613,6 @@ R600DoCopy(ScrnInfoPtr pScrn) CLEAR (draw_conf); CLEAR (vtx_res); -#ifdef XF86DRM_MODE - if (info->cs) - radeon_bo_unmap(accel_state->vb_bo); -#endif - if (accel_state->vb_index == 0) { R600IBDiscard(pScrn, accel_state->ib); r600_vb_discard(pScrn); @@ -1092,10 +1081,7 @@ R600DoneCopy(PixmapPtr pDst) exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area); accel_state->copy_area = NULL; } - accel_state->src_bo[0] = NULL; - accel_state->src_bo[1] = NULL; - accel_state->dst_bo = NULL; - accel_state->vb_bo = NULL; + } @@ -1611,6 +1597,8 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, if (info->cs) { accel_state->dst_mc_addr = 0; accel_state->dst_bo = radeon_get_pixmap_bo(pDst); + accel_state->src_bo[0] = NULL; + accel_state->src_bo[1] = NULL; } else #endif accel_state->dst_mc_addr = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; @@ -1633,6 +1621,10 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, r600_cp_start(pScrn); /* Init */ +#if defined(XF86DRM_MODE) + if (info->cs) + accel_state->XInited3D = FALSE; +#endif start_3d(pScrn, accel_state->ib); set_default_state(pScrn, accel_state->ib); @@ -1714,7 +1706,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, ps_conf.bo = accel_state->shaders_bo; ps_setup (pScrn, accel_state->ib, &ps_conf); - BEGIN_BATCH(12); + BEGIN_BATCH(9); EREG(accel_state->ib, CB_SHADER_MASK, (0xf << OUTPUT0_ENABLE_shift)); blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format); @@ -1893,11 +1885,6 @@ static void R600DoneComposite(PixmapPtr pDst) CLEAR (draw_conf); CLEAR (vtx_res); -#ifdef XF86DRM_MODE - if (info->cs) - radeon_bo_unmap(accel_state->vb_bo); -#endif - if (accel_state->vb_index == 0) { R600IBDiscard(pScrn, accel_state->ib); r600_vb_discard(pScrn); @@ -1954,10 +1941,6 @@ static void R600DoneComposite(PixmapPtr pDst) R600CPFlushIndirect(pScrn, accel_state->ib); - accel_state->src_bo[0] = NULL; - accel_state->src_bo[1] = NULL; - accel_state->dst_bo = NULL; - accel_state->vb_bo = NULL; } Bool diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c index a6e2559..b6f7b39 100644 --- a/src/r600_textured_videofuncs.c +++ b/src/r600_textured_videofuncs.c @@ -65,11 +65,6 @@ R600DoneTexturedVideo(ScrnInfoPtr pScrn) CLEAR (draw_conf); CLEAR (vtx_res); -#ifdef XF86DRM_MODE - if (info->cs) - radeon_bo_unmap(accel_state->vb_bo); -#endif - if (accel_state->vb_index == 0) { R600IBDiscard(pScrn, accel_state->ib); r600_vb_discard(pScrn); @@ -117,9 +112,6 @@ R600DoneTexturedVideo(ScrnInfoPtr pScrn) accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM); R600CPFlushIndirect(pScrn, accel_state->ib); - accel_state->dst_bo = NULL; - accel_state->src_bo[0] = NULL; - accel_state->src_bo[1] = NULL; } void @@ -261,6 +253,10 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) r600_cp_start(pScrn); /* Init */ +#if defined(XF86DRM_MODE) + if (info->cs) + accel_state->XInited3D = FALSE; +#endif start_3d(pScrn, accel_state->ib); set_default_state(pScrn, accel_state->ib); diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c index 8a2b1ae..7c7f469 100644 --- a/src/r6xx_accel.c +++ b/src/r6xx_accel.c @@ -39,6 +39,7 @@ #include "radeon_drm.h" +#if defined(XF86DRM_MODE) void r600_cs_flush_indirect(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -46,6 +47,11 @@ void r600_cs_flush_indirect(ScrnInfoPtr pScrn) if (!info->cs->cdw) return; + + if (info->accel_state->vb_bo) + radeon_bo_unmap(info->accel_state->vb_bo); + info->accel_state->vb_bo = NULL; + radeon_cs_emit(info->cs); radeon_cs_erase(info->cs); @@ -53,6 +59,7 @@ void r600_cs_flush_indirect(ScrnInfoPtr pScrn) if (ret) ErrorF("space check failed in flush\n"); } +#endif /* Flush the indirect buffer to the kernel for submission to the card */ void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib) @@ -98,6 +105,9 @@ void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib) int ret; RADEONInfoPtr info = RADEONPTR(pScrn); if (info->cs) { + if (info->accel_state->vb_bo) + radeon_bo_unmap(info->accel_state->vb_bo); + info->accel_state->vb_bo = NULL; if (CS_FULL(info->cs)) { r600_cs_flush_indirect(pScrn); return; |