diff options
| author | Wolke Liu <wolke.liu@amd.com> | 2009-02-02 17:01:34 -0500 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-02-02 17:01:34 -0500 |
| commit | c88c3ef6f3db266c1aacba5297b8dfc8b66bf00e (patch) | |
| tree | e5ee7856150e4fe1e475ef8343385bd10a3291e1 /src/radeon_reg.h | |
| parent | 6fac3cefd1f46161c1e276ba40e72da2823aa9f6 (diff) | |
AVIVO: Save/restore vga pll registers
This fixes some VT switch issues on some chips
Diffstat (limited to 'src/radeon_reg.h')
| -rw-r--r-- | src/radeon_reg.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 1987d61..7b8840b 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3495,6 +3495,25 @@ # define AVIVO_DVGA_CONTROL_ROTATE (1<<24) #define AVIVO_D2VGA_CONTROL 0x0338 +#define AVIVO_VGA25_PPLL_REF_DIV_SRC 0x0360 +#define AVIVO_VGA25_PPLL_REF_DIV 0x0364 +#define AVIVO_VGA28_PPLL_REF_DIV_SRC 0x0368 +#define AVIVO_VGA28_PPLL_REF_DIV 0x036c +#define AVIVO_VGA41_PPLL_REF_DIV_SRC 0x0370 +#define AVIVO_VGA41_PPLL_REF_DIV 0x0374 +#define AVIVO_VGA25_PPLL_FB_DIV 0x0378 +#define AVIVO_VGA28_PPLL_FB_DIV 0x037c +#define AVIVO_VGA41_PPLL_FB_DIV 0x0380 +#define AVIVO_VGA25_PPLL_POST_DIV_SRC 0x0384 +#define AVIVO_VGA25_PPLL_POST_DIV 0x0388 +#define AVIVO_VGA28_PPLL_POST_DIV_SRC 0x038c +#define AVIVO_VGA28_PPLL_POST_DIV 0x0390 +#define AVIVO_VGA41_PPLL_POST_DIV_SRC 0x0394 +#define AVIVO_VGA41_PPLL_POST_DIV 0x0398 +#define AVIVO_VGA25_PPLL_CNTL 0x039c +#define AVIVO_VGA28_PPLL_CNTL 0x03a0 +#define AVIVO_VGA41_PPLL_CNTL 0x03a4 + #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 #define AVIVO_EXT1_PPLL_REF_DIV 0x404 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 |