diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-10-09 11:07:30 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-10-09 11:07:30 -0400 |
| commit | de55995e82c3875f70b6394fff440d695d062113 (patch) | |
| tree | 27a08a063c9f6266fcd654a6c1d03f90722ac0a5 | |
| parent | a168caf5349b757873ad89d977772feaa7fb6e58 (diff) | |
r600 EXA: fix up mask reg mixup
| -rw-r--r-- | src/r600_exa.c | 6 | ||||
| -rw-r--r-- | src/r600_textured_videofuncs.c | 2 | ||||
| -rw-r--r-- | src/r6xx_accel.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/r600_exa.c b/src/r600_exa.c index 47f1624..a2ce5c9 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -284,7 +284,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) if (pm & 0xff000000) pmask |= 8; /* A */ BEGIN_BATCH(6); - EREG(accel_state->ib, CB_SHADER_MASK, (pmask << OUTPUT0_ENABLE_shift)); + EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift)); EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[alu]); END_BATCH(); @@ -611,7 +611,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn, if (planemask & 0xff000000) pmask |= 8; /* A */ BEGIN_BATCH(6); - EREG(accel_state->ib, CB_SHADER_MASK, (pmask << OUTPUT0_ENABLE_shift)); + EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift)); EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[rop]); END_BATCH(); @@ -1801,7 +1801,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, ps_setup (pScrn, accel_state->ib, &ps_conf); BEGIN_BATCH(9); - EREG(accel_state->ib, CB_SHADER_MASK, (0xf << OUTPUT0_ENABLE_shift)); + EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift)); blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format); diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c index ab3c498..dd4d3d1 100644 --- a/src/r600_textured_videofuncs.c +++ b/src/r600_textured_videofuncs.c @@ -516,7 +516,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) /* Render setup */ BEGIN_BATCH(6); - EREG(accel_state->ib, CB_SHADER_MASK, (0x0f << OUTPUT0_ENABLE_shift)); + EREG(accel_state->ib, CB_TARGET_MASK, (0x0f << TARGET0_ENABLE_shift)); EREG(accel_state->ib, CB_COLOR_CONTROL, (0xcc << ROP3_shift)); /* copy */ END_BATCH(); diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c index 8377ae5..dd74d46 100644 --- a/src/r6xx_accel.c +++ b/src/r6xx_accel.c @@ -971,7 +971,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) E32(ib, 0); // CB_CLRCMP_DST E32(ib, 0); // CB_CLRCMP_MSK - EREG(ib, CB_TARGET_MASK, (0x0f << TARGET0_ENABLE_shift)); + EREG(ib, CB_SHADER_MASK, (0xf << OUTPUT0_ENABLE_shift)); EREG(ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); |