diff options
| author | Dave Airlie <airlied@redhat.com> | 2009-09-08 11:25:39 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-09-08 11:25:39 +1000 |
| commit | 853f4c3d1ea8f975ab2855f18d3ae336a4095091 (patch) | |
| tree | bf6b3d4556ff284ec3f7d6e1cf646003ea9ea355 | |
| parent | 8f4196e88855f10762254fca9e0a0988e7b5562f (diff) | |
r600: more alignment fixups + vb map/unmap
I'm not so sure the vb map/unmap is a good idea, I think
it pretty much locksteps the cpu/gpu, so we should really
work out if we really need to flush this often, since
mesa doesn't have to and we are just doing 3D ops.
| -rw-r--r-- | src/r600_exa.c | 7 | ||||
| -rw-r--r-- | src/r6xx_accel.c | 9 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/r600_exa.c b/src/r600_exa.c index db4c0b1..c143b69 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -780,8 +780,7 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, radeon_bo_unref(accel_state->copy_area_bo); accel_state->copy_area_bo = NULL; } - accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, - 4096, + accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (accel_state->copy_area_bo == NULL) { @@ -789,7 +788,7 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, return FALSE; } radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo, - RADEON_GEM_DOMAIN_VRAM, 0); + 0, RADEON_GEM_DOMAIN_VRAM); if (radeon_cs_space_check(info->cs)) { radeon_bo_unref(accel_state->copy_area_bo); accel_state->copy_area_bo = NULL; @@ -2157,7 +2156,7 @@ R600AllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen) #ifdef XF86DRM_MODE #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4) if (info->cs) { - accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 4096, + accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (accel_state->shaders_bo == NULL) { ErrorF("Allocating shader failed\n"); diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c index 6346e52..985595e 100644 --- a/src/r6xx_accel.c +++ b/src/r6xx_accel.c @@ -50,8 +50,7 @@ void r600_cs_flush_indirect(ScrnInfoPtr pScrn) if (info->accel_state->vb_bo) { radeon_bo_unmap(info->accel_state->vb_bo); - radeon_bo_ref(info->accel_state->vb_bo); - info->accel_state->vb_bo = NULL; + info->accel_state->vb_ptr = NULL; } radeon_cs_emit(info->cs); @@ -1161,15 +1160,17 @@ r600_vb_get(ScrnInfoPtr pScrn) if (accel_state->vb_bo == NULL) { accel_state->vb_mc_addr = 0; accel_state->vb_bo = radeon_bo_open(info->bufmgr, 0, 16 * 1024, - 4096, RADEON_GEM_DOMAIN_GTT, 0); + 0, RADEON_GEM_DOMAIN_GTT, 0); if (accel_state->vb_bo == NULL) return FALSE; + accel_state->vb_total = 16 * 1024; + } + if (!accel_state->vb_ptr) { ret = radeon_bo_map(accel_state->vb_bo, 1); if (ret) { FatalError("failed to vb %d\n", ret); return FALSE; } - accel_state->vb_total = 16 * 1024; accel_state->vb_ptr = accel_state->vb_bo->ptr; } } else |