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authorAlex Deucher <alexdeucher@gmail.com>2009-09-25 16:46:43 -0400
committerAlex Deucher <alexdeucher@gmail.com>2009-09-25 16:46:43 -0400
commit0380a9cf98d34e88dd81370ade5525680ec89c02 (patch)
tree1b23e897f7cec4afa66b9b0c92c928c9deebe89e
parent3efecebb10de7f7bacf9f8c57ae20fd508097294 (diff)
kms/r600: add support for vline relocs
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
-rw-r--r--src/r6xx_accel.c37
1 files changed, 29 insertions, 8 deletions
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index f5e6bce..8377ae5 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -318,12 +318,6 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t offset;
- //XXX FIXME
-#if defined(XF86DRM_MODE)
- if (info->cs)
- return;
-#endif
-
if (!crtc)
return;
@@ -333,7 +327,10 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
if (!crtc->enabled)
return;
- {
+ if (info->cs) {
+ if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen))
+ return;
+ } else {
#ifdef USE_EXA
if (info->useEXA)
offset = exaGetPixmapOffset(pPix);
@@ -352,10 +349,34 @@ void cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
if (start > crtc->mode.VDisplay)
return;
+#if defined(XF86DRM_MODE)
+ if (info->cs) {
+ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
+
+ BEGIN_BATCH(11);
+ /* set the VLINE range */
+ EREG(ib, AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
+ (start << AVIVO_D1MODE_VLINE_START_SHIFT) |
+ (stop << AVIVO_D1MODE_VLINE_END_SHIFT));
+
+ /* tell the CP to poll the VLINE state register */
+ PACK3(ib, IT_WAIT_REG_MEM, 6);
+ E32(ib, IT_WAIT_REG | IT_WAIT_EQ);
+ E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS));
+ E32(ib, 0);
+ E32(ib, 0); // Ref value
+ E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask
+ E32(ib, 10); // Wait interval
+ /* add crtc reloc */
+ PACK3(ib, IT_NOP, 1);
+ E32(ib, drmmode_crtc->mode_crtc->crtc_id);
+ END_BATCH();
+ } else
+#endif
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- BEGIN_BATCH(10);
+ BEGIN_BATCH(9);
/* set the VLINE range */
EREG(ib, AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
(start << AVIVO_D1MODE_VLINE_START_SHIFT) |