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authorJohn Clements <john.clements@amd.com>2020-09-24 22:20:31 +0800
committerLikun Gao <Likun.Gao@amd.com>2020-09-25 11:46:51 +0800
commit6c34fe556727b7de13d641f634f78d10f03e11a8 (patch)
tree597aa0d701813ef822df759b8e2d01c7062a338f
parent1a1fbcd497314dc623b60c77e8a50b4419b185e4 (diff)
drm/amdgpu: disable sienna chichlid UMC RAS
disable UMC RAS in lieu of stability issues on certain sku Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Change-Id: Ibd6f634548e99fb895b4a12601935d1a843af2a1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e5ea14774c0c..e4a81531fc98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1967,8 +1967,7 @@ static int amdgpu_ras_check_asic_type(struct amdgpu_device *adev)
{
if (adev->asic_type != CHIP_VEGA10 &&
adev->asic_type != CHIP_VEGA20 &&
- adev->asic_type != CHIP_ARCTURUS &&
- adev->asic_type != CHIP_SIENNA_CICHLID)
+ adev->asic_type != CHIP_ARCTURUS)
return 1;
else
return 0;
@@ -2012,6 +2011,7 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
*supported = amdgpu_ras_enable == 0 ?
0 : *hw_supported & amdgpu_ras_mask;
+
adev->ras_features = *supported;
}