DRI XFree86-4_3_99_12-merge importDRI-XFree86-4_3_99_12-merge

10 files changed, 75 insertions, 159 deletions

diff --git a/hw/xfree86/os-support/bus/Pci.c b/hw/xfree86/os-support/bus/Pci.c
index 6b36fdaf2..bccf4456f 100644
--- a/hw/xfree86/os-support/bus/Pci.c
+++ b/hw/xfree86/os-support/bus/Pci.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/Pci.c,v 1.82 2004/01/16 15:39:04 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/Pci.c,v 1.80 2003/08/29 20:49:03 tsi Exp $ */
 /*
  * Pci.c - New server PCI access functions
  *
@@ -453,9 +453,9 @@ pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr)
  * to the base address register to get an accurate result.  Otherwise it
  * makes a conservative guess based on the alignment of the already allocated
  * address.  If the result is accurate (ie, not an over-estimate), this is
- * indicated by setting *min to TRUE (when min is non-NULL).  This happens
- * when either the destructive flag is set, the information is supplied by
- * the OS if the OS supports this.
+ * indicated by setting *min to TRUE (when min is non-NULL).  This currently
+ * only happens when the destructive flag is set, but in future it may be
+ * possible to get the information from the OS when supported.
  */
 
 int
@@ -575,7 +575,7 @@ Bool
 pciMfDev(int busnum, int devnum)
 {
     PCITAG tag0, tag1;
-    CARD32 id0, id1, val;
+    unsigned long id0, id1, val;
 
     /* Detect a multi-function device that complies to the PCI 2.0 spec */
 
@@ -782,7 +782,7 @@ pciGenFindNext(void)
 		    (sub_class != PCI_SUBCLASS_BRIDGE_CARDBUS))
 		    xf86Msg(X_WARNING,
 			    "pciGenFindNext:  primary bus mismatch on PCI"
-			    " bridge 0x%08lx (0x%02x, 0x%02x)\n",
+			    " bridge 0x%08x (0x%02x, 0x%02x)\n",
 			    pciDeviceTag, pciBusNum, pri_bus);
 		pri_bus = pciBusNum;
 	    }
@@ -1016,9 +1016,7 @@ xf86scanpci(int flags)
 	    if (!(devp->pci_bridge_control & PCI_PCI_BRIDGE_MASTER_ABORT_EN))
 		break;
 	    pciWriteByte(tag, PCI_PCI_BRIDGE_CONTROL_REG,
-		devp->pci_bridge_control &
-		     ~(PCI_PCI_BRIDGE_MASTER_ABORT_EN |
-		       PCI_PCI_BRIDGE_SECONDARY_RESET));
+		devp->pci_bridge_control & ~PCI_PCI_BRIDGE_MASTER_ABORT_EN);
 	    break;
 
 	default:
@@ -1081,7 +1079,7 @@ xf86scanpci(int flags)
 	    if (!(devp->pci_bridge_control & PCI_PCI_BRIDGE_MASTER_ABORT_EN))
 		break;
 	    pciWriteByte(devp->tag, PCI_PCI_BRIDGE_CONTROL_REG,
-		devp->pci_bridge_control & ~PCI_PCI_BRIDGE_SECONDARY_RESET);
+		devp->pci_bridge_control);
 	    break;
 
 	default:
@@ -1139,7 +1137,7 @@ xf86MapPciMem(int ScreenNum, int Flags, PCITAG Tag, ADDRESS Base,
 	base = xf86MapDomainMemory(ScreenNum, Flags, Tag, hostbase, Size);
 	if (!base)	{
 		FatalError("xf86MapPciMem: Could not mmap PCI memory "
-			   "[base=0x%lx,hostbase=0x%lx,size=%lx] (%s)\n",
+			   "[base=0x%x,hostbase=0x%x,size=%x] (%s)\n",
 			   Base, hostbase, Size, strerror(errno));
 	}
 	/*
@@ -1189,8 +1187,8 @@ handlePciBIOS(PCITAG Tag, int basereg,
 	    savebase = pciReadLong(Tag, PCI_MAP_REG_START+(b_reg<<2));
 	    xf86MsgVerb(X_INFO,5,"xf86ReadPciBios: modifying membase[%i]"
 			" for device %i:%i:%i\n", basereg,
-			(int)PCI_BUS_FROM_TAG(Tag), (int)PCI_DEV_FROM_TAG(Tag),
-			(int)PCI_FUNC_FROM_TAG(Tag));
+			PCI_BUS_FROM_TAG(Tag), PCI_DEV_FROM_TAG(Tag),
+			PCI_FUNC_FROM_TAG(Tag));
 	    pciWriteLong(Tag, PCI_MAP_REG_START + (b_reg << 2),
 			 (CARD32)~0);
 	}
@@ -1299,7 +1297,7 @@ readPciBios(PCITAG Tag, CARD8* tmp, ADDRESS hostbase, pointer args)
     }
     if ((rd->Offset) > (image_length)) {
       xf86Msg(X_WARNING,"xf86ReadPciBios: requesting data past "
-	      "end of BIOS %li > %i\n",(rd->Offset) , (image_length));
+	      "end of BIOS %i > %i\n",(rd->Offset) , (image_length));
     } else {
       if ((rd->Offset + rd->Len) > (image_length)) {
 	rd->Len = (image_length) - rd->Offset;
diff --git a/hw/xfree86/os-support/bus/Pci.h b/hw/xfree86/os-support/bus/Pci.h
index 36b4a477e..529613ad7 100644
--- a/hw/xfree86/os-support/bus/Pci.h
+++ b/hw/xfree86/os-support/bus/Pci.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/Pci.h,v 1.45 2004/02/02 03:55:31 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/Pci.h,v 1.42 2003/08/29 21:08:06 tsi Exp $ */
 /*
  * Copyright 1998 by Concurrent Computer Corporation
  *
@@ -255,13 +255,9 @@
 #  define ARCH_PCI_INIT linuxPciInit
 #  define INCLUDE_XF86_MAP_PCI_MEM
 #  define INCLUDE_XF86_NO_DOMAIN
-# elif defined(FreeBSD)
-#  define ARCH_PCI_INIT freebsdPciInit
-#  define INCLUDE_XF86_MAP_PCI_MEM
-#  define INCLUDE_XF86_NO_DOMAIN
 # endif
 # define XF86SCANPCI_WRAPPER ia64ScanPCIWrapper
-#elif defined(__i386__) || defined(i386)
+#elif defined(__i386__)
 # define ARCH_PCI_INIT ix86PciInit
 # define INCLUDE_XF86_MAP_PCI_MEM
 # define INCLUDE_XF86_NO_DOMAIN
@@ -312,27 +308,21 @@
 #  define INCLUDE_XF86_MAP_PCI_MEM
 #  define INCLUDE_XF86_NO_DOMAIN
 # endif
-#elif defined(__sparc__) || defined(sparc)
+#elif defined(__sparc__)
 # if defined(linux)
 #  define ARCH_PCI_INIT linuxPciInit
 #  define INCLUDE_XF86_MAP_PCI_MEM
 # elif defined(sun)
 #  define ARCH_PCI_INIT sparcPciInit
 #  define INCLUDE_XF86_MAP_PCI_MEM
-# elif (defined(__OpenBSD__) || defined(__FreeBSD__)) && defined(__sparc64__)
+# elif defined(__OpenBSD__) && defined(__sparc64__)
 #  define  ARCH_PCI_INIT freebsdPciInit
 #  define INCLUDE_XF86_MAP_PCI_MEM
 #  define INCLUDE_XF86_NO_DOMAIN
 # endif
-# if !defined(__FreeBSD__)
-#  define ARCH_PCI_PCI_BRIDGE sparcPciPciBridge
-# endif
-#elif defined(__amd64__)
-# if defined(__FreeBSD__)
-#  define ARCH_PCI_INIT freebsdPciInit
-# else
-#  define ARCH_PCI_INIT ix86PciInit
-# endif
+# define ARCH_PCI_PCI_BRIDGE sparcPciPciBridge
+#elif defined(__AMD64__)
+# define ARCH_PCI_INIT ix86PciInit
 # define INCLUDE_XF86_MAP_PCI_MEM
 # define INCLUDE_XF86_NO_DOMAIN
 # if defined(linux)
diff --git a/hw/xfree86/os-support/bus/Sbus.c b/hw/xfree86/os-support/bus/Sbus.c
index f81112474..4be660a75 100644
--- a/hw/xfree86/os-support/bus/Sbus.c
+++ b/hw/xfree86/os-support/bus/Sbus.c
@@ -20,7 +20,7 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/Sbus.c,v 1.2tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/Sbus.c,v 1.3 2003/06/10 20:48:01 tsi Exp $ */
 
 #include <fcntl.h>
 #include <stdio.h>
@@ -170,8 +170,6 @@ promIsP1275(void)
 	promP1275 = TRUE;
     else
 	promP1275 = FALSE;
-#elif defined(__FreeBSD__)
-    promP1275 = TRUE;
 #else
 #error Missing promIsP1275() function for this OS
 #endif
diff --git a/hw/xfree86/os-support/bus/axpPci.c b/hw/xfree86/os-support/bus/axpPci.c
index d218a0d2f..04ff8b956 100644
--- a/hw/xfree86/os-support/bus/axpPci.c
+++ b/hw/xfree86/os-support/bus/axpPci.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/axpPci.c,v 1.14 2002/12/11 02:44:28 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/axpPci.c,v 1.15 2002/12/12 04:12:02 dawes Exp $ */
 /*
  * Copyright 1998 by Concurrent Computer Corporation
  *
diff --git a/hw/xfree86/os-support/bus/freebsdPci.c b/hw/xfree86/os-support/bus/freebsdPci.c
index 3b2bf5a9b..c3e621daf 100644
--- a/hw/xfree86/os-support/bus/freebsdPci.c
+++ b/hw/xfree86/os-support/bus/freebsdPci.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/freebsdPci.c,v 1.4 2002/07/24 19:06:52 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/freebsdPci.c,v 1.5 2002/08/27 22:07:07 tsi Exp $ */
 /*
  * Copyright 1998 by Concurrent Computer Corporation
  *
@@ -84,7 +84,7 @@ static pciBusInfo_t freebsdPci0 = {
 /* bridge      */	NULL
 };
 
-#if !defined(__OpenBSD__) && !defined(__FreeBSD__)
+#if !defined(__OpenBSD__)
 #if X_BYTE_ORDER == X_BIG_ENDIAN
 #ifdef __sparc__
 #ifndef ASI_PL
diff --git a/hw/xfree86/os-support/bus/ix86Pci.c b/hw/xfree86/os-support/bus/ix86Pci.c
index b135d0b73..4ce835acb 100644
--- a/hw/xfree86/os-support/bus/ix86Pci.c
+++ b/hw/xfree86/os-support/bus/ix86Pci.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ix86Pci.c,v 1.25 2003/09/24 02:43:34 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ix86Pci.c,v 1.24 2003/08/29 20:49:03 tsi Exp $ */
 /*
  * ix86Pci.c - x86 PCI driver
  *
@@ -345,9 +345,8 @@ void ix86PciSelectCfgmech(void)
 
 		xf86MsgVerb(X_INFO, 2, "PCI: Config type is 1\n");
 		xf86MsgVerb(X_INFO, 3,
-			"PCI: stages = 0x%02x, oldVal1 = 0x%08lx, mode1Res1"
-			" = 0x%08lx\n", stages, (unsigned long)oldVal1,
-			(unsigned long)mode1Res1);
+			"PCI: stages = 0x%02x, oldVal1 = 0x%08x, mode1Res1"
+			" = 0x%08x\n", stages, oldVal1, mode1Res1);
 		return;
 	    }
 
@@ -400,10 +399,9 @@ void ix86PciSelectCfgmech(void)
 
 		xf86MsgVerb(X_INFO, 2, "PCI: Config type is 1\n");
 		xf86MsgVerb(X_INFO, 3,
-			"PCI: stages = 0x%02x, oldVal1 = 0x%08lx,\n"
-			"\tmode1Res1 = 0x%08lx, mode1Res2 = 0x%08lx\n",
-			stages, (unsigned long)oldVal1,
-			(unsigned long)mode1Res1, (unsigned long)mode1Res2);
+			"PCI: stages = 0x%02x, oldVal1 = 0x%08x,\n"
+			"\tmode1Res1 = 0x%08x, mode1Res2 = 0x%08x\n",
+			stages, oldVal1, mode1Res1, mode1Res2);
 		return;
 	    }
 
@@ -417,10 +415,9 @@ void ix86PciSelectCfgmech(void)
       }
 
       xf86MsgVerb(X_INFO, 3, "PCI: Standard check for type 1 failed.\n");
-      xf86MsgVerb(X_INFO, 3, "PCI: stages = 0x%02x, oldVal1 = 0x%08lx,\n"
-	       "\tmode1Res1 = 0x%08lx, mode1Res2 = 0x%08lx\n",
-	       stages, (unsigned long)oldVal1, (unsigned long)mode1Res1,
-	       (unsigned long)mode1Res2);
+      xf86MsgVerb(X_INFO, 3, "PCI: stages = 0x%02x, oldVal1 = 0x%08x,\n"
+	       "\tmode1Res1 = 0x%08x, mode1Res2 = 0x%08x\n",
+	       stages, oldVal1, mode1Res1, mode1Res2);
 
       /* Try config type 2 */
       oldVal2 = inb(PCI_CFGMECH2_ENABLE_REG);
diff --git a/hw/xfree86/os-support/bus/linuxPci.c b/hw/xfree86/os-support/bus/linuxPci.c
index 4846ee0ed..76194802f 100644
--- a/hw/xfree86/os-support/bus/linuxPci.c
+++ b/hw/xfree86/os-support/bus/linuxPci.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c,v 1.9 2002/09/24 16:14:16 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/linuxPci.c,v 1.10 2002/11/17 18:42:01 alanh Exp $ */
 /*
  * Copyright 1998 by Concurrent Computer Corporation
  *
diff --git a/hw/xfree86/os-support/bus/ppcPci.c b/hw/xfree86/os-support/bus/ppcPci.c
index 7b00acb6b..2aa98355b 100644
--- a/hw/xfree86/os-support/bus/ppcPci.c
+++ b/hw/xfree86/os-support/bus/ppcPci.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ppcPci.c,v 1.8 2002/07/24 19:06:52 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ppcPci.c,v 1.9 2002/08/27 22:07:07 tsi Exp $ */
 /*
  * ppcPci.c - PowerPC PCI access functions
  *
diff --git a/hw/xfree86/os-support/bus/xf86Sbus.h b/hw/xfree86/os-support/bus/xf86Sbus.h
index dbd17810f..5c8acfd4b 100644
--- a/hw/xfree86/os-support/bus/xf86Sbus.h
+++ b/hw/xfree86/os-support/bus/xf86Sbus.h
@@ -20,7 +20,7 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/xf86Sbus.h,v 1.3 2001/04/20 17:02:43 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/xf86Sbus.h,v 1.5 2002/05/22 21:38:30 herrb Exp $ */
 
 #ifndef _XF86_SBUS_H
 #define _XF86_SBUS_H
@@ -35,13 +35,7 @@
 #elif defined(__OpenBSD__) && defined(__sparc64__)
 /* XXX */
 #elif defined(CSRG_BASED)
-#if defined(__FreeBSD__)
-#include <sys/types.h>
-#include <sys/fbio.h>
-#include <dev/ofw/openpromio.h>
-#else
 #include <machine/fbio.h>
-#endif
 #else
 #include <sun/fbio.h>
 #endif
diff --git a/hw/xfree86/os-support/bus/zx1PCI.c b/hw/xfree86/os-support/bus/zx1PCI.c
index 5d4d6a991..16640b95b 100644
--- a/hw/xfree86/os-support/bus/zx1PCI.c
+++ b/hw/xfree86/os-support/bus/zx1PCI.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/zx1PCI.c,v 1.8 2004/01/16 15:39:38 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/zx1PCI.c,v 1.3 2003/07/17 15:08:22 tsi Exp $ */
 /*
  * Copyright (C) 2002-2003 The XFree86 Project, Inc.  All Rights Reserved.
  *
@@ -97,10 +97,9 @@
 #define LBA_PORT5_CNTRL		0x1228U
 #define LBA_PORT6_CNTRL		0x1230U
 #define LBA_PORT7_CNTRL		0x1238U
-#define LBA_RESET_FUNCTION	  0x0000000001UL
-#define LBA_CLEAR_ERROR		  0x0000000010UL
-#define LBA_HARD_FAIL		  0x0000000040UL
-#define LBA_RESET_COMPLETE	  0x0100000000UL
+#define LBA_ROPE_RESET		  0x01UL
+#define LBA_CLEAR_ERROR		  0x10UL
+#define LBA_HARD_FAIL		  0x40UL
 
 #define ROPE_PAGE_CONTROL	0x1418U
 
@@ -118,11 +117,8 @@
 #define IOA_SUBORDINATE_BUS	0x0059U
 
 #define IOA_CONTROL		0x0108U
-#define IOA_RESET_FUNCTION	  0x0000000001UL
-#define IOA_FORWARD_VGA		  0x0000000008UL
-#define IOA_CLEAR_ERROR		  0x0000000010UL
-#define IOA_HARD_FAIL		  0x0000000040UL
-#define IOA_RESET_COMPLETE	  0x0100000000UL
+#define IOA_FORWARD_VGA		  0x08UL
+#define IOA_HARD_FAIL		  0x40UL
 
 #define IOA_LMMIO_BASE		0x0200U
 #define IOA_LMMIO_MASK		0x0208U
@@ -138,33 +134,12 @@
 #define IOA_ELMMIO_MASK		0x0258U
 #define IOA_EIOS_BASE		0x0260U
 #define IOA_EIOS_MASK		0x0268U
-#define IOA_GLOBAL_MASK		0x0270U
+
 #define IOA_SLAVE_CONTROL	0x0278U
 #define IOA_VGA_PEER_ENABLE	  0x2000UL
 #define IOA_MSI_BASE		0x0280U
 #define IOA_MSI_MASK		0x0288U
 
-#define IOA_DMA_BASE		0x02B0U
-#define IOA_DMA_MASK		0x02B8U
-
-#define IOA_ERROR_CONFIG	0x0680U
-#define IOA_ERROR_PIOWRITE	  0x0001UL
-#define IOA_ERROR_PIOREAD	  0x0002UL
-#define IOA_ERROR_DMAWRITE	  0x0004UL
-#define IOA_ERROR_DMAREAD	  0x0008UL
-#define IOA_ERROR_CONFIG_MASTER	  0x0010UL
-#define IOA_ERROR_SMART		  0x0020UL
-#define IOA_ERROR_FATAL_SERR	  0x0040UL
-#define IOA_ERROR_ASSERT_SERR	  0x0080UL
-/*	?			  0x0100UL */
-#define IOA_ERROR_LOOPBACK	  0x0200UL
-#define IOA_ERROR_CONFIG_TARGET	  0x0400UL
-#define IOA_ERROR_IO_MASTER	  0x0800UL
-#define IOA_ERROR_IO_TARGET	  0x1000UL
-#define IOA_ERROR_MEM_MASTER	  0x2000UL
-#define IOA_ERROR_MEM_TARGET	  0x4000UL
-#define IOA_ERROR_HF_IO_FATAL	  0x8000UL
-
 #define RANGE_ENABLE		0x01UL		/* In various base registers */
 
 #define IO_MASK			((1UL << 16) - 1UL)
@@ -181,15 +156,10 @@
 static CARD8 *pZX1mio = NULL,
 	     *pZX1ioa = NULL;
 
-/* Per-rope data */
-static INT8   zx1_ropemap[8];
-static CARD32 zx1_pciids[8];
-static CARD64 zx1_lbacntl[8];
+static INT8   zx1_ropemap[8];		/* One for each (potential) rope */
+static CARD64 zx1_lbacntl[8];		/*  "   "   "        "       "   */
 static int    zx1_busno[8], zx1_subno[8];
 
-/* Array of Booleans for non-empty buses */
-static INT8   zx1_busnmpt[MAX_PCI_BUSES];
-
 static pciBusFuncs_t zx1BusFuncs;
 static int           zx1_fakebus = -1;
 static Bool          zx1_hasvga = FALSE;
@@ -322,8 +292,7 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value)
 	 * SLAVE_CONTROL register.
 	 */
 	tmp1 = MIO_QUAD(VGA_ROUTE);
-	tmp2 = IOA_QUAD(ropenum, IOA_CONTROL) &
-	    ~(IOA_RESET_FUNCTION | IOA_CLEAR_ERROR);
+	tmp2 = IOA_QUAD(ropenum, IOA_CONTROL);
 	if ((tmp1 & VGA_ENABLE) && ((tmp1 & 0x07UL) == ropenum)) {
 	    current |= PCI_PCI_BRIDGE_VGA_EN;
 	    if ((mask & PCI_PCI_BRIDGE_VGA_EN) &&
@@ -346,9 +315,8 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value)
 		    MIO_QUAD(VGA_ROUTE) = 0UL;
 		    tmp3 = IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL);
 		    if (tmp3 & IOA_FORWARD_VGA)
-			IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL) = tmp3 &
-			    ~(IOA_RESET_FUNCTION | IOA_FORWARD_VGA |
-			      IOA_CLEAR_ERROR);
+			IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL) =
+			    tmp3 & ~IOA_FORWARD_VGA;
 		}
 		if (!(tmp2 & IOA_FORWARD_VGA)) {
 		    tmp2 |= IOA_FORWARD_VGA;
@@ -361,7 +329,7 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value)
 
 	/* Move on to master abort failure enablement */
 	tmp1 = MIO_QUAD((ropenum << 3) + LBA_PORT0_CNTRL) &
-	       ~(LBA_RESET_FUNCTION | LBA_CLEAR_ERROR);
+	       ~(LBA_ROPE_RESET | LBA_CLEAR_ERROR);
 	if ((tmp1 & LBA_HARD_FAIL) || (tmp2 & IOA_HARD_FAIL)) {
 	    current |= PCI_PCI_BRIDGE_MASTER_ABORT_EN;
 	    if ((mask & PCI_PCI_BRIDGE_MASTER_ABORT_EN) &&
@@ -423,15 +391,14 @@ GetZX1BridgeResources(int bus,
 static CARD32
 zx1FakeReadLong(PCITAG tag, int offset)
 {
-    FatalError("zx1FakeReadLong(0x%lX, 0x%X) called\n",
-	       (unsigned long)tag, offset);
+    FatalError("zx1FakeReadLong(0x%X, 0x%X) called\n", tag, offset);
 }
 
 static void
 zx1FakeWriteLong(PCITAG tag, int offset, CARD32 val)
 {
-    FatalError("zx1FakeWriteLong(0x%lX, 0x%X, 0x%08X) called\n",
-	       (unsigned long)tag, offset, val);
+    FatalError("zx1FakeWriteLong(0x%X, 0x%X, 0x%08X) called\n",
+	       tag, offset, val);
 }
 
 static void
@@ -477,13 +444,13 @@ xf86PreScanZX1(void)
     resRange range;
     unsigned long mapSize = xf86getpagesize();
     unsigned long tmp, base, ioaaddr;
-    unsigned long flagsd, based, lastd, maskd, routed;
-    unsigned long flags0, base0, last0, mask0, route0;
-    unsigned long flags1, base1, last1, mask1, route1;
-    unsigned long flags2, base2, last2, mask2, route2;
-    unsigned long flags3, base3, last3, mask3, route3;
-    unsigned long flagsg, baseg, lastg, maskg, routeg;
-    unsigned long flagsl, basel, lastl;
+    unsigned long flagsd = 0, based = 0, lastd = 0, maskd = 0, routed = 0;
+    unsigned long flags0 = 0, base0 = 0, last0 = 0, mask0 = 0, route0 = 0;
+    unsigned long flags1 = 0, base1 = 0, last1 = 0, mask1 = 0, route1 = 0;
+    unsigned long flags2 = 0, base2 = 0, last2 = 0, mask2 = 0, route2 = 0;
+    unsigned long flags3 = 0, base3 = 0, last3 = 0, mask3 = 0, route3 = 0;
+    unsigned long flagsg = 0, baseg = 0, lastg = 0, maskg = 0, routeg = 0;
+    unsigned long flagsl = 0, basel = 0, lastl = 0;
     int i, rope;
 
     /* Map mio registers (minimum 8k) */
@@ -493,7 +460,7 @@ xf86PreScanZX1(void)
     if (!(pZX1mio = xf86MapVidMem(-1, VIDMEM_MMIO, MIO_BASE, mapSize)))
 	return FALSE;
 
-    /* Look for ZX1's SBA and IOC */	/* XXX What about Dino? */
+    /* Look for ZX1's SBA and IOC */
     if ((MIO_LONG(MIO_FUNCTION0 + PCI_ID_REG) !=
 	 DEVID(VENDOR_HP, CHIP_ZX1_SBA)) ||
 	(MIO_LONG(MIO_FUNCTION1 + PCI_ID_REG) !=
@@ -552,17 +519,16 @@ xf86PreScanZX1(void)
 
 	    /* Prevent hard-fails */
 	    zx1_lbacntl[i] = MIO_QUAD((i << 3) + LBA_PORT0_CNTRL) &
-		~(LBA_RESET_FUNCTION | LBA_CLEAR_ERROR);
+		~(LBA_ROPE_RESET | LBA_CLEAR_ERROR);
 	    if (zx1_lbacntl[i] & LBA_HARD_FAIL)
 		MIO_QUAD((i << 3) + LBA_PORT0_CNTRL) =
 		    zx1_lbacntl[i] & ~LBA_HARD_FAIL;
 
 	    /* Poke for an ioa */
-	    zx1_pciids[i] = IOA_LONG(i, PCI_ID_REG);
-	    switch (zx1_pciids[i]) {
+	    tmp = IOA_LONG(i, PCI_ID_REG);
+	    switch ((CARD32)tmp) {
 	    case DEVID(VENDOR_HP, CHIP_ELROY):
-	    case DEVID(VENDOR_HP, CHIP_ZX1_LBA):	/* Mercury */
-	    case DEVID(VENDOR_HP, CHIP_ZX1_AGP8):	/* QuickSilver */
+	    case DEVID(VENDOR_HP, CHIP_ZX1_LBA):
 		/* Expected vendor/device IDs */
 		zx1_busno[i] =
 		    (unsigned int)IOA_BYTE(i, IOA_SECONDARY_BUS);
@@ -571,10 +537,10 @@ xf86PreScanZX1(void)
 		break;
 
 	    default:
-		if ((CARD16)(zx1_pciids[i] + 1U) > (CARD16)1U)
+		if ((CARD16)(tmp + 1U) > (CARD16)1U)
 		    xf86MsgVerb(X_NOTICE, 0,
 			"HP ZX1:  Unexpected vendor/device id 0x%08X"
-			" on rope %d\n", zx1_pciids[i], i);
+			" on rope %d\n", (CARD32)tmp, i);
 		/* Nobody home, or not the "right" kind of rope guest */
 
 		/*
@@ -621,14 +587,6 @@ xf86PreScanZX1(void)
      * ones.
      */
 
-    flagsd = 0; based = 0; lastd = 0; maskd = 0; routed = 0;
-    flags0 = 0; base0 = 0; last0 = 0; mask0 = 0; route0 = 0;
-    flags1 = 0; base1 = 0; last1 = 0; mask1 = 0; route1 = 0;
-    flags2 = 0; base2 = 0; last2 = 0; mask2 = 0; route2 = 0;
-    flags3 = 0; base3 = 0; last3 = 0; mask3 = 0; route3 = 0;
-    flagsg = 0; baseg = 0; lastg = 0; maskg = 0; routeg = 0;
-    flagsl = 0; basel = 0; lastl = 0;
-
     if ((tmp = MIO_QUAD(IOS_DIST_BASE)) & RANGE_ENABLE) {
 	flagsd = RANGE_ENABLE;
 	maskd = MIO_QUAD(IOS_DIST_MASK);
@@ -938,9 +896,6 @@ xf86PostScanZX1(void)
     if (!pZX1mio)
 	return;
 
-    (void)memset(zx1_busnmpt, FALSE, sizeof(zx1_busnmpt));
-    pBusInfo = pciBusInfo[0];
-
     /*
      * Certain 2.4 & 2.5 Linux kernels add fake PCI devices.  Remove them to
      * prevent any possible interference with our PCI validation.
@@ -952,11 +907,9 @@ xf86PostScanZX1(void)
     ppPCI = ppPCI2 = xf86scanpci(0);	/* Recursion is only apparent */
     while ((pPCI = *ppPCI2++)) {
 	switch (pPCI->pci_device_vendor) {
-	case DEVID(VENDOR_HP, CHIP_ELROY):
-	case DEVID(VENDOR_HP, CHIP_ZX1_SBA):	/* Pluto function 0 */
-	case DEVID(VENDOR_HP, CHIP_ZX1_IOC):	/* Pluto function 1 */
-	case DEVID(VENDOR_HP, CHIP_ZX1_LBA):	/* Mercury */
-	case DEVID(VENDOR_HP, CHIP_ZX1_AGP8):	/* QuickSilver */
+	case DEVID(VENDOR_HP, CHIP_ZX1_SBA):
+	case DEVID(VENDOR_HP, CHIP_ZX1_IOC):
+	case DEVID(VENDOR_HP, CHIP_ZX1_LBA):
 	    xfree(pPCI);		/* Remove it */
 	    continue;
 
@@ -964,8 +917,6 @@ xf86PostScanZX1(void)
 	    *ppPCI++ = pPCI;
 	    idx++;
 
-	    zx1_busnmpt[pPCI->busnum] = TRUE;
-
 	    if (zx1_hasvga)
 		continue;
 
@@ -990,8 +941,8 @@ xf86PostScanZX1(void)
     }
 
     /*
-     * Restore hard-fail settings and figure out the actual secondary and
-     * subordinate bus numbers.
+     * Restore hard-fail settings and figure out the actual subordinate bus
+     * numbers.
      */
     for (i = 0;  i < 8;  i++) {
 	if (zx1_ropemap[i] != i)
@@ -1005,14 +956,6 @@ xf86PostScanZX1(void)
 
 	if (zx1_fakebus <= zx1_subno[i])
 	    zx1_fakebus = zx1_subno[i] + 1;
-
-	while (!zx1_busnmpt[zx1_busno[i]]) {
-	    if (zx1_busno[i])	/* Info for bus zero is in static storage */
-		xfree(pciBusInfo[zx1_busno[i]]);
-	    pciBusInfo[zx1_busno[i]++] = NULL;
-	    if (zx1_busno[i] > zx1_subno[i])
-		break;
-	}
     }
 
     if (zx1_fakebus >= pciNumBuses) {
@@ -1022,13 +965,13 @@ xf86PostScanZX1(void)
     }
 
     /* Set up our extra bus functions */
-    zx1BusFuncs = *(pBusInfo->funcs);
+    zx1BusFuncs = *(pciBusInfo[0]->funcs);
     zx1BusFuncs.pciControlBridge = ControlZX1Bridge;
     zx1BusFuncs.pciGetBridgeResources = GetZX1BridgeResources;
 
     /* Set up our own fake bus to act as the root segment */
-    zx1FakeBus.configMech = pBusInfo->configMech;
-    zx1FakeBus.numDevices = pBusInfo->numDevices;
+    zx1FakeBus.configMech = pciBusInfo[0]->configMech;
+    zx1FakeBus.numDevices = pciBusInfo[0]->numDevices;
     zx1FakeBus.primary_bus = zx1_fakebus;
     pciBusInfo[zx1_fakebus] = &zx1FakeBus;
 
@@ -1063,8 +1006,7 @@ xf86PostScanZX1(void)
 
     /* Add a fake PCI-to-PCI bridge to represent each active rope */
     for (i = 0;  i < 8;  i++) {
-	if ((zx1_ropemap[i] != i) || (zx1_busno[i] > zx1_subno[i]) ||
-	    !(pBusInfo = pciBusInfo[zx1_busno[i]]))
+	if ((zx1_ropemap[i] != i) || !(pBusInfo = pciBusInfo[zx1_busno[i]]))
 	    continue;
 
 	if (++idx >= MAX_PCI_DEVICES)
@@ -1074,7 +1016,7 @@ xf86PostScanZX1(void)
 	pPCI->devnum = i | 0x10;
      /* pPCI->funcnum = 0; */
 	pPCI->tag = PCI_MAKE_TAG(zx1_fakebus, pPCI->devnum, 0);
-	pPCI->pci_device_vendor = zx1_pciids[i];
+	pPCI->pci_device_vendor = DEVID(VENDOR_HP, CHIP_ZX1_LBA);
 	pPCI->pci_base_class = PCI_CLASS_BRIDGE;
 	pPCI->pci_sub_class = PCI_SUBCLASS_BRIDGE_PCI;
 	pPCI->pci_header_type = 1;
@@ -1090,9 +1032,6 @@ xf86PostScanZX1(void)
 	/* Plug in chipset routines */
 	pBusInfo->funcs = &zx1BusFuncs;
 
-	/* Set bridge control register for scanpci utility */
-	pPCI->pci_bridge_control = ControlZX1Bridge(zx1_busno[i], 0, 0);
-
 #ifdef OLD_FORMAT
 	xf86MsgVerb(X_INFO, 2, "PCI: BusID 0x%.2x,0x%02x,0x%1x "
 		    "ID 0x%04x,0x%04x Rev 0x%02x Class 0x%02x,0x%02x\n",