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-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/clk-u300.c718
-rw-r--r--drivers/clk/clk-zynq.c378
-rw-r--r--drivers/clk/mvebu/Kconfig25
-rw-r--r--drivers/clk/mvebu/Makefile8
-rw-r--r--drivers/clk/mvebu/armada-370.c176
-rw-r--r--drivers/clk/mvebu/armada-xp.c210
-rw-r--r--drivers/clk/mvebu/clk-core.c675
-rw-r--r--drivers/clk/mvebu/clk-core.h18
-rw-r--r--drivers/clk/mvebu/clk-gating-ctrl.c250
-rw-r--r--drivers/clk/mvebu/clk-gating-ctrl.h22
-rw-r--r--drivers/clk/mvebu/clk.c23
-rw-r--r--drivers/clk/mvebu/common.c163
-rw-r--r--drivers/clk/mvebu/common.h48
-rw-r--r--drivers/clk/mvebu/dove.c194
-rw-r--r--drivers/clk/mvebu/kirkwood.c247
-rw-r--r--drivers/clk/socfpga/clk.c194
-rw-r--r--drivers/clk/tegra/clk-tegra114.c23
-rw-r--r--drivers/clk/zynq/Makefile3
-rw-r--r--drivers/clk/zynq/clkc.c533
-rw-r--r--drivers/clk/zynq/pll.c235
21 files changed, 2626 insertions, 1519 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f0e46997bb12..f9cf7085ef70 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
-obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
+obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a15f7928fb11..8774e058cb6c 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,7 +11,349 @@
#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
-#include <mach/syscon.h>
+#include <linux/of.h>
+
+/* APP side SYSCON registers */
+/* CLK Control Register 16bit (R/W) */
+#define U300_SYSCON_CCR (0x0000)
+#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
+#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
+#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
+/* CLK Status Register 16bit (R/W) */
+#define U300_SYSCON_CSR (0x0004)
+#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
+#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
+/* Reset lines for SLOW devices 16bit (R/W) */
+#define U300_SYSCON_RSR (0x0014)
+#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
+#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
+#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
+#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
+#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
+#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
+#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
+#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
+#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
+#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
+/* Reset lines for FAST devices 16bit (R/W) */
+#define U300_SYSCON_RFR (0x0018)
+#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
+#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
+#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
+#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
+#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
+#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
+#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
+#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
+/* Reset lines for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_RRR (0x001c)
+#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
+#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
+#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
+#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
+#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
+#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
+#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
+#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
+#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
+#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
+#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
+#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
+#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
+/* Clock enable for SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CESR (0x0020)
+#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
+#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
+#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
+#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
+#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
+#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
+#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
+#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
+#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
+/* Clock enable for FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CEFR (0x0024)
+#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
+#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
+#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
+#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
+#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
+#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
+/* Clock enable for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CERR (0x0028)
+#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
+#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
+#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
+#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
+#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
+#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
+#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
+#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
+#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
+#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
+#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
+#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
+#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
+#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
+/* Single block clock enable 16bit (-/W) */
+#define U300_SYSCON_SBCER (0x002c)
+#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
+#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
+#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
+#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
+#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
+#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
+#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
+#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
+#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
+#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
+#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
+#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
+#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
+#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
+#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
+#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
+#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
+#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
+#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
+#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
+#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
+#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
+#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
+#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
+#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
+#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
+#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
+#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
+#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
+#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
+#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
+#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
+#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
+/* Single block clock disable 16bit (-/W) */
+#define U300_SYSCON_SBCDR (0x0030)
+/* Same values as above for SBCER */
+/* Clock force SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CFSR (0x003c)
+#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
+#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
+#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
+#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
+#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
+#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
+#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
+#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
+#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
+/* Clock force FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CFFR (0x40)
+/* Values not defined. Define if you want to use them. */
+/* Clock force the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CFRR (0x44)
+#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
+#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
+#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
+#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
+#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
+#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
+#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
+#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
+#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
+#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
+#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
+#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
+#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
+#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
+/* PLL208 Frequency Control 16bit (R/W) */
+#define U300_SYSCON_PFCR (0x48)
+#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
+/* Reset Out 16bit (R/W) */
+#define U300_SYSCON_RCR (0x6c)
+#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
+/* EMIF Slew Rate Control 16bit (R/W) */
+#define U300_SYSCON_SRCLR (0x70)
+#define U300_SYSCON_SRCLR_MASK (0x03FF)
+#define U300_SYSCON_SRCLR_VALUE (0x03FF)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
+/* EMIF Clock Control Register 16bit (R/W) */
+#define U300_SYSCON_ECCR (0x0078)
+#define U300_SYSCON_ECCR_MASK (0x000F)
+#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
+#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
+#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
+#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
+/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
+#define U300_SYSCON_MMF0R (0x90)
+#define U300_SYSCON_MMF0R_MASK (0x00FF)
+#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
+#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
+/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
+#define U300_SYSCON_MMF1R (0x94)
+#define U300_SYSCON_MMF1R_MASK (0x00FF)
+#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
+#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
+/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
+#define U300_SYSCON_MMCR (0x9C)
+#define U300_SYSCON_MMCR_MASK (0x0003)
+#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
+#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
+/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
+#define U300_SYSCON_S0CCR (0x120)
+#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
+#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
+#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
+#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
+#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
+#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
+#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
+#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
+#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
+/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
+#define U300_SYSCON_S1CCR (0x124)
+#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
+#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
+#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
+#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
+#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
+#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
+#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
+#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
+#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
+/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
+#define U300_SYSCON_S2CCR (0x128)
+#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
+#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
+#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
+#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
+#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
+#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
+#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
+#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
+/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
+#define U300_SYSCON_PICR (0x0130)
+#define U300_SYSCON_PICR_MASK (0x00FF)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
+/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
+#define U300_SYSCON_PISR (0x0134)
+#define U300_SYSCON_PISR_MASK (0x000F)
+#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
+#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
+#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
+#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
+/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
+#define U300_SYSCON_PICLR (0x0138)
+#define U300_SYSCON_PICLR_MASK (0x000F)
+#define U300_SYSCON_PICLR_RWMASK (0x0000)
+#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
+#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
+#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
+#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
+/* Clock activity observability register 0 */
+#define U300_SYSCON_C0OAR (0x140)
+#define U300_SYSCON_C0OAR_MASK (0xFFFF)
+#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
+#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
+#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
+#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
+#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
+#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
+#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
+#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
+#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
+#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
+#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
+#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
+#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
+#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
+#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
+#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
+#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
+/* Clock activity observability register 1 */
+#define U300_SYSCON_C1OAR (0x144)
+#define U300_SYSCON_C1OAR_MASK (0x3FFE)
+#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
+#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
+#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
+#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
+#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
+#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
+#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
+#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
+#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
+#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
+#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
+#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
+#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
+#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
+/* Clock activity observability register 2 */
+#define U300_SYSCON_C2OAR (0x148)
+#define U300_SYSCON_C2OAR_MASK (0x0FFF)
+#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
+#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
+#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
+#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
+#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
+#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
+#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
+#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
+#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
+
/*
* The clocking hierarchy currently looks like this.
@@ -386,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
return clk;
}
+#define U300_CLK_TYPE_SLOW 0
+#define U300_CLK_TYPE_FAST 1
+#define U300_CLK_TYPE_REST 2
+
+/**
+ * struct u300_clock - defines the bits and pieces for a certain clock
+ * @type: the clock type, slow fast or rest
+ * @id: the bit in the slow/fast/rest register for this clock
+ * @hw_ctrld: whether the clock is hardware controlled
+ * @clk_val: a value to poke in the one-write enable/disable registers
+ */
+struct u300_clock {
+ u8 type;
+ u8 id;
+ bool hw_ctrld;
+ u16 clk_val;
+};
+
+struct u300_clock const __initconst u300_clk_lookup[] = {
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 3,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 4,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 5,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 6,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 8,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 9,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 10,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_REST,
+ .id = 12,
+ .hw_ctrld = false,
+ /* INTCON: cannot be enabled, just taken out of reset */
+ .clk_val = 0xFFFFU,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 0,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 1,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 2,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 5,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_FAST,
+ .id = 6,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 0,
+ .hw_ctrld = true,
+ .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 1,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 4,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 6,
+ .hw_ctrld = true,
+ /* No clock enable register bit */
+ .clk_val = 0xFFFFU,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 7,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
+ },
+ {
+ .type = U300_CLK_TYPE_SLOW,
+ .id = 8,
+ .hw_ctrld = false,
+ .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
+ },
+};
+
+static void __init of_u300_syscon_clk_init(struct device_node *np)
+{
+ struct clk *clk = ERR_PTR(-EINVAL);
+ const char *clk_name = np->name;
+ const char *parent_name;
+ void __iomem *res_reg;
+ void __iomem *en_reg;
+ u32 clk_type;
+ u32 clk_id;
+ int i;
+
+ if (of_property_read_u32(np, "clock-type", &clk_type)) {
+ pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
+ __func__, clk_name);
+ return;
+ }
+ if (of_property_read_u32(np, "clock-id", &clk_id)) {
+ pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
+ __func__, clk_name);
+ return;
+ }
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ switch (clk_type) {
+ case U300_CLK_TYPE_SLOW:
+ res_reg = syscon_vbase + U300_SYSCON_RSR;
+ en_reg = syscon_vbase + U300_SYSCON_CESR;
+ break;
+ case U300_CLK_TYPE_FAST:
+ res_reg = syscon_vbase + U300_SYSCON_RFR;
+ en_reg = syscon_vbase + U300_SYSCON_CEFR;
+ break;
+ case U300_CLK_TYPE_REST:
+ res_reg = syscon_vbase + U300_SYSCON_RRR;
+ en_reg = syscon_vbase + U300_SYSCON_CERR;
+ break;
+ default:
+ pr_err("unknown clock type %x specified\n", clk_type);
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
+ const struct u300_clock *u3clk = &u300_clk_lookup[i];
+
+ if (u3clk->type == clk_type && u3clk->id == clk_id)
+ clk = syscon_clk_register(NULL,
+ clk_name, parent_name,
+ 0, u3clk->hw_ctrld,
+ res_reg, u3clk->id,
+ en_reg, u3clk->id,
+ u3clk->clk_val);
+ }
+
+ if (!IS_ERR(clk)) {
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+ /*
+ * Some few system clocks - device tree does not
+ * represent clocks without a corresponding device node.
+ * for now we add these three clocks here.
+ */
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
+ clk_register_clkdev(clk, NULL, "pl172");
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
+ clk_register_clkdev(clk, NULL, "semi");
+ if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
+ clk_register_clkdev(clk, NULL, "intcon");
+ }
+}
+
/**
* struct clk_mclk - U300 MCLK clock (MMC/SD clock)
* @hw: corresponding clock hardware entry
@@ -590,10 +1139,41 @@ mclk_clk_register(struct device *dev, const char *name,
return clk;
}
+static void __init of_u300_syscon_mclk_init(struct device_node *np)
+{
+ struct clk *clk = ERR_PTR(-EINVAL);
+ const char *clk_name = np->name;
+ const char *parent_name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ clk = mclk_clk_register(NULL, clk_name, parent_name, false);
+ if (!IS_ERR(clk))
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static const __initconst struct of_device_id u300_clk_match[] = {
+ {
+ .compatible = "fixed-clock",
+ .data = of_fixed_clk_setup,
+ },
+ {
+ .compatible = "fixed-factor-clock",
+ .data = of_fixed_factor_clk_setup,
+ },
+ {
+ .compatible = "stericsson,u300-syscon-clk",
+ .data = of_u300_syscon_clk_init,
+ },
+ {
+ .compatible = "stericsson,u300-syscon-mclk",
+ .data = of_u300_syscon_mclk_init,
+ },
+};
+
+
void __init u300_clk_init(void __iomem *base)
{
u16 val;
- struct clk *clk;
syscon_vbase = base;
@@ -610,137 +1190,5 @@ void __init u300_clk_init(void __iomem *base)
val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
writew(val, syscon_vbase + U300_SYSCON_PMCR);
- /* These are always available (RTC and PLL13) */
- clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
- CLK_IS_ROOT, 32768);
- /* The watchdog sits directly on the 32 kHz clock */
- clk_register_clkdev(clk, NULL, "coh901327_wdog");
- clk = clk_register_fixed_rate(NULL, "pll13", NULL,
- CLK_IS_ROOT, 13000000);
-
- /* These derive from PLL208 */
- clk = clk_register_fixed_rate(NULL, "pll208", NULL,
- CLK_IS_ROOT, 208000000);
- clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
- 0, 1, 1);
- clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
- 0, 1, 2);
- clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
- 0, 1, 4);
- /* The 52 MHz is divided down to 26 MHz */
- clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
- 0, 1, 2);
-
- /* Directly on the AMBA interconnect */
- clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 3,
- syscon_vbase + U300_SYSCON_CERR, 3,
- U300_SYSCON_SBCER_CPU_CLK_EN);
- clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 4,
- syscon_vbase + U300_SYSCON_CERR, 4,
- U300_SYSCON_SBCER_DMAC_CLK_EN);
- clk_register_clkdev(clk, NULL, "dma");
- clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 6,
- syscon_vbase + U300_SYSCON_CERR, 6,
- U300_SYSCON_SBCER_NANDIF_CLK_EN);
- clk_register_clkdev(clk, NULL, "fsmc-nand");
- clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 8,
- syscon_vbase + U300_SYSCON_CERR, 8,
- U300_SYSCON_SBCER_XGAM_CLK_EN);
- clk_register_clkdev(clk, NULL, "xgam");
- clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 9,
- syscon_vbase + U300_SYSCON_CERR, 9,
- U300_SYSCON_SBCER_SEMI_CLK_EN);
- clk_register_clkdev(clk, NULL, "semi");
-
- /* AHB bridge clocks */
- clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
- syscon_vbase + U300_SYSCON_RRR, 10,
- syscon_vbase + U300_SYSCON_CERR, 10,
- U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 12,
- syscon_vbase + U300_SYSCON_CERR, 12,
- /* Cannot be enabled, just taken out of reset */
- 0xFFFFU);
- clk_register_clkdev(clk, NULL, "intcon");
- clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
- syscon_vbase + U300_SYSCON_RRR, 5,
- syscon_vbase + U300_SYSCON_CERR, 5,
- U300_SYSCON_SBCER_EMIF_CLK_EN);
- clk_register_clkdev(clk, NULL, "pl172");
-
- /* FAST bridge clocks */
- clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
- syscon_vbase + U300_SYSCON_RFR, 0,
- syscon_vbase + U300_SYSCON_CEFR, 0,
- U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 1,
- syscon_vbase + U300_SYSCON_CEFR, 1,
- U300_SYSCON_SBCER_I2C0_CLK_EN);
- clk_register_clkdev(clk, NULL, "stu300.0");
- clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 2,
- syscon_vbase + U300_SYSCON_CEFR, 2,
- U300_SYSCON_SBCER_I2C1_CLK_EN);
- clk_register_clkdev(clk, NULL, "stu300.1");
- clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 5,
- syscon_vbase + U300_SYSCON_CEFR, 5,
- U300_SYSCON_SBCER_MMC_CLK_EN);
- clk_register_clkdev(clk, "apb_pclk", "mmci");
- clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
- syscon_vbase + U300_SYSCON_RFR, 6,
- syscon_vbase + U300_SYSCON_CEFR, 6,
- U300_SYSCON_SBCER_SPI_CLK_EN);
- /* The SPI has no external clock for the outward bus, uses the pclk */
- clk_register_clkdev(clk, NULL, "pl022");
- clk_register_clkdev(clk, "apb_pclk", "pl022");
-
- /* SLOW bridge clocks */
- clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
- syscon_vbase + U300_SYSCON_RSR, 0,
- syscon_vbase + U300_SYSCON_CESR, 0,
- U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
- clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 1,
- syscon_vbase + U300_SYSCON_CESR, 1,
- U300_SYSCON_SBCER_UART_CLK_EN);
- /* Same clock is used for APB and outward bus */
- clk_register_clkdev(clk, NULL, "uart0");
- clk_register_clkdev(clk, "apb_pclk", "uart0");
- clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 4,
- syscon_vbase + U300_SYSCON_CESR, 4,
- U300_SYSCON_SBCER_GPIO_CLK_EN);
- clk_register_clkdev(clk, NULL, "u300-gpio");
- clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 5,
- syscon_vbase + U300_SYSCON_CESR, 6,
- U300_SYSCON_SBCER_KEYPAD_CLK_EN);
- clk_register_clkdev(clk, NULL, "coh901461-keypad");
- clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
- syscon_vbase + U300_SYSCON_RSR, 6,
- /* No clock enable register bit */
- NULL, 0, 0xFFFFU);
- clk_register_clkdev(clk, NULL, "rtc-coh901331");
- clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 7,
- syscon_vbase + U300_SYSCON_CESR, 7,
- U300_SYSCON_SBCER_APP_TMR_CLK_EN);
- clk_register_clkdev(clk, NULL, "apptimer");
- clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
- syscon_vbase + U300_SYSCON_RSR, 8,
- syscon_vbase + U300_SYSCON_CESR, 8,
- U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
- clk_register_clkdev(clk, NULL, "timer");
-
- /* Then this special MMC/SD clock */
- clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
- clk_register_clkdev(clk, NULL, "mmci");
+ of_clk_init(u300_clk_match);
}
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c
deleted file mode 100644
index 32062977f453..000000000000
--- a/drivers/clk/clk-zynq.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright (c) 2012 National Instruments
- *
- * Josh Cartwright <josh.cartwright@ni.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/zynq.h>
-
-static void __iomem *slcr_base;
-
-struct zynq_pll_clk {
- struct clk_hw hw;
- void __iomem *pll_ctrl;
- void __iomem *pll_cfg;
-};
-
-#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw)
-
-#define CTRL_PLL_FDIV(x) ((x) >> 12)
-
-static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct zynq_pll_clk *pll = to_zynq_pll_clk(hw);
- return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl));
-}
-
-static const struct clk_ops zynq_pll_clk_ops = {
- .recalc_rate = zynq_pll_recalc_rate,
-};
-
-static void __init zynq_pll_clk_setup(struct device_node *np)
-{
- struct clk_init_data init;
- struct zynq_pll_clk *pll;
- const char *parent_name;
- struct clk *clk;
- u32 regs[2];
- int ret;
-
- ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs));
- if (WARN_ON(ret))
- return;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (WARN_ON(!pll))
- return;
-
- pll->pll_ctrl = slcr_base + regs[0];
- pll->pll_cfg = slcr_base + regs[1];
-
- of_property_read_string(np, "clock-output-names", &init.name);
-
- init.ops = &zynq_pll_clk_ops;
- parent_name = of_clk_get_parent_name(np, 0);
- init.parent_names = &parent_name;
- init.num_parents = 1;
-
- pll->hw.init = &init;
-
- clk = clk_register(NULL, &pll->hw);
- if (WARN_ON(IS_ERR(clk)))
- return;
-
- ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
- if (WARN_ON(ret))
- return;
-}
-CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup);
-
-struct zynq_periph_clk {
- struct clk_hw hw;
- struct clk_onecell_data onecell_data;
- struct clk *gates[2];
- void __iomem *clk_ctrl;
- spinlock_t clkact_lock;
-};
-
-#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw)
-
-static const u8 periph_clk_parent_map[] = {
- 0, 0, 1, 2
-};
-#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4])
-#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
-
-static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
- return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl));
-}
-
-static u8 zynq_periph_get_parent(struct clk_hw *hw)
-{
- struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
- return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl));
-}
-
-static const struct clk_ops zynq_periph_clk_ops = {
- .recalc_rate = zynq_periph_recalc_rate,
- .get_parent = zynq_periph_get_parent,
-};
-
-static void __init zynq_periph_clk_setup(struct device_node *np)
-{
- struct zynq_periph_clk *periph;
- const char *parent_names[3];
- struct clk_init_data init;
- int clk_num = 0, err;
- const char *name;
- struct clk *clk;
- u32 reg;
- int i;
-
- err = of_property_read_u32(np, "reg", &reg);
- if (WARN_ON(err))
- return;
-
- periph = kzalloc(sizeof(*periph), GFP_KERNEL);
- if (WARN_ON(!periph))
- return;
-
- periph->clk_ctrl = slcr_base + reg;
- spin_lock_init(&periph->clkact_lock);
-
- init.name = np->name;
- init.ops = &zynq_periph_clk_ops;
- for (i = 0; i < ARRAY_SIZE(parent_names); i++)
- parent_names[i] = of_clk_get_parent_name(np, i);
- init.parent_names = parent_names;
- init.num_parents = ARRAY_SIZE(parent_names);
-
- periph->hw.init = &init;
-
- clk = clk_register(NULL, &periph->hw);
- if (WARN_ON(IS_ERR(clk)))
- return;
-
- err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
- if (WARN_ON(err))
- return;
-
- err = of_property_read_string_index(np, "clock-output-names", 0,
- &name);
- if (WARN_ON(err))
- return;
-
- periph->gates[0] = clk_register_gate(NULL, name, np->name, 0,
- periph->clk_ctrl, 0, 0,
- &periph->clkact_lock);
- if (WARN_ON(IS_ERR(periph->gates[0])))
- return;
- clk_num++;
-
- /* some periph clks have 2 downstream gates */
- err = of_property_read_string_index(np, "clock-output-names", 1,
- &name);
- if (err != -ENODATA) {
- periph->gates[1] = clk_register_gate(NULL, name, np->name, 0,
- periph->clk_ctrl, 1, 0,
- &periph->clkact_lock);
- if (WARN_ON(IS_ERR(periph->gates[1])))
- return;
- clk_num++;
- }
-
- periph->onecell_data.clks = periph->gates;
- periph->onecell_data.clk_num = clk_num;
-
- err = of_clk_add_provider(np, of_clk_src_onecell_get,
- &periph->onecell_data);
- if (WARN_ON(err))
- return;
-}
-CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup);
-
-/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
- * derivative rates depend on CLK_621_TRUE
- */
-
-struct zynq_cpu_clk {
- struct clk_hw hw;
- struct clk_onecell_data onecell_data;
- struct clk *subclks[4];
- void __iomem *clk_ctrl;
- spinlock_t clkact_lock;
-};
-
-#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw)
-
-static const u8 zynq_cpu_clk_parent_map[] = {
- 1, 1, 2, 0
-};
-#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
-#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8)
-
-static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw)
-{
- struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
- return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl));
-}
-
-static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
- return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl));
-}
-
-static const struct clk_ops zynq_cpu_clk_ops = {
- .get_parent = zynq_cpu_clk_get_parent,
- .recalc_rate = zynq_cpu_clk_recalc_rate,
-};
-
-struct zynq_cpu_subclk {
- struct clk_hw hw;
- void __iomem *clk_621;
- enum {
- CPU_SUBCLK_6X4X,
- CPU_SUBCLK_3X2X,
- CPU_SUBCLK_2X,
- CPU_SUBCLK_1X,
- } which;
-};
-
-#define CLK_621_TRUE(x) ((x) & 1)
-
-#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw);
-
-static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- unsigned long uninitialized_var(rate);
- struct zynq_cpu_subclk *subclk;
- bool is_621;
-
- subclk = to_zynq_cpu_subclk(hw)
- is_621 = CLK_621_TRUE(ioread32(subclk->clk_621));
-
- switch (subclk->which) {
- case CPU_SUBCLK_6X4X:
- rate = parent_rate;
- break;
- case CPU_SUBCLK_3X2X:
- rate = parent_rate / 2;
- break;
- case CPU_SUBCLK_2X:
- rate = parent_rate / (is_621 ? 3 : 2);
- break;
- case CPU_SUBCLK_1X:
- rate = parent_rate / (is_621 ? 6 : 4);
- break;
- };
-
- return rate;
-}
-
-static const struct clk_ops zynq_cpu_subclk_ops = {
- .recalc_rate = zynq_cpu_subclk_recalc_rate,
-};
-
-static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which,
- void __iomem *clk_621)
-{
- struct zynq_cpu_subclk *subclk;
- struct clk_init_data init;
- struct clk *clk;
- int err;
-
- err = of_property_read_string_index(np, "clock-output-names",
- which, &init.name);
- if (WARN_ON(err))
- goto err_read_output_name;
-
- subclk = kzalloc(sizeof(*subclk), GFP_KERNEL);
- if (!subclk)
- goto err_subclk_alloc;
-
- subclk->clk_621 = clk_621;
- subclk->which = which;
-
- init.ops = &zynq_cpu_subclk_ops;
- init.parent_names = &np->name;
- init.num_parents = 1;
-
- subclk->hw.init = &init;
-
- clk = clk_register(NULL, &subclk->hw);
- if (WARN_ON(IS_ERR(clk)))
- goto err_clk_register;
-
- return clk;
-
-err_clk_register:
- kfree(subclk);
-err_subclk_alloc:
-err_read_output_name:
- return ERR_PTR(-EINVAL);
-}
-
-static void __init zynq_cpu_clk_setup(struct device_node *np)
-{
- struct zynq_cpu_clk *cpuclk;
- const char *parent_names[3];
- struct clk_init_data init;
- void __iomem *clk_621;
- struct clk *clk;
- u32 reg[2];
- int err;
- int i;
-
- err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
- if (WARN_ON(err))
- return;
-
- cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
- if (WARN_ON(!cpuclk))
- return;
-
- cpuclk->clk_ctrl = slcr_base + reg[0];
- clk_621 = slcr_base + reg[1];
- spin_lock_init(&cpuclk->clkact_lock);
-
- init.name = np->name;
- init.ops = &zynq_cpu_clk_ops;
- for (i = 0; i < ARRAY_SIZE(parent_names); i++)
- parent_names[i] = of_clk_get_parent_name(np, i);
- init.parent_names = parent_names;
- init.num_parents = ARRAY_SIZE(parent_names);
-
- cpuclk->hw.init = &init;
-
- clk = clk_register(NULL, &cpuclk->hw);
- if (WARN_ON(IS_ERR(clk)))
- return;
-
- err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
- if (WARN_ON(err))
- return;
-
- for (i = 0; i < 4; i++) {
- cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621);
- if (WARN_ON(IS_ERR(cpuclk->subclks[i])))
- return;
- }
-
- cpuclk->onecell_data.clks = cpuclk->subclks;
- cpuclk->onecell_data.clk_num = i;
-
- err = of_clk_add_provider(np, of_clk_src_onecell_get,
- &cpuclk->onecell_data);
- if (WARN_ON(err))
- return;
-}
-CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup);
-
-void __init xilinx_zynq_clocks_init(void __iomem *slcr)
-{
- slcr_base = slcr;
- of_clk_init(NULL);
-}
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 57323fd15ec9..0b0f3e729cf7 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -1,8 +1,23 @@
-config MVEBU_CLK_CORE
- bool
+config MVEBU_CLK_COMMON
+ bool
config MVEBU_CLK_CPU
- bool
+ bool
-config MVEBU_CLK_GATING
- bool
+config ARMADA_370_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
+config ARMADA_XP_CLK
+ bool
+ select MVEBU_CLK_COMMON
+ select MVEBU_CLK_CPU
+
+config DOVE_CLK
+ bool
+ select MVEBU_CLK_COMMON
+
+config KIRKWOOD_CLK
+ bool
+ select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 58df3dc49363..1c7e70c63fb2 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,3 +1,7 @@
-obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o
+obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
-obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o
+
+obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
+obj-$(CONFIG_DOVE_CLK) += dove.o
+obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 000000000000..079960e7c304
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_A370_PCLK_FREQ_OPT 11
+#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
+#define SARL_A370_FAB_FREQ_OPT 15
+#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
+#define SARL_A370_TCLK_FREQ_OPT 20
+#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+ { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = A370_CPU_TO_HCLK, .name = "hclk" },
+ { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+ 16600000,
+ 20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+ u8 tclk_freq_select = 0;
+
+ tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+ SARL_A370_TCLK_FREQ_OPT_MASK);
+ return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+ 400000000,
+ 533000000,
+ 667000000,
+ 800000000,
+ 1000000000,
+ 1067000000,
+ 1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+ SARL_A370_PCLK_FREQ_OPT_MASK);
+ if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+ pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+ SARL_A370_FAB_FREQ_OPT_MASK);
+
+ switch (id) {
+ case A370_CPU_TO_NBCLK:
+ *mult = a370_nbclk_ratios[opt][0];
+ *div = a370_nbclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_HCLK:
+ *mult = a370_hclk_ratios[opt][0];
+ *div = a370_hclk_ratios[opt][1];
+ break;
+ case A370_CPU_TO_DRAMCLK:
+ *mult = a370_dramclk_ratios[opt][0];
+ *div = a370_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+ .get_tclk_freq = a370_get_tclk_freq,
+ .get_cpu_freq = a370_get_cpu_freq,
+ .get_clk_ratio = a370_get_clk_ratio,
+ .ratios = a370_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+ a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "pex0_en", NULL, 1, 0 },
+ { "pex1_en", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex0", "pex0_en", 5, 0 },
+ { "pex1", "pex1_en", 9, 0 },
+ { "sata0", NULL, 15, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+ { "sata1", NULL, 30, 0 },
+ { }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+ a370_clk_gating_init);
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 000000000000..13b62ceb3407
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,210 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL 0 /* Low part [0:31] */
+#define SARL_AXP_PCLK_FREQ_OPT 21
+#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
+#define SARL_AXP_FAB_FREQ_OPT 24
+#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
+#define SARH 4 /* High part [32:63] */
+#define SARH_AXP_PCLK_FREQ_OPT (52-32)
+#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
+#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
+#define SARH_AXP_FAB_FREQ_OPT (51-32)
+#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
+#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+ { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+ { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+ { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+ return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+ 1000000000,
+ 1066000000,
+ 1200000000,
+ 1333000000,
+ 1500000000,
+ 1666000000,
+ 1800000000,
+ 2000000000,
+ 667000000,
+ 0,
+ 800000000,
+ 1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+ u32 cpu_freq;
+ u8 cpu_freq_select = 0;
+
+ cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+ SARL_AXP_PCLK_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+ SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+ if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+ pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+ cpu_freq = 0;
+ } else
+ cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+ return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 2}, {2, 2},
+ {1, 2}, {1, 2}, {1, 1}, {2, 3},
+ {0, 1}, {1, 2}, {2, 4}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {2, 2},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 6}, {2, 3},
+ {1, 3}, {1, 4}, {1, 2}, {2, 6},
+ {0, 1}, {1, 6}, {2, 10}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 2},
+ {2, 6}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+ {0, 1}, {1, 2}, {2, 3}, {2, 3},
+ {1, 3}, {1, 2}, {1, 2}, {2, 6},
+ {0, 1}, {1, 3}, {2, 5}, {0, 1},
+ {1, 4}, {0, 1}, {0, 1}, {2, 5},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {2, 3}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {1, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+ SARL_AXP_FAB_FREQ_OPT_MASK);
+ /*
+ * The upper bit is not contiguous to the other ones and
+ * located in the high part of the SAR registers
+ */
+ opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+ SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+ switch (id) {
+ case AXP_CPU_TO_NBCLK:
+ *mult = axp_nbclk_ratios[opt][0];
+ *div = axp_nbclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_HCLK:
+ *mult = axp_hclk_ratios[opt][0];
+ *div = axp_hclk_ratios[opt][1];
+ break;
+ case AXP_CPU_TO_DRAMCLK:
+ *mult = axp_dramclk_ratios[opt][0];
+ *div = axp_dramclk_ratios[opt][1];
+ break;
+ }
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+ .get_tclk_freq = axp_get_tclk_freq,
+ .get_cpu_freq = axp_get_cpu_freq,
+ .get_clk_ratio = axp_get_clk_ratio,
+ .ratios = axp_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+ axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+ { "audio", NULL, 0, 0 },
+ { "ge3", NULL, 1, 0 },
+ { "ge2", NULL, 2, 0 },
+ { "ge1", NULL, 3, 0 },
+ { "ge0", NULL, 4, 0 },
+ { "pex00", NULL, 5, 0 },
+ { "pex01", NULL, 6, 0 },
+ { "pex02", NULL, 7, 0 },
+ { "pex03", NULL, 8, 0 },
+ { "pex10", NULL, 9, 0 },
+ { "pex11", NULL, 10, 0 },
+ { "pex12", NULL, 11, 0 },
+ { "pex13", NULL, 12, 0 },
+ { "bp", NULL, 13, 0 },
+ { "sata0lnk", NULL, 14, 0 },
+ { "sata0", "sata0lnk", 15, 0 },
+ { "lcd", NULL, 16, 0 },
+ { "sdio", NULL, 17, 0 },
+ { "usb0", NULL, 18, 0 },
+ { "usb1", NULL, 19, 0 },
+ { "usb2", NULL, 20, 0 },
+ { "xor0", NULL, 22, 0 },
+ { "crypto", NULL, 23, 0 },
+ { "tdm", NULL, 25, 0 },
+ { "pex20", NULL, 26, 0 },
+ { "pex30", NULL, 27, 0 },
+ { "xor1", NULL, 28, 0 },
+ { "sata1lnk", NULL, 29, 0 },
+ { "sata1", "sata1lnk", 30, 0 },
+ { }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+ axp_clk_gating_init);
diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
deleted file mode 100644
index 0a53edbae8b8..000000000000
--- a/drivers/clk/mvebu/clk-core.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include "clk-core.h"
-
-struct core_ratio {
- int id;
- const char *name;
-};
-
-struct core_clocks {
- u32 (*get_tclk_freq)(void __iomem *sar);
- u32 (*get_cpu_freq)(void __iomem *sar);
- void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
- const struct core_ratio *ratios;
- int num_ratios;
-};
-
-static struct clk_onecell_data clk_data;
-
-static void __init mvebu_clk_core_setup(struct device_node *np,
- struct core_clocks *coreclk)
-{
- const char *tclk_name = "tclk";
- const char *cpuclk_name = "cpuclk";
- void __iomem *base;
- unsigned long rate;
- int n;
-
- base = of_iomap(np, 0);
- if (WARN_ON(!base))
- return;
-
- /*
- * Allocate struct for TCLK, cpu clk, and core ratio clocks
- */
- clk_data.clk_num = 2 + coreclk->num_ratios;
- clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
- GFP_KERNEL);
- if (WARN_ON(!clk_data.clks))
- return;
-
- /*
- * Register TCLK
- */
- of_property_read_string_index(np, "clock-output-names", 0,
- &tclk_name);
- rate = coreclk->get_tclk_freq(base);
- clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
- CLK_IS_ROOT, rate);
- WARN_ON(IS_ERR(clk_data.clks[0]));
-
- /*
- * Register CPU clock
- */
- of_property_read_string_index(np, "clock-output-names", 1,
- &cpuclk_name);
- rate = coreclk->get_cpu_freq(base);
- clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
- CLK_IS_ROOT, rate);
- WARN_ON(IS_ERR(clk_data.clks[1]));
-
- /*
- * Register fixed-factor clocks derived from CPU clock
- */
- for (n = 0; n < coreclk->num_ratios; n++) {
- const char *rclk_name = coreclk->ratios[n].name;
- int mult, div;
-
- of_property_read_string_index(np, "clock-output-names",
- 2+n, &rclk_name);
- coreclk->get_clk_ratio(base, coreclk->ratios[n].id,
- &mult, &div);
- clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
- cpuclk_name, 0, mult, div);
- WARN_ON(IS_ERR(clk_data.clks[2+n]));
- };
-
- /*
- * SAR register isn't needed anymore
- */
- iounmap(base);
-
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-
-#ifdef CONFIG_MACH_ARMADA_370_XP
-/*
- * Armada 370/XP Sample At Reset is a 64 bit bitfiled split in two
- * register of 32 bits
- */
-
-#define SARL 0 /* Low part [0:31] */
-#define SARL_AXP_PCLK_FREQ_OPT 21
-#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
-#define SARL_A370_PCLK_FREQ_OPT 11
-#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF
-#define SARL_AXP_FAB_FREQ_OPT 24
-#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
-#define SARL_A370_FAB_FREQ_OPT 15
-#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F
-#define SARL_A370_TCLK_FREQ_OPT 20
-#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1
-#define SARH 4 /* High part [32:63] */
-#define SARH_AXP_PCLK_FREQ_OPT (52-32)
-#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
-#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
-#define SARH_AXP_FAB_FREQ_OPT (51-32)
-#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
-#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
-
-static const u32 __initconst armada_370_tclk_frequencies[] = {
- 16600000,
- 20000000,
-};
-
-static u32 __init armada_370_get_tclk_freq(void __iomem *sar)
-{
- u8 tclk_freq_select = 0;
-
- tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
- SARL_A370_TCLK_FREQ_OPT_MASK);
- return armada_370_tclk_frequencies[tclk_freq_select];
-}
-
-static const u32 __initconst armada_370_cpu_frequencies[] = {
- 400000000,
- 533000000,
- 667000000,
- 800000000,
- 1000000000,
- 1067000000,
- 1200000000,
-};
-
-static u32 __init armada_370_get_cpu_freq(void __iomem *sar)
-{
- u32 cpu_freq;
- u8 cpu_freq_select = 0;
-
- cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
- SARL_A370_PCLK_FREQ_OPT_MASK);
- if (cpu_freq_select >= ARRAY_SIZE(armada_370_cpu_frequencies)) {
- pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
- cpu_freq = 0;
- } else
- cpu_freq = armada_370_cpu_frequencies[cpu_freq_select];
-
- return cpu_freq;
-}
-
-enum { A370_XP_NBCLK, A370_XP_HCLK, A370_XP_DRAMCLK };
-
-static const struct core_ratio __initconst armada_370_xp_core_ratios[] = {
- { .id = A370_XP_NBCLK, .name = "nbclk" },
- { .id = A370_XP_HCLK, .name = "hclk" },
- { .id = A370_XP_DRAMCLK, .name = "dramclk" },
-};
-
-static const int __initconst armada_370_xp_nbclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 2}, {2, 2},
- {1, 2}, {1, 2}, {1, 1}, {2, 3},
- {0, 1}, {1, 2}, {2, 4}, {0, 1},
- {1, 2}, {0, 1}, {0, 1}, {2, 2},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {2, 3}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_hclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 6}, {2, 3},
- {1, 3}, {1, 4}, {1, 2}, {2, 6},
- {0, 1}, {1, 6}, {2, 10}, {0, 1},
- {1, 4}, {0, 1}, {0, 1}, {2, 5},
- {0, 1}, {0, 1}, {0, 1}, {1, 2},
- {2, 6}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_dramclk_ratios[32][2] = {
- {0, 1}, {1, 2}, {2, 3}, {2, 3},
- {1, 3}, {1, 2}, {1, 2}, {2, 6},
- {0, 1}, {1, 3}, {2, 5}, {0, 1},
- {1, 4}, {0, 1}, {0, 1}, {2, 5},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {2, 3}, {0, 1}, {0, 1}, {0, 1},
- {0, 1}, {0, 1}, {0, 1}, {1, 1},
- {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static void __init armada_370_xp_get_clk_ratio(u32 opt,
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case A370_XP_NBCLK:
- *mult = armada_370_xp_nbclk_ratios[opt][0];
- *div = armada_370_xp_nbclk_ratios[opt][1];
- break;
- case A370_XP_HCLK:
- *mult = armada_370_xp_hclk_ratios[opt][0];
- *div = armada_370_xp_hclk_ratios[opt][1];
- break;
- case A370_XP_DRAMCLK:
- *mult = armada_370_xp_dramclk_ratios[opt][0];
- *div = armada_370_xp_dramclk_ratios[opt][1];
- break;
- }
-}
-
-static void __init armada_370_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
- SARL_A370_FAB_FREQ_OPT_MASK);
-
- armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-
-static const struct core_clocks armada_370_core_clocks = {
- .get_tclk_freq = armada_370_get_tclk_freq,
- .get_cpu_freq = armada_370_get_cpu_freq,
- .get_clk_ratio = armada_370_get_clk_ratio,
- .ratios = armada_370_xp_core_ratios,
- .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-static const u32 __initconst armada_xp_cpu_frequencies[] = {
- 1000000000,
- 1066000000,
- 1200000000,
- 1333000000,
- 1500000000,
- 1666000000,
- 1800000000,
- 2000000000,
- 667000000,
- 0,
- 800000000,
- 1600000000,
-};
-
-/* For Armada XP TCLK frequency is fix: 250MHz */
-static u32 __init armada_xp_get_tclk_freq(void __iomem *sar)
-{
- return 250 * 1000 * 1000;
-}
-
-static u32 __init armada_xp_get_cpu_freq(void __iomem *sar)
-{
- u32 cpu_freq;
- u8 cpu_freq_select = 0;
-
- cpu_freq_select = ((readl(sar) >> SARL_AXP_PCLK_FREQ_OPT) &
- SARL_AXP_PCLK_FREQ_OPT_MASK);
- /*
- * The upper bit is not contiguous to the other ones and
- * located in the high part of the SAR registers
- */
- cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) &
- SARH_AXP_PCLK_FREQ_OPT_MASK)
- << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
- if (cpu_freq_select >= ARRAY_SIZE(armada_xp_cpu_frequencies)) {
- pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
- cpu_freq = 0;
- } else
- cpu_freq = armada_xp_cpu_frequencies[cpu_freq_select];
-
- return cpu_freq;
-}
-
-static void __init armada_xp_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
-
- u32 opt = ((readl(sar) >> SARL_AXP_FAB_FREQ_OPT) &
- SARL_AXP_FAB_FREQ_OPT_MASK);
- /*
- * The upper bit is not contiguous to the other ones and
- * located in the high part of the SAR registers
- */
- opt |= (((readl(sar+4) >> SARH_AXP_FAB_FREQ_OPT) &
- SARH_AXP_FAB_FREQ_OPT_MASK)
- << SARH_AXP_FAB_FREQ_OPT_SHIFT);
-
- armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-static const struct core_clocks armada_xp_core_clocks = {
- .get_tclk_freq = armada_xp_get_tclk_freq,
- .get_cpu_freq = armada_xp_get_cpu_freq,
- .get_clk_ratio = armada_xp_get_clk_ratio,
- .ratios = armada_370_xp_core_ratios,
- .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-#endif /* CONFIG_MACH_ARMADA_370_XP */
-
-/*
- * Dove PLL sample-at-reset configuration
- *
- * SAR0[8:5] : CPU frequency
- * 5 = 1000 MHz
- * 6 = 933 MHz
- * 7 = 933 MHz
- * 8 = 800 MHz
- * 9 = 800 MHz
- * 10 = 800 MHz
- * 11 = 1067 MHz
- * 12 = 667 MHz
- * 13 = 533 MHz
- * 14 = 400 MHz
- * 15 = 333 MHz
- * others reserved.
- *
- * SAR0[11:9] : CPU to L2 Clock divider ratio
- * 0 = (1/1) * CPU
- * 2 = (1/2) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * others reserved.
- *
- * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
- * 0 = (1/1) * CPU
- * 2 = (1/2) * CPU
- * 3 = (2/5) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * 8 = (1/5) * CPU
- * 10 = (1/6) * CPU
- * 12 = (1/7) * CPU
- * 14 = (1/8) * CPU
- * 15 = (1/10) * CPU
- * others reserved.
- *
- * SAR0[24:23] : TCLK frequency
- * 0 = 166 MHz
- * 1 = 125 MHz
- * others reserved.
- */
-#ifdef CONFIG_ARCH_DOVE
-#define SAR_DOVE_CPU_FREQ 5
-#define SAR_DOVE_CPU_FREQ_MASK 0xf
-#define SAR_DOVE_L2_RATIO 9
-#define SAR_DOVE_L2_RATIO_MASK 0x7
-#define SAR_DOVE_DDR_RATIO 12
-#define SAR_DOVE_DDR_RATIO_MASK 0xf
-#define SAR_DOVE_TCLK_FREQ 23
-#define SAR_DOVE_TCLK_FREQ_MASK 0x3
-
-static const u32 __initconst dove_tclk_frequencies[] = {
- 166666667,
- 125000000,
- 0, 0
-};
-
-static u32 __init dove_get_tclk_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
- SAR_DOVE_TCLK_FREQ_MASK;
- return dove_tclk_frequencies[opt];
-}
-
-static const u32 __initconst dove_cpu_frequencies[] = {
- 0, 0, 0, 0, 0,
- 1000000000,
- 933333333, 933333333,
- 800000000, 800000000, 800000000,
- 1066666667,
- 666666667,
- 533333333,
- 400000000,
- 333333333
-};
-
-static u32 __init dove_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
- SAR_DOVE_CPU_FREQ_MASK;
- return dove_cpu_frequencies[opt];
-}
-
-enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
-
-static const struct core_ratio __initconst dove_core_ratios[] = {
- { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
- { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static const int __initconst dove_cpu_l2_ratios[8][2] = {
- { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
-};
-
-static const int __initconst dove_cpu_ddr_ratios[16][2] = {
- { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
- { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
- { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
-};
-
-static void __init dove_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case DOVE_CPU_TO_L2:
- {
- u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
- SAR_DOVE_L2_RATIO_MASK;
- *mult = dove_cpu_l2_ratios[opt][0];
- *div = dove_cpu_l2_ratios[opt][1];
- break;
- }
- case DOVE_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
- SAR_DOVE_DDR_RATIO_MASK;
- *mult = dove_cpu_ddr_ratios[opt][0];
- *div = dove_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks dove_core_clocks = {
- .get_tclk_freq = dove_get_tclk_freq,
- .get_cpu_freq = dove_get_cpu_freq,
- .get_clk_ratio = dove_get_clk_ratio,
- .ratios = dove_core_ratios,
- .num_ratios = ARRAY_SIZE(dove_core_ratios),
-};
-#endif /* CONFIG_ARCH_DOVE */
-
-/*
- * Kirkwood PLL sample-at-reset configuration
- * (6180 has different SAR layout than other Kirkwood SoCs)
- *
- * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
- * 4 = 600 MHz
- * 6 = 800 MHz
- * 7 = 1000 MHz
- * 9 = 1200 MHz
- * 12 = 1500 MHz
- * 13 = 1600 MHz
- * 14 = 1800 MHz
- * 15 = 2000 MHz
- * others reserved.
- *
- * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
- * 1 = (1/2) * CPU
- * 3 = (1/3) * CPU
- * 5 = (1/4) * CPU
- * others reserved.
- *
- * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
- * 2 = (1/2) * CPU
- * 4 = (1/3) * CPU
- * 6 = (1/4) * CPU
- * 7 = (2/9) * CPU
- * 8 = (1/5) * CPU
- * 9 = (1/6) * CPU
- * others reserved.
- *
- * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
- * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
- * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
- * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
- * others reserved.
- *
- * SAR0[21] : TCLK frequency
- * 0 = 200 MHz
- * 1 = 166 MHz
- * others reserved.
- */
-#ifdef CONFIG_ARCH_KIRKWOOD
-#define SAR_KIRKWOOD_CPU_FREQ(x) \
- (((x & (1 << 1)) >> 1) | \
- ((x & (1 << 22)) >> 21) | \
- ((x & (3 << 3)) >> 1))
-#define SAR_KIRKWOOD_L2_RATIO(x) \
- (((x & (3 << 9)) >> 9) | \
- (((x & (1 << 19)) >> 17)))
-#define SAR_KIRKWOOD_DDR_RATIO 5
-#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
-#define SAR_MV88F6180_CLK 2
-#define SAR_MV88F6180_CLK_MASK 0x7
-#define SAR_KIRKWOOD_TCLK_FREQ 21
-#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
-
-enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
-
-static const struct core_ratio __initconst kirkwood_core_ratios[] = {
- { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
- { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
- SAR_KIRKWOOD_TCLK_FREQ_MASK;
- return (opt) ? 166666667 : 200000000;
-}
-
-static const u32 __initconst kirkwood_cpu_frequencies[] = {
- 0, 0, 0, 0,
- 600000000,
- 0,
- 800000000,
- 1000000000,
- 0,
- 1200000000,
- 0, 0,
- 1500000000,
- 1600000000,
- 1800000000,
- 2000000000
-};
-
-static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
- return kirkwood_cpu_frequencies[opt];
-}
-
-static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
- { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
- { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
-};
-
-static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
- { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
- { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
- { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
- { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
-};
-
-static void __init kirkwood_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case KIRKWOOD_CPU_TO_L2:
- {
- u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
- *mult = kirkwood_cpu_l2_ratios[opt][0];
- *div = kirkwood_cpu_l2_ratios[opt][1];
- break;
- }
- case KIRKWOOD_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
- SAR_KIRKWOOD_DDR_RATIO_MASK;
- *mult = kirkwood_cpu_ddr_ratios[opt][0];
- *div = kirkwood_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks kirkwood_core_clocks = {
- .get_tclk_freq = kirkwood_get_tclk_freq,
- .get_cpu_freq = kirkwood_get_cpu_freq,
- .get_clk_ratio = kirkwood_get_clk_ratio,
- .ratios = kirkwood_core_ratios,
- .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-
-static const u32 __initconst mv88f6180_cpu_frequencies[] = {
- 0, 0, 0, 0, 0,
- 600000000,
- 800000000,
- 1000000000
-};
-
-static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
-{
- u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
- return mv88f6180_cpu_frequencies[opt];
-}
-
-static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
- { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
- { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
-};
-
-static void __init mv88f6180_get_clk_ratio(
- void __iomem *sar, int id, int *mult, int *div)
-{
- switch (id) {
- case KIRKWOOD_CPU_TO_L2:
- {
- /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
- *mult = 1;
- *div = 2;
- break;
- }
- case KIRKWOOD_CPU_TO_DDR:
- {
- u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
- SAR_MV88F6180_CLK_MASK;
- *mult = mv88f6180_cpu_ddr_ratios[opt][0];
- *div = mv88f6180_cpu_ddr_ratios[opt][1];
- break;
- }
- }
-}
-
-static const struct core_clocks mv88f6180_core_clocks = {
- .get_tclk_freq = kirkwood_get_tclk_freq,
- .get_cpu_freq = mv88f6180_get_cpu_freq,
- .get_clk_ratio = mv88f6180_get_clk_ratio,
- .ratios = kirkwood_core_ratios,
- .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-#endif /* CONFIG_ARCH_KIRKWOOD */
-
-static const __initdata struct of_device_id clk_core_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370_XP
- {
- .compatible = "marvell,armada-370-core-clock",
- .data = &armada_370_core_clocks,
- },
- {
- .compatible = "marvell,armada-xp-core-clock",
- .data = &armada_xp_core_clocks,
- },
-#endif
-#ifdef CONFIG_ARCH_DOVE
- {
- .compatible = "marvell,dove-core-clock",
- .data = &dove_core_clocks,
- },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
- {
- .compatible = "marvell,kirkwood-core-clock",
- .data = &kirkwood_core_clocks,
- },
- {
- .compatible = "marvell,mv88f6180-core-clock",
- .data = &mv88f6180_core_clocks,
- },
-#endif
-
- { }
-};
-
-void __init mvebu_core_clk_init(void)
-{
- struct device_node *np;
-
- for_each_matching_node(np, clk_core_match) {
- const struct of_device_id *match =
- of_match_node(clk_core_match, np);
- mvebu_clk_core_setup(np, (struct core_clocks *)match->data);
- }
-}
diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
deleted file mode 100644
index 28b5e02e9885..000000000000
--- a/drivers/clk/mvebu/clk-core.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_CORE_H
-#define __MVEBU_CLK_CORE_H
-
-void __init mvebu_core_clk_init(void);
-
-#endif
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
deleted file mode 100644
index ebf141d4374b..000000000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * Marvell MVEBU clock gating control.
- *
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-struct mvebu_gating_ctrl {
- spinlock_t lock;
- struct clk **gates;
- int num_gates;
-};
-
-struct mvebu_soc_descr {
- const char *name;
- const char *parent;
- int bit_idx;
-};
-
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
-static struct clk *mvebu_clk_gating_get_src(
- struct of_phandle_args *clkspec, void *data)
-{
- struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
- int n;
-
- if (clkspec->args_count < 1)
- return ERR_PTR(-EINVAL);
-
- for (n = 0; n < ctrl->num_gates; n++) {
- struct clk_gate *gate =
- to_clk_gate(__clk_get_hw(ctrl->gates[n]));
- if (clkspec->args[0] == gate->bit_idx)
- return ctrl->gates[n];
- }
- return ERR_PTR(-ENODEV);
-}
-
-static void __init mvebu_clk_gating_setup(
- struct device_node *np, const struct mvebu_soc_descr *descr)
-{
- struct mvebu_gating_ctrl *ctrl;
- struct clk *clk;
- void __iomem *base;
- const char *default_parent = NULL;
- int n;
-
- base = of_iomap(np, 0);
-
- clk = of_clk_get(np, 0);
- if (!IS_ERR(clk)) {
- default_parent = __clk_get_name(clk);
- clk_put(clk);
- }
-
- ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL);
- if (WARN_ON(!ctrl))
- return;
-
- spin_lock_init(&ctrl->lock);
-
- /*
- * Count, allocate, and register clock gates
- */
- for (n = 0; descr[n].name;)
- n++;
-
- ctrl->num_gates = n;
- ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
- GFP_KERNEL);
- if (WARN_ON(!ctrl->gates)) {
- kfree(ctrl);
- return;
- }
-
- for (n = 0; n < ctrl->num_gates; n++) {
- u8 flags = 0;
- const char *parent =
- (descr[n].parent) ? descr[n].parent : default_parent;
-
- /*
- * On Armada 370, the DDR clock is a special case: it
- * isn't taken by any driver, but should anyway be
- * kept enabled, so we mark it as IGNORE_UNUSED for
- * now.
- */
- if (!strcmp(descr[n].name, "ddr"))
- flags |= CLK_IGNORE_UNUSED;
-
- ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
- flags, base, descr[n].bit_idx, 0, &ctrl->lock);
- WARN_ON(IS_ERR(ctrl->gates[n]));
- }
- of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
-}
-
-/*
- * SoC specific clock gating control
- */
-
-#ifdef CONFIG_MACH_ARMADA_370
-static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
- { "audio", NULL, 0 },
- { "pex0_en", NULL, 1 },
- { "pex1_en", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", NULL, 5 },
- { "pex1", NULL, 9 },
- { "sata0", NULL, 15 },
- { "sdio", NULL, 17 },
- { "tdm", NULL, 25 },
- { "ddr", NULL, 28 },
- { "sata1", NULL, 30 },
- { }
-};
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
- { "audio", NULL, 0 },
- { "ge3", NULL, 1 },
- { "ge2", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", NULL, 5 },
- { "pex1", NULL, 6 },
- { "pex2", NULL, 7 },
- { "pex3", NULL, 8 },
- { "bp", NULL, 13 },
- { "sata0lnk", NULL, 14 },
- { "sata0", "sata0lnk", 15 },
- { "lcd", NULL, 16 },
- { "sdio", NULL, 17 },
- { "usb0", NULL, 18 },
- { "usb1", NULL, 19 },
- { "usb2", NULL, 20 },
- { "xor0", NULL, 22 },
- { "crypto", NULL, 23 },
- { "tdm", NULL, 25 },
- { "xor1", NULL, 28 },
- { "sata1lnk", NULL, 29 },
- { "sata1", "sata1lnk", 30 },
- { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
- { "usb0", NULL, 0 },
- { "usb1", NULL, 1 },
- { "ge", "gephy", 2 },
- { "sata", NULL, 3 },
- { "pex0", NULL, 4 },
- { "pex1", NULL, 5 },
- { "sdio0", NULL, 8 },
- { "sdio1", NULL, 9 },
- { "nand", NULL, 10 },
- { "camera", NULL, 11 },
- { "i2s0", NULL, 12 },
- { "i2s1", NULL, 13 },
- { "crypto", NULL, 15 },
- { "ac97", NULL, 21 },
- { "pdma", NULL, 22 },
- { "xor0", NULL, 23 },
- { "xor1", NULL, 24 },
- { "gephy", NULL, 30 },
- { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
- { "ge0", NULL, 0 },
- { "pex0", NULL, 2 },
- { "usb0", NULL, 3 },
- { "sdio", NULL, 4 },
- { "tsu", NULL, 5 },
- { "runit", NULL, 7 },
- { "xor0", NULL, 8 },
- { "audio", NULL, 9 },
- { "powersave", "cpuclk", 11 },
- { "sata0", NULL, 14 },
- { "sata1", NULL, 15 },
- { "xor1", NULL, 16 },
- { "crypto", NULL, 17 },
- { "pex1", NULL, 18 },
- { "ge1", NULL, 19 },
- { "tdm", NULL, 20 },
- { }
-};
-#endif
-
-static const __initdata struct of_device_id clk_gating_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370
- {
- .compatible = "marvell,armada-370-gating-clock",
- .data = armada_370_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
- {
- .compatible = "marvell,armada-xp-gating-clock",
- .data = armada_xp_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
- {
- .compatible = "marvell,dove-gating-clock",
- .data = dove_gating_descr,
- },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
- {
- .compatible = "marvell,kirkwood-gating-clock",
- .data = kirkwood_gating_descr,
- },
-#endif
-
- { }
-};
-
-void __init mvebu_gating_clk_init(void)
-{
- struct device_node *np;
-
- for_each_matching_node(np, clk_gating_match) {
- const struct of_device_id *match =
- of_match_node(clk_gating_match, np);
- mvebu_clk_gating_setup(np,
- (const struct mvebu_soc_descr *)match->data);
- }
-}
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.h b/drivers/clk/mvebu/clk-gating-ctrl.h
deleted file mode 100644
index 9275d1e51f1b..000000000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Marvell EBU gating clock handling
- *
- * Copyright (C) 2012 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_GATING_H
-#define __MVEBU_CLK_GATING_H
-
-#ifdef CONFIG_MVEBU_CLK_GATING
-void __init mvebu_gating_clk_init(void);
-#else
-void mvebu_gating_clk_init(void) {}
-#endif
-
-#endif
diff --git a/drivers/clk/mvebu/clk.c b/drivers/clk/mvebu/clk.c
deleted file mode 100644
index 29f10fb3006c..000000000000
--- a/drivers/clk/mvebu/clk.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Marvell EBU SoC clock handling.
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include "clk-core.h"
-#include "clk-gating-ctrl.h"
-
-void __init mvebu_clocks_init(void)
-{
- mvebu_core_clk_init();
- mvebu_gating_clk_init();
- of_clk_init(NULL);
-}
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
new file mode 100644
index 000000000000..adaa4a1821b8
--- /dev/null
+++ b/drivers/clk/mvebu/common.c
@@ -0,0 +1,163 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+static struct clk_onecell_data clk_data;
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+ const struct coreclk_soc_desc *desc)
+{
+ const char *tclk_name = "tclk";
+ const char *cpuclk_name = "cpuclk";
+ void __iomem *base;
+ unsigned long rate;
+ int n;
+
+ base = of_iomap(np, 0);
+ if (WARN_ON(!base))
+ return;
+
+ /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
+ clk_data.clk_num = 2 + desc->num_ratios;
+ clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
+ GFP_KERNEL);
+ if (WARN_ON(!clk_data.clks))
+ return;
+
+ /* Register TCLK */
+ of_property_read_string_index(np, "clock-output-names", 0,
+ &tclk_name);
+ rate = desc->get_tclk_freq(base);
+ clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
+ CLK_IS_ROOT, rate);
+ WARN_ON(IS_ERR(clk_data.clks[0]));
+
+ /* Register CPU clock */
+ of_property_read_string_index(np, "clock-output-names", 1,
+ &cpuclk_name);
+ rate = desc->get_cpu_freq(base);
+ clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
+ CLK_IS_ROOT, rate);
+ WARN_ON(IS_ERR(clk_data.clks[1]));
+
+ /* Register fixed-factor clocks derived from CPU clock */
+ for (n = 0; n < desc->num_ratios; n++) {
+ const char *rclk_name = desc->ratios[n].name;
+ int mult, div;
+
+ of_property_read_string_index(np, "clock-output-names",
+ 2+n, &rclk_name);
+ desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
+ clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
+ cpuclk_name, 0, mult, div);
+ WARN_ON(IS_ERR(clk_data.clks[2+n]));
+ };
+
+ /* SAR register isn't needed anymore */
+ iounmap(base);
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+/*
+ * Clock Gating Control
+ */
+
+struct clk_gating_ctrl {
+ spinlock_t lock;
+ struct clk **gates;
+ int num_gates;
+};
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static struct clk *clk_gating_get_src(
+ struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
+ int n;
+
+ if (clkspec->args_count < 1)
+ return ERR_PTR(-EINVAL);
+
+ for (n = 0; n < ctrl->num_gates; n++) {
+ struct clk_gate *gate =
+ to_clk_gate(__clk_get_hw(ctrl->gates[n]));
+ if (clkspec->args[0] == gate->bit_idx)
+ return ctrl->gates[n];
+ }
+ return ERR_PTR(-ENODEV);
+}
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+ const struct clk_gating_soc_desc *desc)
+{
+ struct clk_gating_ctrl *ctrl;
+ struct clk *clk;
+ void __iomem *base;
+ const char *default_parent = NULL;
+ int n;
+
+ base = of_iomap(np, 0);
+ if (WARN_ON(!base))
+ return;
+
+ clk = of_clk_get(np, 0);
+ if (!IS_ERR(clk)) {
+ default_parent = __clk_get_name(clk);
+ clk_put(clk);
+ }
+
+ ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+ if (WARN_ON(!ctrl))
+ return;
+
+ spin_lock_init(&ctrl->lock);
+
+ /* Count, allocate, and register clock gates */
+ for (n = 0; desc[n].name;)
+ n++;
+
+ ctrl->num_gates = n;
+ ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
+ GFP_KERNEL);
+ if (WARN_ON(!ctrl->gates)) {
+ kfree(ctrl);
+ return;
+ }
+
+ for (n = 0; n < ctrl->num_gates; n++) {
+ const char *parent =
+ (desc[n].parent) ? desc[n].parent : default_parent;
+ ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
+ desc[n].flags, base, desc[n].bit_idx,
+ 0, &ctrl->lock);
+ WARN_ON(IS_ERR(ctrl->gates[n]));
+ }
+
+ of_clk_add_provider(np, clk_gating_get_src, ctrl);
+}
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
new file mode 100644
index 000000000000..f968b4d9df92
--- /dev/null
+++ b/drivers/clk/mvebu/common.h
@@ -0,0 +1,48 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CLK_MVEBU_COMMON_H_
+#define __CLK_MVEBU_COMMON_H_
+
+#include <linux/kernel.h>
+
+struct device_node;
+
+struct coreclk_ratio {
+ int id;
+ const char *name;
+};
+
+struct coreclk_soc_desc {
+ u32 (*get_tclk_freq)(void __iomem *sar);
+ u32 (*get_cpu_freq)(void __iomem *sar);
+ void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+ const struct coreclk_ratio *ratios;
+ int num_ratios;
+};
+
+struct clk_gating_soc_desc {
+ const char *name;
+ const char *parent;
+ int bit_idx;
+ unsigned long flags;
+};
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+ const struct coreclk_soc_desc *desc);
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+ const struct clk_gating_soc_desc *desc);
+
+#endif
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
new file mode 100644
index 000000000000..79d7aedf03fb
--- /dev/null
+++ b/drivers/clk/mvebu/dove.c
@@ -0,0 +1,194 @@
+/*
+ * Marvell Dove SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Dove PLL sample-at-reset configuration
+ *
+ * SAR0[8:5] : CPU frequency
+ * 5 = 1000 MHz
+ * 6 = 933 MHz
+ * 7 = 933 MHz
+ * 8 = 800 MHz
+ * 9 = 800 MHz
+ * 10 = 800 MHz
+ * 11 = 1067 MHz
+ * 12 = 667 MHz
+ * 13 = 533 MHz
+ * 14 = 400 MHz
+ * 15 = 333 MHz
+ * others reserved.
+ *
+ * SAR0[11:9] : CPU to L2 Clock divider ratio
+ * 0 = (1/1) * CPU
+ * 2 = (1/2) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * others reserved.
+ *
+ * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
+ * 0 = (1/1) * CPU
+ * 2 = (1/2) * CPU
+ * 3 = (2/5) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * 8 = (1/5) * CPU
+ * 10 = (1/6) * CPU
+ * 12 = (1/7) * CPU
+ * 14 = (1/8) * CPU
+ * 15 = (1/10) * CPU
+ * others reserved.
+ *
+ * SAR0[24:23] : TCLK frequency
+ * 0 = 166 MHz
+ * 1 = 125 MHz
+ * others reserved.
+ */
+
+#define SAR_DOVE_CPU_FREQ 5
+#define SAR_DOVE_CPU_FREQ_MASK 0xf
+#define SAR_DOVE_L2_RATIO 9
+#define SAR_DOVE_L2_RATIO_MASK 0x7
+#define SAR_DOVE_DDR_RATIO 12
+#define SAR_DOVE_DDR_RATIO_MASK 0xf
+#define SAR_DOVE_TCLK_FREQ 23
+#define SAR_DOVE_TCLK_FREQ_MASK 0x3
+
+enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst dove_coreclk_ratios[] = {
+ { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
+ { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static const u32 __initconst dove_tclk_freqs[] = {
+ 166666667,
+ 125000000,
+ 0, 0
+};
+
+static u32 __init dove_get_tclk_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
+ SAR_DOVE_TCLK_FREQ_MASK;
+ return dove_tclk_freqs[opt];
+}
+
+static const u32 __initconst dove_cpu_freqs[] = {
+ 0, 0, 0, 0, 0,
+ 1000000000,
+ 933333333, 933333333,
+ 800000000, 800000000, 800000000,
+ 1066666667,
+ 666666667,
+ 533333333,
+ 400000000,
+ 333333333
+};
+
+static u32 __init dove_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
+ SAR_DOVE_CPU_FREQ_MASK;
+ return dove_cpu_freqs[opt];
+}
+
+static const int __initconst dove_cpu_l2_ratios[8][2] = {
+ { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
+};
+
+static const int __initconst dove_cpu_ddr_ratios[16][2] = {
+ { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
+ { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
+ { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
+};
+
+static void __init dove_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case DOVE_CPU_TO_L2:
+ {
+ u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
+ SAR_DOVE_L2_RATIO_MASK;
+ *mult = dove_cpu_l2_ratios[opt][0];
+ *div = dove_cpu_l2_ratios[opt][1];
+ break;
+ }
+ case DOVE_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
+ SAR_DOVE_DDR_RATIO_MASK;
+ *mult = dove_cpu_ddr_ratios[opt][0];
+ *div = dove_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const struct coreclk_soc_desc dove_coreclks = {
+ .get_tclk_freq = dove_get_tclk_freq,
+ .get_cpu_freq = dove_get_cpu_freq,
+ .get_clk_ratio = dove_get_clk_ratio,
+ .ratios = dove_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
+};
+
+static void __init dove_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &dove_coreclks);
+}
+CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst dove_gating_desc[] = {
+ { "usb0", NULL, 0, 0 },
+ { "usb1", NULL, 1, 0 },
+ { "ge", "gephy", 2, 0 },
+ { "sata", NULL, 3, 0 },
+ { "pex0", NULL, 4, 0 },
+ { "pex1", NULL, 5, 0 },
+ { "sdio0", NULL, 8, 0 },
+ { "sdio1", NULL, 9, 0 },
+ { "nand", NULL, 10, 0 },
+ { "camera", NULL, 11, 0 },
+ { "i2s0", NULL, 12, 0 },
+ { "i2s1", NULL, 13, 0 },
+ { "crypto", NULL, 15, 0 },
+ { "ac97", NULL, 21, 0 },
+ { "pdma", NULL, 22, 0 },
+ { "xor0", NULL, 23, 0 },
+ { "xor1", NULL, 24, 0 },
+ { "gephy", NULL, 30, 0 },
+ { }
+};
+
+static void __init dove_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, dove_gating_desc);
+}
+CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
+ dove_clk_gating_init);
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
new file mode 100644
index 000000000000..71d24619ccdb
--- /dev/null
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -0,0 +1,247 @@
+/*
+ * Marvell Kirkwood SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Kirkwood PLL sample-at-reset configuration
+ * (6180 has different SAR layout than other Kirkwood SoCs)
+ *
+ * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
+ * 4 = 600 MHz
+ * 6 = 800 MHz
+ * 7 = 1000 MHz
+ * 9 = 1200 MHz
+ * 12 = 1500 MHz
+ * 13 = 1600 MHz
+ * 14 = 1800 MHz
+ * 15 = 2000 MHz
+ * others reserved.
+ *
+ * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
+ * 1 = (1/2) * CPU
+ * 3 = (1/3) * CPU
+ * 5 = (1/4) * CPU
+ * others reserved.
+ *
+ * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
+ * 2 = (1/2) * CPU
+ * 4 = (1/3) * CPU
+ * 6 = (1/4) * CPU
+ * 7 = (2/9) * CPU
+ * 8 = (1/5) * CPU
+ * 9 = (1/6) * CPU
+ * others reserved.
+ *
+ * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
+ * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
+ * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
+ * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
+ * others reserved.
+ *
+ * SAR0[21] : TCLK frequency
+ * 0 = 200 MHz
+ * 1 = 166 MHz
+ * others reserved.
+ */
+
+#define SAR_KIRKWOOD_CPU_FREQ(x) \
+ (((x & (1 << 1)) >> 1) | \
+ ((x & (1 << 22)) >> 21) | \
+ ((x & (3 << 3)) >> 1))
+#define SAR_KIRKWOOD_L2_RATIO(x) \
+ (((x & (3 << 9)) >> 9) | \
+ (((x & (1 << 19)) >> 17)))
+#define SAR_KIRKWOOD_DDR_RATIO 5
+#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
+#define SAR_MV88F6180_CLK 2
+#define SAR_MV88F6180_CLK_MASK 0x7
+#define SAR_KIRKWOOD_TCLK_FREQ 21
+#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
+
+enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = {
+ { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
+ { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
+ SAR_KIRKWOOD_TCLK_FREQ_MASK;
+ return (opt) ? 166666667 : 200000000;
+}
+
+static const u32 __initconst kirkwood_cpu_freqs[] = {
+ 0, 0, 0, 0,
+ 600000000,
+ 0,
+ 800000000,
+ 1000000000,
+ 0,
+ 1200000000,
+ 0, 0,
+ 1500000000,
+ 1600000000,
+ 1800000000,
+ 2000000000
+};
+
+static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
+ return kirkwood_cpu_freqs[opt];
+}
+
+static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
+ { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
+ { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
+};
+
+static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
+ { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+ { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
+ { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
+ { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+};
+
+static void __init kirkwood_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case KIRKWOOD_CPU_TO_L2:
+ {
+ u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
+ *mult = kirkwood_cpu_l2_ratios[opt][0];
+ *div = kirkwood_cpu_l2_ratios[opt][1];
+ break;
+ }
+ case KIRKWOOD_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
+ SAR_KIRKWOOD_DDR_RATIO_MASK;
+ *mult = kirkwood_cpu_ddr_ratios[opt][0];
+ *div = kirkwood_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const u32 __initconst mv88f6180_cpu_freqs[] = {
+ 0, 0, 0, 0, 0,
+ 600000000,
+ 800000000,
+ 1000000000
+};
+
+static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
+ return mv88f6180_cpu_freqs[opt];
+}
+
+static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
+ { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
+ { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
+};
+
+static void __init mv88f6180_get_clk_ratio(
+ void __iomem *sar, int id, int *mult, int *div)
+{
+ switch (id) {
+ case KIRKWOOD_CPU_TO_L2:
+ {
+ /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
+ *mult = 1;
+ *div = 2;
+ break;
+ }
+ case KIRKWOOD_CPU_TO_DDR:
+ {
+ u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
+ SAR_MV88F6180_CLK_MASK;
+ *mult = mv88f6180_cpu_ddr_ratios[opt][0];
+ *div = mv88f6180_cpu_ddr_ratios[opt][1];
+ break;
+ }
+ }
+}
+
+static const struct coreclk_soc_desc kirkwood_coreclks = {
+ .get_tclk_freq = kirkwood_get_tclk_freq,
+ .get_cpu_freq = kirkwood_get_cpu_freq,
+ .get_clk_ratio = kirkwood_get_clk_ratio,
+ .ratios = kirkwood_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init kirkwood_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &kirkwood_coreclks);
+}
+CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
+ kirkwood_coreclk_init);
+
+static const struct coreclk_soc_desc mv88f6180_coreclks = {
+ .get_tclk_freq = kirkwood_get_tclk_freq,
+ .get_cpu_freq = mv88f6180_get_cpu_freq,
+ .get_clk_ratio = mv88f6180_get_clk_ratio,
+ .ratios = kirkwood_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init mv88f6180_coreclk_init(struct device_node *np)
+{
+ mvebu_coreclk_setup(np, &mv88f6180_coreclks);
+}
+CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
+ mv88f6180_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = {
+ { "ge0", NULL, 0, 0 },
+ { "pex0", NULL, 2, 0 },
+ { "usb0", NULL, 3, 0 },
+ { "sdio", NULL, 4, 0 },
+ { "tsu", NULL, 5, 0 },
+ { "runit", NULL, 7, 0 },
+ { "xor0", NULL, 8, 0 },
+ { "audio", NULL, 9, 0 },
+ { "powersave", "cpuclk", 11, 0 },
+ { "sata0", NULL, 14, 0 },
+ { "sata1", NULL, 15, 0 },
+ { "xor1", NULL, 16, 0 },
+ { "crypto", NULL, 17, 0 },
+ { "pex1", NULL, 18, 0 },
+ { "ge1", NULL, 19, 0 },
+ { "tdm", NULL, 20, 0 },
+ { }
+};
+
+static void __init kirkwood_clk_gating_init(struct device_node *np)
+{
+ mvebu_clk_gating_setup(np, kirkwood_gating_desc);
+}
+CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
+ kirkwood_clk_gating_init);
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index bd11315cf5ab..5bb848cac6ec 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -24,15 +24,17 @@
#include <linux/of.h>
/* Clock Manager offsets */
-#define CLKMGR_CTRL 0x0
-#define CLKMGR_BYPASS 0x4
+#define CLKMGR_CTRL 0x0
+#define CLKMGR_BYPASS 0x4
+#define CLKMGR_L4SRC 0x70
+#define CLKMGR_PERPLL_SRC 0xAC
/* Clock bypass bits */
-#define MAINPLL_BYPASS (1<<0)
-#define SDRAMPLL_BYPASS (1<<1)
-#define SDRAMPLL_SRC_BYPASS (1<<2)
-#define PERPLL_BYPASS (1<<3)
-#define PERPLL_SRC_BYPASS (1<<4)
+#define MAINPLL_BYPASS (1<<0)
+#define SDRAMPLL_BYPASS (1<<1)
+#define SDRAMPLL_SRC_BYPASS (1<<2)
+#define PERPLL_BYPASS (1<<3)
+#define PERPLL_SRC_BYPASS (1<<4)
#define SOCFPGA_PLL_BG_PWRDWN 0
#define SOCFPGA_PLL_EXT_ENA 1
@@ -41,6 +43,17 @@
#define SOCFPGA_PLL_DIVF_SHIFT 3
#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
#define SOCFPGA_PLL_DIVQ_SHIFT 16
+#define SOCFGPA_MAX_PARENTS 3
+
+#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
+#define SOCFPGA_NAND_CLK "nand_clk"
+#define SOCFPGA_NAND_X_CLK "nand_x_clk"
+#define SOCFPGA_MMC_CLK "mmc_clk"
+#define SOCFPGA_DB_CLK "gpio_db_clk"
+
+#define div_mask(width) ((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
extern void __iomem *clk_mgr_base_addr;
@@ -49,6 +62,9 @@ struct socfpga_clk {
char *parent_name;
char *clk_name;
u32 fixed_div;
+ void __iomem *div_reg;
+ u32 width; /* only valid if div_reg != 0 */
+ u32 shift; /* only valid if div_reg != 0 */
};
#define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
@@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
socfpga_clk->hw.hw.init = &init;
- if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
- strcmp(clk_name, "sdram_pll")) {
+ if (streq(clk_name, "main_pll") ||
+ streq(clk_name, "periph_pll") ||
+ streq(clk_name, "sdram_pll")) {
socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
clk_pll_ops.enable = clk_gate_ops.enable;
clk_pll_ops.disable = clk_gate_ops.disable;
@@ -148,6 +165,159 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
return clk;
}
+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
+{
+ u32 l4_src;
+ u32 perpll_src;
+
+ if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+ l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+ return l4_src &= 0x1;
+ }
+ if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+ l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+ return !!(l4_src & 2);
+ }
+
+ perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+ if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+ return perpll_src &= 0x3;
+ if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+ streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+ return (perpll_src >> 2) & 3;
+
+ /* QSPI clock */
+ return (perpll_src >> 4) & 3;
+
+}
+
+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
+{
+ u32 src_reg;
+
+ if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+ src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+ src_reg &= ~0x1;
+ src_reg |= parent;
+ writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+ } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+ src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+ src_reg &= ~0x2;
+ src_reg |= (parent << 1);
+ writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+ } else {
+ src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+ if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+ src_reg &= ~0x3;
+ src_reg |= parent;
+ } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+ streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+ src_reg &= ~0xC;
+ src_reg |= (parent << 2);
+ } else {/* QSPI clock */
+ src_reg &= ~0x30;
+ src_reg |= (parent << 4);
+ }
+ writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+ }
+
+ return 0;
+}
+
+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
+ unsigned long parent_rate)
+{
+ struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+ u32 div = 1, val;
+
+ if (socfpgaclk->fixed_div)
+ div = socfpgaclk->fixed_div;
+ else if (socfpgaclk->div_reg) {
+ val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+ val &= div_mask(socfpgaclk->width);
+ if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
+ div = val + 1;
+ else
+ div = (1 << val);
+ }
+
+ return parent_rate / div;
+}
+
+static struct clk_ops gateclk_ops = {
+ .recalc_rate = socfpga_clk_recalc_rate,
+ .get_parent = socfpga_clk_get_parent,
+ .set_parent = socfpga_clk_set_parent,
+};
+
+static void __init socfpga_gate_clk_init(struct device_node *node,
+ const struct clk_ops *ops)
+{
+ u32 clk_gate[2];
+ u32 div_reg[3];
+ u32 fixed_div;
+ struct clk *clk;
+ struct socfpga_clk *socfpga_clk;
+ const char *clk_name = node->name;
+ const char *parent_name[SOCFGPA_MAX_PARENTS];
+ struct clk_init_data init;
+ int rc;
+ int i = 0;
+
+ socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
+ if (WARN_ON(!socfpga_clk))
+ return;
+
+ rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+ if (rc)
+ clk_gate[0] = 0;
+
+ if (clk_gate[0]) {
+ socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+ socfpga_clk->hw.bit_idx = clk_gate[1];
+
+ gateclk_ops.enable = clk_gate_ops.enable;
+ gateclk_ops.disable = clk_gate_ops.disable;
+ }
+
+ rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+ if (rc)
+ socfpga_clk->fixed_div = 0;
+ else
+ socfpga_clk->fixed_div = fixed_div;
+
+ rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+ if (!rc) {
+ socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+ socfpga_clk->shift = div_reg[1];
+ socfpga_clk->width = div_reg[2];
+ } else {
+ socfpga_clk->div_reg = 0;
+ }
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ init.name = clk_name;
+ init.ops = ops;
+ init.flags = 0;
+ while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
+ of_clk_get_parent_name(node, i)) != NULL)
+ i++;
+
+ init.parent_names = parent_name;
+ init.num_parents = i;
+ socfpga_clk->hw.hw.init = &init;
+
+ clk = clk_register(NULL, &socfpga_clk->hw.hw);
+ if (WARN_ON(IS_ERR(clk))) {
+ kfree(socfpga_clk);
+ return;
+ }
+ rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ if (WARN_ON(rc))
+ return;
+}
+
static void __init socfpga_pll_init(struct device_node *node)
{
socfpga_clk_init(node, &clk_pll_ops);
@@ -160,6 +330,12 @@ static void __init socfpga_periph_init(struct device_node *node)
}
CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
+static void __init socfpga_gate_init(struct device_node *node)
+{
+ socfpga_gate_clk_init(node, &gateclk_ops);
+}
+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
+
void __init socfpga_init_clocks(void)
{
struct clk *clk;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16ee161c..40d939d091bf 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -250,6 +250,9 @@
#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
#define CLK_SOURCE_EMC 0x19c
+/* Tegra CPU clock and reset control regs */
+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
+
static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
static void __iomem *clk_base;
@@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
}
}
-static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+/* Tegra114 CPU clock and reset control functions */
+static void tegra114_wait_cpu_in_reset(u32 cpu)
+{
+ unsigned int reg;
+
+ do {
+ reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+ cpu_relax();
+ } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
+}
+static void tegra114_disable_cpu_clock(u32 cpu)
+{
+ /* flow controller would take care in the power sequence. */
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
+ .wait_for_reset = tegra114_wait_cpu_in_reset,
+ .disable_clock = tegra114_disable_cpu_clock,
+};
static const struct of_device_id pmc_match[] __initconst = {
{ .compatible = "nvidia,tegra114-pmc" },
diff --git a/drivers/clk/zynq/Makefile b/drivers/clk/zynq/Makefile
new file mode 100644
index 000000000000..156d923f4fa9
--- /dev/null
+++ b/drivers/clk/zynq/Makefile
@@ -0,0 +1,3 @@
+# Zynq clock specific Makefile
+
+obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
new file mode 100644
index 000000000000..5c205b60a82a
--- /dev/null
+++ b/drivers/clk/zynq/clkc.c
@@ -0,0 +1,533 @@
+/*
+ * Zynq clock controller
+ *
+ * Copyright (C) 2012 - 2013 Xilinx
+ *
+ * Sören Brinkmann <soren.brinkmann@xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk/zynq.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/io.h>
+
+static void __iomem *zynq_slcr_base_priv;
+
+#define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100)
+#define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104)
+#define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108)
+#define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c)
+#define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120)
+#define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124)
+#define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128)
+#define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c)
+#define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140)
+#define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144)
+#define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148)
+#define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c)
+#define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150)
+#define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154)
+#define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158)
+#define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c)
+#define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160)
+#define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164)
+#define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168)
+#define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170)
+#define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4)
+#define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304)
+
+#define NUM_MIO_PINS 54
+
+enum zynq_clk {
+ armpll, ddrpll, iopll,
+ cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
+ ddr2x, ddr3x, dci,
+ lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
+ sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
+ usb0_aper, usb1_aper, gem0_aper, gem1_aper,
+ sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
+ i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
+ smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
+
+static struct clk *ps_clk;
+static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
+
+static DEFINE_SPINLOCK(armpll_lock);
+static DEFINE_SPINLOCK(ddrpll_lock);
+static DEFINE_SPINLOCK(iopll_lock);
+static DEFINE_SPINLOCK(armclk_lock);
+static DEFINE_SPINLOCK(ddrclk_lock);
+static DEFINE_SPINLOCK(dciclk_lock);
+static DEFINE_SPINLOCK(gem0clk_lock);
+static DEFINE_SPINLOCK(gem1clk_lock);
+static DEFINE_SPINLOCK(canclk_lock);
+static DEFINE_SPINLOCK(canmioclk_lock);
+static DEFINE_SPINLOCK(dbgclk_lock);
+static DEFINE_SPINLOCK(aperclk_lock);
+
+static const char dummy_nm[] __initconst = "dummy_name";
+
+static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
+static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
+static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
+static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm};
+static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm};
+static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
+ "can0_mio_mux"};
+static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
+ "can1_mio_mux"};
+static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
+ dummy_nm};
+
+static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
+static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
+static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
+static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
+
+static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
+ const char *clk_name, void __iomem *fclk_ctrl_reg,
+ const char **parents)
+{
+ struct clk *clk;
+ char *mux_name;
+ char *div0_name;
+ char *div1_name;
+ spinlock_t *fclk_lock;
+ spinlock_t *fclk_gate_lock;
+ void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
+
+ fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
+ if (!fclk_lock)
+ goto err;
+ fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
+ if (!fclk_gate_lock)
+ goto err;
+ spin_lock_init(fclk_lock);
+ spin_lock_init(fclk_gate_lock);
+
+ mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
+ div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
+ div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
+
+ clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
+ fclk_ctrl_reg, 4, 2, 0, fclk_lock);
+
+ clk = clk_register_divider(NULL, div0_name, mux_name,
+ 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
+
+ clk = clk_register_divider(NULL, div1_name, div0_name,
+ CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ fclk_lock);
+
+ clks[fclk] = clk_register_gate(NULL, clk_name,
+ div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
+ 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
+ kfree(mux_name);
+ kfree(div0_name);
+ kfree(div1_name);
+
+ return;
+
+err:
+ clks[fclk] = ERR_PTR(-ENOMEM);
+}
+
+static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
+ enum zynq_clk clk1, const char *clk_name0,
+ const char *clk_name1, void __iomem *clk_ctrl,
+ const char **parents, unsigned int two_gates)
+{
+ struct clk *clk;
+ char *mux_name;
+ char *div_name;
+ spinlock_t *lock;
+
+ lock = kmalloc(sizeof(*lock), GFP_KERNEL);
+ if (!lock)
+ goto err;
+ spin_lock_init(lock);
+
+ mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
+ div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
+
+ clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
+ clk_ctrl, 4, 2, 0, lock);
+
+ clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
+
+ clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
+ CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
+ if (two_gates)
+ clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
+ CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
+
+ kfree(mux_name);
+ kfree(div_name);
+
+ return;
+
+err:
+ clks[clk0] = ERR_PTR(-ENOMEM);
+ if (two_gates)
+ clks[clk1] = ERR_PTR(-ENOMEM);
+}
+
+static void __init zynq_clk_setup(struct device_node *np)
+{
+ int i;
+ u32 tmp;
+ int ret;
+ struct clk *clk;
+ char *clk_name;
+ const char *clk_output_name[clk_max];
+ const char *cpu_parents[4];
+ const char *periph_parents[4];
+ const char *swdt_ext_clk_mux_parents[2];
+ const char *can_mio_mux_parents[NUM_MIO_PINS];
+
+ pr_info("Zynq clock init\n");
+
+ /* get clock output names from DT */
+ for (i = 0; i < clk_max; i++) {
+ if (of_property_read_string_index(np, "clock-output-names",
+ i, &clk_output_name[i])) {
+ pr_err("%s: clock output name not in DT\n", __func__);
+ BUG();
+ }
+ }
+ cpu_parents[0] = clk_output_name[armpll];
+ cpu_parents[1] = clk_output_name[armpll];
+ cpu_parents[2] = clk_output_name[ddrpll];
+ cpu_parents[3] = clk_output_name[iopll];
+ periph_parents[0] = clk_output_name[iopll];
+ periph_parents[1] = clk_output_name[iopll];
+ periph_parents[2] = clk_output_name[armpll];
+ periph_parents[3] = clk_output_name[ddrpll];
+
+ /* ps_clk */
+ ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
+ if (ret) {
+ pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
+ tmp = 33333333;
+ }
+ ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
+ tmp);
+
+ /* PLLs */
+ clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
+ SLCR_PLL_STATUS, 0, &armpll_lock);
+ clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
+ armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0,
+ &armpll_lock);
+
+ clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
+ SLCR_PLL_STATUS, 1, &ddrpll_lock);
+ clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
+ ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0,
+ &ddrpll_lock);
+
+ clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
+ SLCR_PLL_STATUS, 2, &iopll_lock);
+ clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
+ iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0,
+ &iopll_lock);
+
+ /* CPU clocks */
+ tmp = readl(SLCR_621_TRUE) & 1;
+ clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0,
+ SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock);
+ clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
+ SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
+
+ clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
+ "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
+
+ clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
+ 1, 2);
+ clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
+ "cpu_3or2x_div", CLK_IGNORE_UNUSED,
+ SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
+
+ clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
+ 2 + tmp);
+ clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
+ "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
+ 26, 0, &armclk_lock);
+
+ clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
+ 4 + 2 * tmp);
+ clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
+ "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
+ 0, &armclk_lock);
+
+ /* Timers */
+ swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
+ for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
+ int idx = of_property_match_string(np, "clock-names",
+ swdt_ext_clk_input_names[i]);
+ if (idx >= 0)
+ swdt_ext_clk_mux_parents[i + 1] =
+ of_clk_get_parent_name(np, idx);
+ else
+ swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
+ }
+ clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
+ swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
+ SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock);
+
+ /* DDR clocks */
+ clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
+ SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
+ clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
+ "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
+ clk_prepare_enable(clks[ddr2x]);
+ clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
+ SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
+ clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
+ "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
+ clk_prepare_enable(clks[ddr3x]);
+
+ clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
+ SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
+ clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
+ CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ &dciclk_lock);
+ clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
+ CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
+ &dciclk_lock);
+ clk_prepare_enable(clks[dci]);
+
+ /* Peripheral clocks */
+ for (i = fclk0; i <= fclk3; i++)
+ zynq_clk_register_fclk(i, clk_output_name[i],
+ SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
+ periph_parents);
+
+ zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
+ SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
+
+ zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
+ SLCR_SMC_CLK_CTRL, periph_parents, 0);
+
+ zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
+ SLCR_PCAP_CLK_CTRL, periph_parents, 0);
+
+ zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
+ clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
+ periph_parents, 1);
+
+ zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
+ clk_output_name[uart1], SLCR_UART_CLK_CTRL,
+ periph_parents, 1);
+
+ zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
+ clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
+ periph_parents, 1);
+
+ for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
+ int idx = of_property_match_string(np, "clock-names",
+ gem0_emio_input_names[i]);
+ if (idx >= 0)
+ gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
+ idx);
+ }
+ clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0,
+ SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock);
+ clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
+ SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
+ clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
+ CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ &gem0clk_lock);
+ clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0,
+ SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
+ clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
+ "gem0_emio_mux", CLK_SET_RATE_PARENT,
+ SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
+
+ for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
+ int idx = of_property_match_string(np, "clock-names",
+ gem1_emio_input_names[i]);
+ if (idx >= 0)
+ gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
+ idx);
+ }
+ clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0,
+ SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock);
+ clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
+ SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
+ clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
+ CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ &gem1clk_lock);
+ clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0,
+ SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
+ clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
+ "gem1_emio_mux", CLK_SET_RATE_PARENT,
+ SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
+
+ tmp = strlen("mio_clk_00x");
+ clk_name = kmalloc(tmp, GFP_KERNEL);
+ for (i = 0; i < NUM_MIO_PINS; i++) {
+ int idx;
+
+ snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
+ idx = of_property_match_string(np, "clock-names", clk_name);
+ if (idx >= 0)
+ can_mio_mux_parents[i] = of_clk_get_parent_name(np,
+ idx);
+ else
+ can_mio_mux_parents[i] = dummy_nm;
+ }
+ kfree(clk_name);
+ clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0,
+ SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock);
+ clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
+ SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
+ clk = clk_register_divider(NULL, "can_div1", "can_div0",
+ CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
+ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ &canclk_lock);
+ clk = clk_register_gate(NULL, "can0_gate", "can_div1",
+ CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
+ &canclk_lock);
+ clk = clk_register_gate(NULL, "can1_gate", "can_div1",
+ CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
+ &canclk_lock);
+ clk = clk_register_mux(NULL, "can0_mio_mux",
+ can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
+ SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock);
+ clk = clk_register_mux(NULL, "can1_mio_mux",
+ can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
+ SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock);
+ clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
+ can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
+ SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock);
+ clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
+ can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
+ SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock);
+
+ for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
+ int idx = of_property_match_string(np, "clock-names",
+ dbgtrc_emio_input_names[i]);
+ if (idx >= 0)
+ dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
+ idx);
+ }
+ clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0,
+ SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock);
+ clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
+ SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
+ clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0,
+ SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock);
+ clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
+ "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
+ 0, 0, &dbgclk_lock);
+ clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
+ clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
+ &dbgclk_lock);
+
+ /* One gated clock for all APER clocks. */
+ clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
+ clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
+ &aperclk_lock);
+ clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
+ &aperclk_lock);
+ clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
+ &aperclk_lock);
+ clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
+ &aperclk_lock);
+ clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
+ &aperclk_lock);
+ clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
+ &aperclk_lock);
+ clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
+ &aperclk_lock);
+ clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
+ &aperclk_lock);
+ clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
+ &aperclk_lock);
+ clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
+ &aperclk_lock);
+ clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
+ &aperclk_lock);
+ clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
+ &aperclk_lock);
+ clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
+ &aperclk_lock);
+ clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
+ &aperclk_lock);
+ clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
+ &aperclk_lock);
+ clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
+ &aperclk_lock);
+ clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
+ &aperclk_lock);
+ clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
+ clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
+ &aperclk_lock);
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ if (IS_ERR(clks[i])) {
+ pr_err("Zynq clk %d: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+ BUG();
+ }
+ }
+
+ clk_data.clks = clks;
+ clk_data.clk_num = ARRAY_SIZE(clks);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
+
+void __init zynq_clock_init(void __iomem *slcr_base)
+{
+ zynq_slcr_base_priv = slcr_base;
+ of_clk_init(NULL);
+}
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
new file mode 100644
index 000000000000..47e307c25a7b
--- /dev/null
+++ b/drivers/clk/zynq/pll.c
@@ -0,0 +1,235 @@
+/*
+ * Zynq PLL driver
+ *
+ * Copyright (C) 2013 Xilinx
+ *
+ * Sören Brinkmann <soren.brinkmann@xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/clk/zynq.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+/**
+ * struct zynq_pll
+ * @hw: Handle between common and hardware-specific interfaces
+ * @pll_ctrl: PLL control register
+ * @pll_status: PLL status register
+ * @lock: Register lock
+ * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
+ * register.
+ */
+struct zynq_pll {
+ struct clk_hw hw;
+ void __iomem *pll_ctrl;
+ void __iomem *pll_status;
+ spinlock_t *lock;
+ u8 lockbit;
+};
+#define to_zynq_pll(_hw) container_of(_hw, struct zynq_pll, hw)
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK 0x7f000
+#define PLLCTRL_FBDIV_SHIFT 12
+#define PLLCTRL_BPQUAL_MASK (1 << 3)
+#define PLLCTRL_PWRDWN_MASK 2
+#define PLLCTRL_PWRDWN_SHIFT 1
+#define PLLCTRL_RESET_MASK 1
+#define PLLCTRL_RESET_SHIFT 0
+
+/**
+ * zynq_pll_round_rate() - Round a clock frequency
+ * @hw: Handle between common and hardware-specific interfaces
+ * @rate: Desired clock frequency
+ * @prate: Clock frequency of parent clock
+ * Returns frequency closest to @rate the hardware can generate.
+ */
+static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u32 fbdiv;
+
+ fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
+ if (fbdiv < 13)
+ fbdiv = 13;
+ else if (fbdiv > 66)
+ fbdiv = 66;
+
+ return *prate * fbdiv;
+}
+
+/**
+ * zynq_pll_recalc_rate() - Recalculate clock frequency
+ * @hw: Handle between common and hardware-specific interfaces
+ * @parent_rate: Clock frequency of parent clock
+ * Returns current clock frequency.
+ */
+static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct zynq_pll *clk = to_zynq_pll(hw);
+ u32 fbdiv;
+
+ /*
+ * makes probably sense to redundantly save fbdiv in the struct
+ * zynq_pll to save the IO access.
+ */
+ fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
+ PLLCTRL_FBDIV_SHIFT;
+
+ return parent_rate * fbdiv;
+}
+
+/**
+ * zynq_pll_is_enabled - Check if a clock is enabled
+ * @hw: Handle between common and hardware-specific interfaces
+ * Returns 1 if the clock is enabled, 0 otherwise.
+ *
+ * Not sure this is a good idea, but since disabled means bypassed for
+ * this clock implementation we say we are always enabled.
+ */
+static int zynq_pll_is_enabled(struct clk_hw *hw)
+{
+ unsigned long flags = 0;
+ u32 reg;
+ struct zynq_pll *clk = to_zynq_pll(hw);
+
+ spin_lock_irqsave(clk->lock, flags);
+
+ reg = readl(clk->pll_ctrl);
+
+ spin_unlock_irqrestore(clk->lock, flags);
+
+ return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
+}
+
+/**
+ * zynq_pll_enable - Enable clock
+ * @hw: Handle between common and hardware-specific interfaces
+ * Returns 0 on success
+ */
+static int zynq_pll_enable(struct clk_hw *hw)
+{
+ unsigned long flags = 0;
+ u32 reg;
+ struct zynq_pll *clk = to_zynq_pll(hw);
+
+ if (zynq_pll_is_enabled(hw))
+ return 0;
+
+ pr_info("PLL: enable\n");
+
+ /* Power up PLL and wait for lock */
+ spin_lock_irqsave(clk->lock, flags);
+
+ reg = readl(clk->pll_ctrl);
+ reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
+ writel(reg, clk->pll_ctrl);
+ while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
+ ;
+
+ spin_unlock_irqrestore(clk->lock, flags);
+
+ return 0;
+}
+
+/**
+ * zynq_pll_disable - Disable clock
+ * @hw: Handle between common and hardware-specific interfaces
+ * Returns 0 on success
+ */
+static void zynq_pll_disable(struct clk_hw *hw)
+{
+ unsigned long flags = 0;
+ u32 reg;
+ struct zynq_pll *clk = to_zynq_pll(hw);
+
+ if (!zynq_pll_is_enabled(hw))
+ return;
+
+ pr_info("PLL: shutdown\n");
+
+ /* shut down PLL */
+ spin_lock_irqsave(clk->lock, flags);
+
+ reg = readl(clk->pll_ctrl);
+ reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
+ writel(reg, clk->pll_ctrl);
+
+ spin_unlock_irqrestore(clk->lock, flags);
+}
+
+static const struct clk_ops zynq_pll_ops = {
+ .enable = zynq_pll_enable,
+ .disable = zynq_pll_disable,
+ .is_enabled = zynq_pll_is_enabled,
+ .round_rate = zynq_pll_round_rate,
+ .recalc_rate = zynq_pll_recalc_rate
+};
+
+/**
+ * clk_register_zynq_pll() - Register PLL with the clock framework
+ * @np Pointer to the DT device node
+ */
+struct clk *clk_register_zynq_pll(const char *name, const char *parent,
+ void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
+ spinlock_t *lock)
+{
+ struct zynq_pll *pll;
+ struct clk *clk;
+ u32 reg;
+ const char *parent_arr[1] = {parent};
+ unsigned long flags = 0;
+ struct clk_init_data initd = {
+ .name = name,
+ .parent_names = parent_arr,
+ .ops = &zynq_pll_ops,
+ .num_parents = 1,
+ .flags = 0
+ };
+
+ pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll) {
+ pr_err("%s: Could not allocate Zynq PLL clk.\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ /* Populate the struct */
+ pll->hw.init = &initd;
+ pll->pll_ctrl = pll_ctrl;
+ pll->pll_status = pll_status;
+ pll->lockbit = lock_index;
+ pll->lock = lock;
+
+ spin_lock_irqsave(pll->lock, flags);
+
+ reg = readl(pll->pll_ctrl);
+ reg &= ~PLLCTRL_BPQUAL_MASK;
+ writel(reg, pll->pll_ctrl);
+
+ spin_unlock_irqrestore(pll->lock, flags);
+
+ clk = clk_register(NULL, &pll->hw);
+ if (WARN_ON(IS_ERR(clk)))
+ goto free_pll;
+
+ return clk;
+
+free_pll:
+ kfree(pll);
+
+ return clk;
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 01:07:35 +0000