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authorStephen Rothwell <sfr@canb.auug.org.au>2014-01-10 13:32:05 +1100
committerStephen Rothwell <sfr@canb.auug.org.au>2014-01-10 13:32:05 +1100
commit592410b1ba9daf61c3bde92762a43eac58000850 (patch)
tree80b54178a129ec9988bfc978cb8914d4d6b7fb0d /include
parenta11acbbed1bf2fd3204027d2b2ac6246daf14445 (diff)
parent45420d7053db484b4a254cbb36cf6174f483f7d6 (diff)
Merge remote-tracking branch 'spi/for-next'
Conflicts: drivers/spi/spi-mpc512x-psc.c
Diffstat (limited to 'include')
-rw-r--r--include/linux/platform_data/spi-nuc900.h8
-rw-r--r--include/linux/spi/s3c24xx.h2
-rw-r--r--include/linux/spi/spi.h2
3 files changed, 6 insertions, 6 deletions
diff --git a/include/linux/platform_data/spi-nuc900.h b/include/linux/platform_data/spi-nuc900.h
index 2c4e0c128501..4b3f46832e19 100644
--- a/include/linux/platform_data/spi-nuc900.h
+++ b/include/linux/platform_data/spi-nuc900.h
@@ -1,6 +1,4 @@
/*
- * arch/arm/mach-w90x900/include/mach/nuc900_spi.h
- *
* Copyright (c) 2009 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
@@ -11,8 +9,8 @@
*
*/
-#ifndef __ASM_ARCH_SPI_H
-#define __ASM_ARCH_SPI_H
+#ifndef __SPI_NUC900_H
+#define __SPI_NUC900_H
extern void mfp_set_groupg(struct device *dev, const char *subname);
@@ -32,4 +30,4 @@ struct nuc900_spi_chip {
unsigned char bits_per_word;
};
-#endif /* __ASM_ARCH_SPI_H */
+#endif /* __SPI_NUC900_H */
diff --git a/include/linux/spi/s3c24xx.h b/include/linux/spi/s3c24xx.h
index c23b923e493b..ca271c06c591 100644
--- a/include/linux/spi/s3c24xx.h
+++ b/include/linux/spi/s3c24xx.h
@@ -23,4 +23,6 @@ struct s3c2410_spi_info {
void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
};
+extern int s3c24xx_set_fiq(unsigned int irq, bool on);
+
#endif /* __LINUX_SPI_S3C24XX_H */
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 8c62ba74dd91..27a882978c15 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -75,6 +75,7 @@ struct spi_device {
struct spi_master *master;
u32 max_speed_hz;
u8 chip_select;
+ u8 bits_per_word;
u16 mode;
#define SPI_CPHA 0x01 /* clock phase */
#define SPI_CPOL 0x02 /* clock polarity */
@@ -92,7 +93,6 @@ struct spi_device {
#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
- u8 bits_per_word;
int irq;
void *controller_state;
void *controller_data;