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authorThierry Reding <treding@nvidia.com>2014-01-10 17:12:54 +0100
committerThierry Reding <treding@nvidia.com>2014-01-10 17:12:54 +0100
commit1766938c2a1d36aa1963c7669f16b06bb9673860 (patch)
treebc3e729a9139724090d66a436e22ff387de0221e /drivers/gpu
parentd48b4eab92321df96dd8fd0564c9fd0f30f4ac7a (diff)
HACK: Modify display A and B latency allowanceHEADmaster
This allows the HDMI output on Cardhu to work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/tegra/dc.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index da1d55acc41d..635e584dca76 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1175,6 +1175,36 @@ static int tegra_dc_init(struct host1x_client *client)
struct tegra_dc *dc = host1x_client_to_dc(client);
int err;
+ if (1) {
+ void __iomem *mc = ioremap_nocache(0x7000f000, SZ_4K);
+
+ switch (dc->pipe) {
+ case 0:
+ dev_info(client->dev, "latency allowance: display A\n");
+ dev_info(client->dev, " %08x\n", readl(mc + 0x2e8));
+ dev_info(client->dev, " %08x\n", readl(mc + 0x2ec));
+ dev_info(client->dev, " %08x\n", readl(mc + 0x2f0));
+
+ writel(0x00200020, mc + 0x2e8);
+ writel(0x00200020, mc + 0x2ec);
+ writel(0x0000007f, mc + 0x2f0);
+ break;
+
+ case 1:
+ dev_info(client->dev, "latency allowance: display B\n");
+ dev_info(client->dev, " %08x\n", readl(mc + 0x2f4));
+ dev_info(client->dev, " %08x\n", readl(mc + 0x2f8));
+ dev_info(client->dev, " %08x\n", readl(mc + 0x2fc));
+
+ writel(0x00200010, mc + 0x2f4);
+ writel(0x00200020, mc + 0x2f8);
+ writel(0x0000007f, mc + 0x2fc);
+ break;
+ }
+
+ iounmap(mc);
+ }
+
drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs);
drm_mode_crtc_set_gamma_size(&dc->base, 256);
drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);