diff options
| author | Aaro Koskinen <aaro.koskinen@iki.fi> | 2014-01-10 12:40:40 +1100 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2014-01-10 12:40:40 +1100 |
| commit | e8f0761e6332bf8a550facabc5eb1c1f9a7aa841 (patch) | |
| tree | a5b67bc4948a10eb6c3393f00b9320da5c50412d /arch/mips/mm/c-r4k.c | |
| parent | e9eaf04d5a768e4dae090ebd01d4407b9553aa11 (diff) | |
MIPS: fix blast_icache32 on loongson2
Commit 14bd8c082016cd1f6 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery
all over arch/mips") failed to add Loongson2 specific blast_icache32
functions. Fix that.
The patch fixes the following crash seen with 3.13-rc1:
[ 3.652000] Reserved instruction in kernel code[#1]:
[...]
[ 3.652000] Call Trace:
[ 3.652000] [<ffffffff802223c8>] blast_icache32_page+0x8/0xb0
[ 3.652000] [<ffffffff80222c34>] r4k_flush_cache_page+0x19c/0x200
[ 3.652000] [<ffffffff802d17e4>] do_wp_page.isra.97+0x47c/0xe08
[ 3.652000] [<ffffffff802d51b0>] handle_mm_fault+0x938/0x1118
[ 3.652000] [<ffffffff8021bd40>] __do_page_fault+0x140/0x540
[ 3.652000] [<ffffffff80206be4>] resume_userspace_check+0x0/0x10
[ 3.652000]
[ 3.652000] Code: 00200825 64834000 00200825 <bc900000> bc900020 bc900040 bc900060 bc900080 bc9000a0
[ 3.656000] ---[ end trace cd8a48f722f5c5f7 ]---
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 73f02da61baf..49e572d879e1 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -237,6 +237,8 @@ static void r4k_blast_icache_page_setup(void) r4k_blast_icache_page = (void *)cache_noop; else if (ic_lsize == 16) r4k_blast_icache_page = blast_icache16_page; + else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) + r4k_blast_icache_page = loongson2_blast_icache32_page; else if (ic_lsize == 32) r4k_blast_icache_page = blast_icache32_page; else if (ic_lsize == 64) @@ -261,6 +263,9 @@ static void r4k_blast_icache_page_indexed_setup(void) else if (TX49XX_ICACHE_INDEX_INV_WAR) r4k_blast_icache_page_indexed = tx49_blast_icache32_page_indexed; + else if (current_cpu_type() == CPU_LOONGSON2) + r4k_blast_icache_page_indexed = + loongson2_blast_icache32_page_indexed; else r4k_blast_icache_page_indexed = blast_icache32_page_indexed; @@ -284,6 +289,8 @@ static void r4k_blast_icache_setup(void) r4k_blast_icache = blast_r4600_v1_icache32; else if (TX49XX_ICACHE_INDEX_INV_WAR) r4k_blast_icache = tx49_blast_icache32; + else if (current_cpu_type() == CPU_LOONGSON2) + r4k_blast_icache = loongson2_blast_icache32; else r4k_blast_icache = blast_icache32; } else if (ic_lsize == 64) |