diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2020-06-29 06:18:38 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-07-17 16:06:16 +0200 |
| commit | 5c9b969f699979981b1a2008cef76b56cf906f3e (patch) | |
| tree | b2a58dc9ad1a06c49847bbcc9f4918f45f43dc3f | |
| parent | 2c2a291d01efdcf336796557de1f651b2581e08d (diff) | |
drm/tegra: gr2d: Add tiled PATBASE address register
There are two PATBASE address registers, one for linear layout and other
for tiled. The driver's address registers list misses the tiled PATBASE
register.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/gpu/drm/tegra/gr2d.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/gr2d.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c index 48363f744bb9..1a0d3ba6e525 100644 --- a/drivers/gpu/drm/tegra/gr2d.c +++ b/drivers/gpu/drm/tegra/gr2d.c @@ -177,6 +177,7 @@ static const u32 gr2d_addr_regs[] = { GR2D_DSTC_BASE_ADDR, GR2D_SRCA_BASE_ADDR, GR2D_SRCB_BASE_ADDR, + GR2D_PATBASE_ADDR, GR2D_SRC_BASE_ADDR_SB, GR2D_DSTA_BASE_ADDR_SB, GR2D_DSTB_BASE_ADDR_SB, diff --git a/drivers/gpu/drm/tegra/gr2d.h b/drivers/gpu/drm/tegra/gr2d.h index 2398486f0699..9b7d66e15b9f 100644 --- a/drivers/gpu/drm/tegra/gr2d.h +++ b/drivers/gpu/drm/tegra/gr2d.h @@ -14,6 +14,7 @@ #define GR2D_DSTC_BASE_ADDR 0x2d #define GR2D_SRCA_BASE_ADDR 0x31 #define GR2D_SRCB_BASE_ADDR 0x32 +#define GR2D_PATBASE_ADDR 0x47 #define GR2D_SRC_BASE_ADDR_SB 0x48 #define GR2D_DSTA_BASE_ADDR_SB 0x49 #define GR2D_DSTB_BASE_ADDR_SB 0x4a |