spice/qemu - Qemu (mirrored from https://gitlab.freedesktop.org/spice/qemu)

Age	Commit message (Expand)	Author	Files	Lines
2019-02-11	target/riscv: fix counter-enable checks in ctr()	Xi Wang	1	-3/+9
2019-02-11	RISC-V: Add misa runtime write support	Michael Clark	4	-3/+68
2019-02-11	RISC-V: Add misa.MAFD checks to translate	Michael Clark	1	-0/+158
2019-02-11	RISC-V: Add misa to DisasContext	Michael Clark	1	-35/+40
2019-02-11	RISC-V: Add priv_ver to DisasContext	Alistair Francis	1	-2/+5
2019-02-11	RISC-V: Use riscv prefix consistently on cpu helpers	Michael Clark	5	-37/+36
2019-02-11	RISC-V: Implement mstatus.TSR/TW/TVM	Michael Clark	2	-8/+34
2019-02-11	RISC-V: Mark mstatus.fs dirty	Richard Henderson	2	-13/+39
2019-02-11	RISC-V: Split out mstatus_fs from tb_flags	Richard Henderson	2	-8/+8
2019-01-09	RISC-V: Implement existential predicates for CSRs	Michael Clark	4	-79/+105
2019-01-09	RISC-V: Implement atomic mip/sip CSR updates	Michael Clark	1	-28/+28
2019-01-08	RISC-V: Implement modular CSR helper interface	Michael Clark	6	-606/+904
2019-01-03	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1'...	Peter Maydell	3	-11/+13
2018-12-20	riscv/cpu: use device_class_set_parent_realize	Mao Zhongyi	1	-2/+2
2018-12-20	target/riscv/pmp.c: Fix pmp_decode_napot()	Anup Patel	1	-1/+1
2018-12-20	RISC-V: Add hartid and \n to interrupt logging	Michael Clark	1	-8/+10
2018-12-20	Clean up includes	Markus Armbruster	1	-1/+0
2018-11-13	RISC-V: Respect fences for user-only emulators	Palmer Dabbelt	1	-2/+0
2018-11-13	target/riscv: Fix sfence.vm/a both available in any priv version	Bastian Koppelmann	1	-5/+13
2018-11-13	target/riscv: Fix FCLASS_D being treated as RV64 only	Bastian Koppelmann	1	-1/+3
2018-10-30	target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64	Dayeol Lee	1	-1/+1
2018-10-17	RISC-V: Update CSR and interrupt definitions	Michael Clark	3	-321/+370
2018-10-17	RISC-V: Move non-ops from op_helper to cpu_helper	Michael Clark	3	-36/+35
2018-10-17	RISC-V: Allow setting and clearing multiple irqs	Michael Clark	2	-18/+28
2018-09-05	riscv: remove define cpu_init()	Igor Mammedov	1	-1/+0
2018-09-05	target/riscv: call gen_goto_tb on DISAS_TOO_MANY	Emilio G. Cota	1	-6/+1
2018-09-05	target/riscv: optimize indirect branches	Emilio G. Cota	1	-1/+1
2018-09-05	target/riscv: optimize cross-page direct jumps in softmmu	Emilio G. Cota	1	-1/+1
2018-09-04	RISC-V: Simplify riscv_cpu_local_irqs_pending	Michael Clark	1	-22/+12
2018-09-04	RISC-V: Improve page table walker spec compliance	Michael Clark	2	-21/+45
2018-09-04	RISC-V: Update address bits to support sv39 and sv48	Michael Clark	1	-4/+4
2018-06-08	RISC-V: Add trailing '\n' to qemu_log() calls	Philippe Mathieu-Daudé	1	-2/+4
2018-06-01	tcg: Pass tb and index to tcg_gen_exit_tb separately	Richard Henderson	1	-10/+10
2018-05-31	Make address_space_translate{, _cached}() take a MemTxAttrs argument	Peter Maydell	1	-1/+1
2018-05-18	target/riscv: Honor CPU_DUMP_FPU	Richard Henderson	1	-5/+7
2018-05-17	target/riscv: Remove floatX_maybe_silence_nan from conversions	Richard Henderson	1	-4/+2
2018-05-11	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...	Peter Maydell	1	-49/+17
2018-05-10	target/riscv: Use new atomic min/max expanders	Richard Henderson	1	-49/+17
2018-05-09	target/riscv: convert to TranslatorOps	Emilio G. Cota	1	-78/+80
2018-05-09	target/riscv: convert to DisasContextBase	Emilio G. Cota	1	-65/+64
2018-05-09	target/riscv: convert to DisasJumpType	Emilio G. Cota	1	-44/+28
2018-05-09	target/riscv: avoid integer overflow in next_page PC check	Emilio G. Cota	1	-3/+3
2018-05-06	RISC-V: No traps on writes to misa,minstret,mcycle	Michael Clark	1	-12/+13
2018-05-06	RISC-V: Make mtvec/stvec ignore vectored traps	Michael Clark	1	-6/+8
2018-05-06	RISC-V: Add mcycle/minstret support for -icount auto	Michael Clark	2	-2/+28
2018-05-06	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10	Michael Clark	2	-18/+50
2018-05-06	RISC-V: Allow S-mode mxr access when priv ISA >= v1.10	Michael Clark	1	-2/+5
2018-05-06	RISC-V: Clear mtval/stval on exceptions without info	Michael Clark	1	-0/+8
2018-05-06	RISC-V: Hardwire satp to 0 for no-mmu case	Michael Clark	1	-2/+5
2018-05-06	RISC-V: Update E and I extension order	Michael Clark	2	-1/+2