spice/qemu - Qemu (mirrored from https://gitlab.freedesktop.org/spice/qemu)

Age	Commit message (Expand)	Author	Files	Lines
2019-05-06	decodetree: Add DisasContext argument to !function expanders	Richard Henderson	2	-7/+7
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson	1	-2/+2
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	1	-19/+18
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	2	-14/+5
2019-03-26	target/riscv: Fix wrong expanding for c.fswsp	Kito Cheng	1	-1/+1
2019-03-22	target/riscv: Zero extend the inputs of divuw and remuw	Palmer Dabbelt	2	-2/+23
2019-03-19	target/riscv: Remove unused struct	Alistair Francis	1	-6/+0
2019-03-19	RISC-V: Update load reservation comment in do_interrupt	Michael Clark	1	-1/+7
2019-03-19	RISC-V: Convert trap debugging to trace events	Michael Clark	2	-9/+5
2019-03-19	RISC-V: Add support for vectored interrupts	Michael Clark	2	-97/+60
2019-03-19	RISC-V: Change local interrupts from edge to level	Michael Clark	1	-2/+2
2019-03-19	RISC-V: linux-user support for RVE ABI	Kito Cheng	2	-1/+6
2019-03-19	RISC-V: Allow interrupt controllers to claim interrupts	Michael Clark	3	-8/+15
2019-03-19	riscv: pmp: Log pmp access errors as guest errors	Alistair Francis	1	-7/+13
2019-03-19	RISC-V: Add hooks to use the gdb xml files.	Jim Wilson	3	-12/+349
2019-03-19	RISC-V: Add debug support for accessing CSRs.	Jim Wilson	2	-7/+30
2019-03-19	RISC-V: Fixes to CSR_* register macros.	Jim Wilson	1	-2/+33
2019-03-17	target/riscv: Fix manually parsed 16 bit insn	Bastian Koppelmann	1	-5/+25
2019-03-13	target/riscv: Remove decode_RV32_64G()	Bastian Koppelmann	1	-20/+1
2019-03-13	target/riscv: Remove gen_system()	Bastian Koppelmann	1	-34/+0
2019-03-13	target/riscv: Rename trans_arith to gen_arith	Bastian Koppelmann	3	-18/+18
2019-03-13	target/riscv: Remove manual decoding of RV32/64M insn	Bastian Koppelmann	2	-211/+164
2019-03-13	target/riscv: Remove shift and slt insn manual decoding	Bastian Koppelmann	2	-71/+81
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann	3	-30/+34
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann	3	-100/+108
2019-03-13	target/riscv: Remove manual decoding from gen_store()	Bastian Koppelmann	2	-11/+24
2019-03-13	target/riscv: Remove manual decoding from gen_load()	Bastian Koppelmann	2	-16/+25
2019-03-13	target/riscv: Remove manual decoding from gen_branch()	Bastian Koppelmann	2	-60/+33
2019-03-13	target/riscv: Remove gen_jalr()	Bastian Koppelmann	2	-39/+27
2019-03-13	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	Bastian Koppelmann	3	-81/+134
2019-03-13	target/riscv: Convert quadrant 1 of RVXC insns to decodetree	Bastian Koppelmann	3	-117/+195
2019-03-13	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	Bastian Koppelmann	4	-38/+154
2019-03-13	target/riscv: Convert RV priv insns to decodetree	Bastian Koppelmann	3	-56/+126
2019-03-13	target/riscv: Convert RV64D insns to decodetree	Bastian Koppelmann	3	-600/+91
2019-03-13	target/riscv: Convert RV32D insns to decodetree	Bastian Koppelmann	3	-0/+389
2019-03-13	target/riscv: Convert RV64F insns to decodetree	Bastian Koppelmann	2	-0/+66
2019-03-13	target/riscv: Convert RV32F insns to decodetree	Bastian Koppelmann	3	-0/+415
2019-03-13	target/riscv: Convert RV64A insns to decodetree	Bastian Koppelmann	3	-144/+71
2019-03-13	target/riscv: Convert RV32A insns to decodetree	Bastian Koppelmann	3	-0/+178
2019-03-13	target/riscv: Convert RVXM insns to decodetree	Bastian Koppelmann	4	-9/+137
2019-03-13	target/riscv: Convert RVXI csr insns to decodetree	Bastian Koppelmann	3	-42/+88
2019-03-13	target/riscv: Convert RVXI fence insns to decodetree	Bastian Koppelmann	3	-12/+21
2019-03-13	target/riscv: Convert RVXI arithmetic insns to decodetree	Bastian Koppelmann	4	-9/+206
2019-03-13	target/riscv: Convert RV64I load/store insns to decodetree	Bastian Koppelmann	4	-10/+50
2019-03-13	target/riscv: Convert RV32I load/store insns to decodetree	Bastian Koppelmann	2	-0/+58
2019-03-13	target/riscv: Convert RVXI branch insns to decodetree	Bastian Koppelmann	3	-11/+69
2019-03-13	target/riscv: Activate decodetree and implemnt LUI & AUIPC	Bastian Koppelmann	4	-14/+92
2019-02-11	target/riscv: fix counter-enable checks in ctr()	Xi Wang	1	-3/+9
2019-02-11	RISC-V: Add misa runtime write support	Michael Clark	4	-3/+68
2019-02-11	RISC-V: Add misa.MAFD checks to translate	Michael Clark	1	-0/+158