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2019-02-27target/mips: Preparing for adding MMI instructionsMateja Marjanovic1-2/+41
2019-02-21target/mips: implement QMP query-cpu-definitions commandPavel Dovgalyuk1-0/+33
2019-02-14target/mips: introduce MTTCG-enabled buildsAleksandar Markovic1-0/+2
2019-02-14target/mips: hold BQL in mips_vpe_wake()Goran Ferenc1-0/+3
2019-02-14hw/mips_int: hold BQL for all interrupt requestsAleksandar Markovic1-18/+3
2019-02-14target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae5-118/+44
2019-02-14target/mips: compare virtual addresses in LL/SC sequenceLeon Alrae4-18/+25
2019-01-24target/mips: Add I6500 core configurationYongbok Kim1-0/+40
2019-01-24target/mips: nanoMIPS: Fix branch handlingStefan Markovic1-0/+12
2019-01-24target/mips: Extend gen_scwp() functionality to support EVAAleksandar Markovic1-4/+6
2019-01-24target/mips: Correct the second argument type of cpu_supports_isa()Aleksandar Markovic2-2/+2
2019-01-24target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbersAleksandar Markovic1-13/+13
2019-01-24target/mips: nanoMIPS: Remove an unused macroAleksandar Markovic1-1/+0
2019-01-24target/mips: nanoMIPS: Remove duplicate macro definitionsAleksandar Markovic1-10/+0
2019-01-18target/mips: Introduce 32 R5900 multimedia registersFredrik Noring2-0/+19
2019-01-18target/mips: Rename 'rn' to 'register_name'Aleksandar Markovic1-426/+432
2019-01-18target/mips: Add CP0 register MemoryMapIDAleksandar Markovic2-2/+4
2019-01-18target/mips: Amend preprocessor constants for CP0 registersAleksandar Markovic2-170/+284
2019-01-18target/mips: Update ITU to utilize SAARI and SAAR CP0 registersYongbok Kim2-0/+19
2019-01-18target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim5-4/+120
2019-01-18target/mips: Add fields for SAARI and SAAR CP0 registersYongbok Kim2-4/+12
2019-01-18target/mips: Use preprocessor constants for 32 major CP0 registersAleksandar Markovic1-136/+136
2019-01-18target/mips: Add preprocessor constants for 32 major CP0 registersAleksandar Markovic1-0/+32
2019-01-18target/mips: Move comment containing summary of CP0 registersAleksandar Markovic1-81/+84
2019-01-11avoid TABs in files that only contain a fewPaolo Bonzini1-1/+1
2019-01-03target/mips: Support R5900 three-operand MADD1 and MADDU1 instructionsFredrik Noring1-3/+9
2019-01-03target/mips: Support R5900 three-operand MADD and MADDU instructionsPhilippe Mathieu-Daudé1-5/+53
2019-01-03target/mips: MXU: Add handler for an align instructionAleksandar Markovic1-3/+194
2019-01-03target/mips: MXU: Add handlers for max/min instructionsAleksandar Markovic1-21/+279
2019-01-03target/mips: MXU: Add handlers for logic instructionsAleksandar Markovic1-34/+205
2019-01-03target/mips: MXU: Improve the comment containing MXU overviewAleksandar Markovic1-30/+44
2019-01-03target/mips: MXU: Add generic naming for optn2 constantsAleksandar Markovic1-0/+5
2019-01-03target/mips: MXU: Add missing opcodes/decoding for LX* instructionsAleksandar Markovic1-38/+102
2018-11-27vmstate: constify VMStateFieldMarc-André Lureau1-6/+8
2018-11-17target/mips: Disable R5900 supportAleksandar Markovic1-59/+0
2018-11-17target/mips: Rename MMI-related functionsAleksandar Markovic1-16/+16
2018-11-17target/mips: Rename MMI-related opcodesAleksandar Markovic1-236/+236
2018-11-17target/mips: Rename MMI-related masksAleksandar Markovic1-10/+10
2018-11-17target/mips: Guard check_insn with INSN_R5900 checkFredrik Noring1-3/+6
2018-11-17target/mips: Guard check_insn_opc_user_only with INSN_R5900 checkFredrik Noring1-4/+12
2018-11-17target/mips: Fix decoding mechanism of special R5900 opcodesFredrik Noring1-4/+50
2018-11-17target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1Fredrik Noring1-6/+59
2018-11-17target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1Fredrik Noring1-11/+40
2018-10-29target/mips: Amend MXU ASE overview noteAleksandar Markovic1-10/+74
2018-10-29target/mips: Move MXU_EN check one level higherAleksandar Markovic1-271/+238
2018-10-29target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek1-7/+47
2018-10-29target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSUCraig Janeczek1-7/+94
2018-10-29target/mips: Add emulation of MXU instruction D16MACCraig Janeczek1-3/+87
2018-10-29target/mips: Add emulation of MXU instruction D16MULCraig Janeczek1-3/+63
2018-10-29target/mips: Add emulation of MXU instruction S8LDDCraig Janeczek1-3/+87
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