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path: root/target-sparc/machine.c
AgeCommit message (Expand)AuthorFilesLines
2016-01-29sparc: Clean up includesPeter Maydell1-0/+1
2016-01-16target-sparc: Migrate CWP and PIL for SPARC64Peter Maydell1-1/+4
2016-01-16target-sparc: Use VMState arrays for SPARC64 TLB/MMU statePeter Maydell1-295/+19
2016-01-16target-sparc: Convert to VMStateDescriptionJuan Quintela1-197/+444
2016-01-16target-sparc: Don't flush TLB in cpu_load functionPeter Maydell1-2/+0
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-1/+2
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
2012-03-14target-sparc: Don't overuse CPUStateAndreas Färber1-2/+2
2011-10-26target-sparc: Change fpr representation to doubles.Richard Henderson1-14/+6
2011-06-26Remove exec-all.h include directivesBlue Swirl1-1/+1
2011-06-26Sparc32: dummy implementation of MXCC MMU breakpoint registersBlue Swirl1-0/+26
2010-05-09sparc: Fix lazy flag calculation on interrupts, refactorBlue Swirl1-2/+2
2010-01-27sparc64: reimplement tick timers v4Igor V. Kovalenko1-7/+7
2009-08-04Sparc64: replace tsptr with helper routineIgor Kovalenko1-1/+0
2009-07-27sparc64 name mmu registers and general cleanupIgor Kovalenko1-8/+8
2009-05-21Convert machine registration to use module init functionsAnthony Liguori1-22/+0
2008-12-13Remove unnecessary trailing newlinesblueswir11-2/+0
2008-09-26Add a generic Niagara machineblueswir11-0/+1
2008-08-01Handle wrapped registers correctly when savingblueswir11-1/+11
2008-07-25Make MAXTL dynamic, bounds check tl when indexingblueswir11-5/+5
2008-07-24Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir11-3/+109
2008-07-22Add T1 and T2 CPUs, add a Sun4v machineblueswir11-0/+1
2008-06-07Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir11-2/+6
2008-05-04remove target ifdefs from vl.caurel321-0/+102
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