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AgeCommit message (Expand)AuthorFilesLines
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini2-5/+2
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+0
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2-1/+1
2014-06-05softmmu: make do_unaligned_access a method of CPUPaolo Bonzini3-6/+8
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson5-12/+5
2014-03-27target-mips: Avoid shifting left into sign bitPeter Maydell4-17/+17
2014-03-25target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 modePetar Jovanovic1-35/+44
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber3-3/+6
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber1-2/+6
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber2-3/+12
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-2/+2
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-3/+4
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber3-3/+4
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber3-20/+24
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber4-11/+16
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2-28/+30
2014-02-10target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic4-10/+56
2014-02-10target-mips: add support for CP0_Config5Petar Jovanovic5-3/+40
2014-02-10target-mips: add support for CP0_Config4Petar Jovanovic5-3/+31
2014-02-10target-mips: add CPU definition for MIPS32R5Petar Jovanovic2-0/+33
2013-12-21target-mips: Use new qemu_ld/st opcodesAurelien Jarno1-67/+52
2013-12-09target-mips: Use macro ARRAY_SIZE where possibleStefan Weil1-18/+12
2013-12-09target-mips: fix 64-bit FPU config for user-mode emulationPetar Jovanovic1-2/+5
2013-12-02misc: Replace 'struct QEMUTimer' by 'QEMUTimer'Stefan Weil1-1/+1
2013-10-11Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori2-10/+6
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-6/+6
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-4/+0
2013-10-07cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber1-1/+0
2013-09-03cpu: Use QTAILQ for CPU listAndreas Färber1-6/+4
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-08-28target-mips: fix get_physical_address() #if 0 build errorJames Hogan1-1/+1
2013-08-06target-mips: fix decoding of microMIPS POOL32Axf instructionsLeon Alrae1-6/+54
2013-08-03target-mips: fix 34Kf configuration for DSP ASEYongbok Kim1-4/+3
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber1-2/+3
2013-07-29target-mips: fix mipsdsp_mul_q31_q31Petar Jovanovic1-1/+1
2013-07-29target-mips: Remove assignment to a variable which is never usedStefan Weil1-1/+0
2013-07-29target-mips: fix mipsdsp_trunc16_sat16_roundPetar Jovanovic1-5/+11
2013-07-28target-mips: fix branch in likely delay slot tcg assertJames Hogan1-45/+17
2013-07-28target-mips: fix multiplication in mipsdsp_rndq15_mul_q15_q15Petar Jovanovic1-2/+2
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber4-2/+15
2013-07-27gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber1-14/+17
2013-07-26target-mips: Move cpu_gdb_{read,write}_register()Andreas Färber1-0/+144
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber1-0/+2
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber3-3/+10
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-4/+7
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2-7/+11
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber1-0/+14
2013-07-09cpu: Move reset logging to CPUStateAndreas Färber1-5/+0
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