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AgeCommit message (Expand)AuthorFilesLines
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl5-1085/+1162
2012-09-08MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki3-62/+52
2012-08-27target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson1-1/+9
2012-08-27target-mips: add privilege level check to several Cop0 instructionsEric Johnson1-0/+9
2012-08-27mips-linux-user: Always support rdhwr.Richard Henderson1-0/+4
2012-08-27target-mips: Streamline indexed cp1 memory addressing.Richard Henderson1-2/+1
2012-08-27Fix order of CVT.PS.S operandsRichard Sandiford1-1/+1
2012-08-27Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford1-2/+2
2012-08-24target-mips: Fix some helper functions (VR54xx multiplication)Stefan Weil1-46/+29
2012-08-23target-mips: Enable access to required RDHWR hardware registersMeador Inge1-2/+3
2012-08-09MIPS: Correct FCR0 initializationNathan Froyd1-0/+1
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini1-1/+2
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini1-1/+3
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini1-0/+1
2012-06-04Kill off cpu_state_reset()Andreas Färber1-0/+3
2012-06-04target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber2-4/+12
2012-06-04target-mips: Use cpu_reset() in do_interrupt()Andreas Färber1-1/+2
2012-06-04target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber1-1/+1
2012-05-19mips: Fix BC1ANY[24]F instructionsRichard Sandiford1-4/+4
2012-05-12target-mips: Remove commented-out function declarationAndreas Färber1-1/+0
2012-05-03target-mips: Remove unused inline functionStefan Weil1-6/+0
2012-05-01Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpuBlue Swirl4-2/+148
2012-04-30target-mips: Start QOM'ifying CPU initAndreas Färber2-1/+9
2012-04-30target-mips: QOM'ify CPUAndreas Färber4-1/+139
2012-04-28target-mips: Move definition of uint_fast{8, 16}_t to osdep.hAndreas Färber1-7/+0
2012-04-15target-mips: Fix type cast for w64 (uintptr_t)Stefan Weil1-1/+1
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-10/+8
2012-04-07Replace Qemu by QEMU in commentsStefan Weil1-1/+1
2012-04-07Replace Qemu by QEMU in internal documentationStefan Weil1-2/+2
2012-03-24target-mips: Add compiler attribute to some functions which don't returnStefan Weil2-3/+4
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
2012-03-14target-mips: Don't overuse CPUStateAndreas Färber5-274/+274
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber2-3/+3
2012-03-08Spelling fixes in comments (it's -> its)Stefan Weil1-1/+1
2012-02-28target-mips: Clean includesStefan Weil1-7/+0
2011-12-14Fix spelling in comments, documentation and messagesStefan Weil1-1/+1
2011-12-02fix spelling in target sub directoryDong Xu Wang2-2/+2
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl1-4/+3
2011-09-06mips: Support the MT TCStatus IXMT irq disable flagEdgar E. Iglesias1-0/+4
2011-09-06mips: Add MT halting and waking of VPEsEdgar E. Iglesias2-4/+129
2011-09-06mips: Initialize MT state at resetEdgar E. Iglesias1-0/+26
2011-09-06mips: Default to using one VPE and one TC.Edgar E. Iglesias1-1/+1
2011-09-06mips: Enable VInt interrupt mode for the 34KfEdgar E. Iglesias1-1/+1
2011-09-06mips: Correct VInt vector generationEdgar E. Iglesias1-3/+3
2011-09-06mips: Correct IntCtl write mask for VIntEdgar E. Iglesias1-1/+1
2011-09-06mips: Hook in more reg accesses via mttr/mftrEdgar E. Iglesias3-11/+225
2011-09-06mips: Synchronize CP0 TCSTatus, Status and EntryHiEdgar E. Iglesias1-44/+106
2011-09-06mips: Handle TC indexing of other VPEsEdgar E. Iglesias1-105/+161
2011-08-20Use glib memory allocation and free functionsAnthony Liguori2-3/+3
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl3-5/+5
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