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authormalc <malc@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-23 20:01:23 +0000
committermalc <malc@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-23 20:01:23 +0000
commite46b9681e5d69f632c4edc8dc2571cb0f68ee165 (patch)
tree4a572b39e4716aed2583bfdf09a56fbeba069e6a /tcg/ppc64
parent1d58ee9f3b9fa56639ab28a7756ee4c27ccd463c (diff)
Provide extNs_M instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tcg/ppc64')
-rw-r--r--tcg/ppc64/tcg-target.c23
-rw-r--r--tcg/ppc64/tcg-target.h5
2 files changed, 28 insertions, 0 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index a2b6aad5ef..0967b95d5b 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -969,6 +969,8 @@ void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
const int *const_args)
{
+ int c;
+
switch (opc) {
case INDEX_op_exit_tb:
tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
@@ -1313,6 +1315,21 @@ static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
tcg_out_qemu_st (s, args, 3);
break;
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ c = EXTSB;
+ goto gen_ext;
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ c = EXTSH;
+ goto gen_ext;
+ case INDEX_op_ext32s_i64:
+ c = EXTSW;
+ goto gen_ext;
+ gen_ext:
+ tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
+ break;
+
default:
tcg_dump_ops (s, stderr);
tcg_abort ();
@@ -1404,6 +1421,12 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_st32, { "K", "K" } },
{ INDEX_op_qemu_st64, { "M", "M", "M" } },
+ { INDEX_op_ext8s_i32, { "r", "r" } },
+ { INDEX_op_ext16s_i32, { "r", "r" } },
+ { INDEX_op_ext8s_i64, { "r", "r" } },
+ { INDEX_op_ext16s_i64, { "r", "r" } },
+ { INDEX_op_ext32s_i64, { "r", "r" } },
+
{ -1 },
};
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 98d66cd92e..66feb4d5af 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -72,6 +72,11 @@ enum {
#define TCG_TARGET_HAS_div_i32
#define TCG_TARGET_HAS_neg_i64
#define TCG_TARGET_HAS_div_i64
+#define TCG_TARGET_HAS_ext8s_i32
+#define TCG_TARGET_HAS_ext16s_i32
+#define TCG_TARGET_HAS_ext8s_i64
+#define TCG_TARGET_HAS_ext16s_i64
+#define TCG_TARGET_HAS_ext32s_i64
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24