diff options
author | Andreas Färber <afaerber@suse.de> | 2013-01-16 03:31:27 +0100 |
---|---|---|
committer | Andreas Färber <afaerber@suse.de> | 2013-02-16 14:50:57 +0100 |
commit | 9c23169e8cd54b490d55221b6498d42966f964f3 (patch) | |
tree | 9b042a27c4493c73b92c8a858d1630743728856f /target-lm32 | |
parent | ca45f8b0440358ccca63446cf0df05772791b2a1 (diff) |
target-lm32: Introduce QOM realizefn for LM32CPU
Introduce a realizefn and set realized = true in cpu_lm32_init().
Also move cpu_reset() call from initfn to realizefn.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-lm32')
-rw-r--r-- | target-lm32/cpu-qom.h | 2 | ||||
-rw-r--r-- | target-lm32/cpu.c | 18 | ||||
-rw-r--r-- | target-lm32/helper.c | 4 |
3 files changed, 20 insertions, 4 deletions
diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h index 400cdbd554..d7525b300c 100644 --- a/target-lm32/cpu-qom.h +++ b/target-lm32/cpu-qom.h @@ -34,6 +34,7 @@ /** * LM32CPUClass: + * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * * A LatticeMico32 CPU model. @@ -43,6 +44,7 @@ typedef struct LM32CPUClass { CPUClass parent_class; /*< public >*/ + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } LM32CPUClass; diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index eca2dca427..6a84f51bf9 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -42,6 +42,18 @@ static void lm32_cpu_reset(CPUState *s) memset(env, 0, offsetof(CPULM32State, breakpoints)); } +static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) +{ + LM32CPU *cpu = LM32_CPU(dev); + LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev); + + cpu_reset(CPU(cpu)); + + qemu_init_vcpu(&cpu->env); + + lcc->parent_realize(dev, errp); +} + static void lm32_cpu_initfn(Object *obj) { LM32CPU *cpu = LM32_CPU(obj); @@ -50,14 +62,16 @@ static void lm32_cpu_initfn(Object *obj) cpu_exec_init(env); env->flags = 0; - - cpu_reset(CPU(cpu)); } static void lm32_cpu_class_init(ObjectClass *oc, void *data) { LM32CPUClass *lcc = LM32_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + lcc->parent_realize = dc->realize; + dc->realize = lm32_cpu_realizefn; lcc->parent_reset = cc->reset; cc->reset = lm32_cpu_reset; diff --git a/target-lm32/helper.c b/target-lm32/helper.c index d76ea3fe09..a6691addba 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -212,13 +212,13 @@ LM32CPU *cpu_lm32_init(const char *cpu_model) env->num_wps = def->num_watchpoints; env->cfg = cfg_by_def(def); - qemu_init_vcpu(env); - if (tcg_enabled() && !tcg_initialized) { tcg_initialized = 1; lm32_translate_init(); } + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); + return cpu; } |